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Reset Value (hex) Reg. Descr. 7 6 5 4 3 2 10 with Link 80 RESERVED 81 SP SP[7:0] 07 Stack Pointer (SP), page 21 82 DPL DPL[7:0] 00 Data Pointer (DPTR), p age 21 83 DPH DPH[7:0] 00 84 RESERVED 85 DPTC – AT – – – DPSEL[2:0] 00 Table 13., page 37 86 DPTM – – – – MD1[1:0] MD0[1:0] 00 Table 14., page 38 87 PCON SMOD0 SMOD1 – POR RCLK1 TCLK1 PD IDLE 00 Table 24., page 50 88(1) TCON TF1 <8Fh> TR1 <8Eh> TF0 <8Dh> TR0 <8Ch> IE1 <8Bh> IT1 <8Ah> IE0 <89h> IT0 <88h> 00 Table 39., page 70 89 TMOD GATE C/T M1 M0 GATE C/T M1 M0 00 Table 40., page 72 8A TL0 TL0[7:0] 00 Standard Timer SFRs, pag e 69 8B TL1 TL1[7:0] 00 8C TH0 TH0[7:0] 00 8D TH1 TH1[7:0] 00 8E P1SFS0 P1SFS0[7:0] 00 Table 29., page 60 8F P1SFS1 P1SFS1[7:0] 00 Table 30., page 60 90(1) P1 P1.7 <97h> P1.6 <96h> P1.5 <95h> P1.4 <94h> P1.3 <93h> P1.2 <92h> P1.1 <91h> P1.0 <90h> FF Table 25., page 57 91 P3SFS P3SFS[7:0] 00 Table 28., page 60 92 P4SFS0 P4SFS0[7:0] 00 Table 32., page 61 93 P4SFS1 P4SFS1[7:0] 00 Table 33., page 6125/231 uPSD33xx 94 ADCPS – – – – ADCCE ADCPS[2:0] 00 Table 64., page 122 95 ADAT0 ADATA[7:0] 00 Table 65., page 122 96 ADAT1 – – – – – – ADATA[9:8] 00 Table 66., page 122 97 ACON AINTF AINTEN ADEN ADS[2:0] ADST ADSF 00 Table 63., page 121 98(1) SCON0 SM0 <9Fh> SM1 <9Eh> SM2 <9Dh> REN <9Ch> TB8 <9Bh> RB8 <9Ah> TI <99h> RI <9h8> 00 Table 45., page 82 99 SBUF0 SBUF0[7:0] 00 Figure 25., page 79 9A RESERVED 9B RESERVED 9C RESERVED 9D BUSCON EPFQ EBC WRW1 WRW0 RDW1 RDW0 CW1 CW0 EB Table 35., page 63 9E RESERVED 9F RESERVED A0 RESERVED A1 RESERVED A2 PCACL0 PCACL0[7:0] 00 Table 67., page 124 A3 PCACH0 PCACH0[7:0] 00 Table 67., page 124 A4 PCACON0 EN_ALL EN_PCA EOVF1 PCA_IDL – – CLK_SEL[1:0] 00 Table 70., page 129 A5 PCASTA OVF1 INTF5 INTF4 INTF3 OVF0 INTF2 INTF1 INTF0 00 Table 72., page 131 A6 WDTRST WDTRST[7:0] 00 Table 38., page 68 A7 IEA EADC ESPI EPCA ES1 – – EI2C – 00 Table 18., page 44 SFR Addr (hex) SFR Name Bit Name and Reset Value (hex) Reg. Descr. 7 6 5 4 3 2 10 with LinkuPSD33xx 26/231 A8(1) IE EA – ET2 ES0 ET1 EX1 ET0 EX0 00 Table 17., page 43 A9 TCMMODE 0 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00 Table 73., page 132 AA TCMMODE 1 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00 AB TCMMODE 2 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00 AC CAPCOML 0 CAPCOML0[7:0] 00 Table 67., page 124 AD CAPCOMH 0 CAPCOMH0[7:0] 00 AE WDTKEY WDTKEY[7:0] 55 Table 37., page 68 AF CAPCOML 1 CAPCOML1[7:0] 00 Table 67., page 124 B0(1) P3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 FF Table 26., page 58 B1 CAPCOMH 1 CAPCOMH1[7:0] 00 Table 67., page 124 B2 CAPCOML 2 CAPCOML2[7:0] 00 B3 CAPCOMH 2 CAPCOMH2[7:0] 00 B4 PWMF0 PWMF0[7:0] 00 B5 RESERVED B6 RESERVED B7 IPA PADC PSPI PPCA PS1 – – PI2C – 00 Table 20., page 45 B8(1) IP – – PT2 PS0 PT1 PX1 PT0 PX0 00 Table 19., page 44 B9 RESERVED BA PCACL1 PCACL1[7:0] 00 Table 67., page BB PCACH1 PCACH1[7:0] 00 124 BC Table 2671 page 12027/231 uPSD33xx BD TCMMODE 3 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00 Table 73., page 132 BE TCMMODE 4 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00 BF TCMMODE 5 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00 C0(1) P4 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 FF Table 27., page 58 C1 CAPCOML 3 CAPCOML3[7:0] 00 Table 67., page 124 C2 CAPCOMH 3 CAPCOMH3[7:0] 00 C3 CAPCOML 4 CAPCOML4[7:0] 00 C4 CAPCOMH 4 CAPCOMH4[7:0] 00 C5 CAPCOML 5 CAPCOML5[7:0] 00 C6 CAPCOMH 5 CAPCOMH5[7:0] 00 C7 PWMF1 PWMF1[7:0] 00 C8(1) T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/ RL2 00 Table 41., page 75 C9 RESERVED CA RCAP2L RCAP2L[7:0] 00 Standard Timer SFRs, pag e 69 CB RCAP2H RCAP2H[7:0] 00 CC TL2 TL2[7:0] 00 CD TH2 TH2[7:0] 00 CE IRDACON – IRDA_EN BIT_PULS CDIV4 CDIV3 CDIV2 CDIV1 CDIV0 0F Table 48., page 93 D0(1) PSW CY AC F0 RS[1:0] OV – P 00 Program Status Word (PSW), pa ge 22 D1 RESERVED D2 SPICLKD SPICLKD[5:0] – – 04 Table 61., page 118 D3 SPISTAT – – – BUSY TEISF RORISF TISF RISF 02 Table 62., page 119 SFR Addr (hex) SFR Name Bit Name and Reset Value (hex) Reg. Descr. 7 6 5 4 3 2 10 with LinkuPSD33xx 28/231 D4 SPITDR SPITDR[7:0] 00 Table 62., page D5 SPIRDR SPIRDR[7:0] 00 119 D6 SPICON0 – TE RE SPIEN SSEL FLSB SPO – 00 Table 59., page 117 D7 SPICON1 – – – – TEIE RORIE TIE RIE 00 Table 60., page 118 D8(1) SCON1 SM0 SM2

REN TB8 RB8 TI RI 00 Table 46., page 83 D9 SBUF1 SBUF1[7:0] 00 Figure 25., page 79 DA RESERVED DB S1SETUP SS_EN SMPL_SET[6:0] 00 Table 55., page 105 DC S1CON CR2 EN1 STA STO ADDR AA CR1 CR0 00 Table 50., page 100 DD S1STA GC STOP INTR TX_MD B_BUSY B_LOST ACK_R SLV 00 Table 52., page 103 DE S1DAT S1DAT[7:0] 00 Table 53., page 104 DF S1ADR S1ADR[7:0] 00 Table 54., page 104 E0(1) A A[7:0] 00 Accumulat or (ACC), pa ge 21 E1 to EF RESERVED F0(1) B B[7:0] 00 B Register (B), page 21 F1 RESERVED F2 RESERVED F3 RESERVED F4 RESERVED F5 RESERVED F6 RESERVED SFR Addr (hex) SFR Name Bit Name and Reset Value (hex) Reg. Descr. 7 6 5 4 3 2 10 with Link29/231 uPSD33xx Note: 1. This SFR can be addressed by individual bits (Bit Address mode) or addressed by the entire byte (Direct Address mode). F7 RESERVED F8 RESERVED F9 CCON0 – – – DBGCE CPU_AR CPUPS[2:0] 10 Table 21., page 47 FA RESERVED FB CCON2 – – – PCA0CE PCA0PS[3:0] 10 Table 68., page 125 FC CCON3 – – – PCA1CE PCA1PS[3:0] 10 Table 69., page 125 FD RESERVED FE RESERVED FF RESERVED SFR Addr (hex) SFR Name Bit Name and Reset Value (hex) Reg. Descr. 7 6 5 4 3 2 10 with LinkuPSD33xx 30/231 8032 ADDRESSING MODES The 8032 MCU uses 11 different addressing modes listed below: ■ Register ■ Direct ■ Register Indirect ■ Immediate ■ External Direct ■ External Indirect ■ Indexed ■ Relative ■ Absolute ■ Long ■ Bit Register Addressing This mode uses the contents of one of the registers R0 - R7 (selected by the last three bits in the instruction opcode) as the operand source or destination. This mode is very efficient since an additional instruction byte is not needed to identify the operand. For example: Direct Addressing This mode uses an 8-bit address, which is contained in the second byte of the instruction, to directly address an operand which resides in either 8032 DATA SRAM (internal address range 00h- 07Fh) or resides in 8032 SFR (internal address range 80h-FFh). This mode is quite fast since the range limit is 256 bytes of internal 8032 SRAM. For example: Register Indirect Addressing This mode uses an 8-bit address contained in either Register R0 or R1 to indirectly address an operand which resides in 8032 IDATA SRAM (internal address range 80h-FFh). Although 8032 SFR registers also occupy the same physical address range as IDATA, SFRs will not be accessed by Register Indirect mode. SFRs may only be accesses using Direct address mode. For example: Immediate Addressing This mode uses 8-bits of data (a constant) contained in the second byte of the instruction, and stores it into the memory location or register indicated by the first byte of the instruction. Thus, the data is immediately available within the instruction. This mode is commonly used to initialize registers and SFRs or to perform mask operations. There is also a 16-bit version of this mode for loading the DPTR Register. In this case, the two bytes following the instruction byte contain the 16-bit value. For example: External Direct Addressing This mode will access external memory (XDATA) by using the 16-bit address stored in the DPTR Register. There are only two instructions using this mode and both use the accumulator to either receive a byte from external memory addressed by DPTR or to send a byte from the accumulator to the address in DPTR. The uPSD33xx has a special feature to alternate the contents (source and destination) of DPTR rapidly to implement very efficient memory-to-memory transfers. For example: Note: See details in DUAL DATA POINTERS, page 37. External Indirect Addressing This mode will access external memory (XDATA) by using the 8-bit address stored in either Register R0 or R1. This is the fastest way to access XDATA (least bus cycles), but because only 8-bits are available for address, this mode limits XDATA to a size of only 256 bytes (the traditional Port 2 of the 8032 MCU is not available in the uPSD33xx, so it is not possible to write the upper address byte). This mode is not supported by uPSD33xx. For example: MOV A, R7 ; Move contents of R7 to accumulator MOV A, 40h ; Move contents of DATA SRAM ; at location 40h into the accumulator MOV A, @R0 ; Move into the accumulator the ; contents of IDATA SRAM that is ; pointed to by the address ; contained in R0. MOV A, 40# ; Move the constant, 40h, into ; the accumulator MOV DPTR, 1234# ; Move the constant, 1234h, into ; DPTR MOVX A, @DPTR ; Move contents of accumulator to ; XDATA at address contained in ; DPTR MOVX @DPTR, A ; Move XDATA to accumulator MOVX @R0,A ; Move into the accumulator the ; XDATA that is pointed to by ; the address contained in R0.31/231 uPSD33xx Indexed Addressing This mode is used for the MOVC instruction which allows the 8032 to read a constant from program memory (not data memory). MOVC is often used to read look-up tables that are embedded in program memory. The final address produced by this mode is the result of adding either the 16-bit PC or DPTR value to the contents of the accumulator. The value in the accumulator is referred to as an index. The data fetched from the final location in program memory is stored into the accumulator, overwriting the index value that was previously stored there. For example: Relative Addressing This mode will add the two’s-compliment number stored in the second byte of the instruction to the program counter for short jumps within +128 or – 127 addresses relative to the program counter. This is commonly used for looping and is very efficient since no additional bus cycle is needed to fetch the jump destination address. For example: Absolute Addressing This mode will append the 5 high-order bits of the address of the next instruction to the 11 low-order bits of an ACALL or AJUMP instruction to produce a 16-bit jump address. The jump will be within the same 2K byte page of program memory as the first byte of the following instruction. For example: Long Addressing This mode will use the 16-bits contained in the two bytes following the instruction byte as a jump destination address for LCALL and LJMP instructions. For example: Bit Addressing This mode allows setting or clearing an individual bit without disturbing the other bits within an 8-bit value of internal SRAM. Bit Addressing is only available for certain locations in 8032 DATA and SFR memory. Valid locations are DATA addresses 20h - 2Fh and for SFR addresses whose base address ends with 0h or 8h. (Example: The SFR, IE, has a base address of A8h, so each of the eight bits in IE can be addressed individually at address A8h, A9h, ...up to AFh.) For example: MOVC A, @A+DPTR; Move code byte relative to ; DPTR into accumulator MOVC A, @A+PC ; Move code byte relative to PC ; into accumulator SJMP 34h ; Jump 34h bytes ahead (in program ; memory) of the address at which ; the SJMP instruction is stored. If ; SJMP is at 1000h, program ; execution jumps to 1034h. AJMP 0500h ; If next instruction is located at ; address 4000h, the resulting jump ; will be made to 4500h. LJMP 0500h ; Unconditionally jump to address ; 0500h in program memory SETB AFh ; Set the individual EA bit (Enable All ; Interrupts) inside the SFR Register, ; IE. uPSD33xx 32/231 uPSD33xx INSTRUCTION SET SUMMARY Tables 6 through 11 list all of the instructions supported by the uPSD33xx, including the number of bytes and number of machine cycles required to implement each instruction. This is the standard 8051 instruction set. The meaning of “machine cycles” is how many 8032 MCU core machine cycles are required to execute the instruction. The “native” duration of all machine cycles is set by the memory wait state settings in the SFR, BUSCON, and the MCU clock divider selections in the SFR, CCON0 (i.e. a machine cycle is typically set to 4 MCU clocks for a 5V uPSD33xx). However, an individual machine cycle may grow in duration when either of two things happen: 1. a stall is imposed while loading the 8032 PreFetch Queue (PFQ); or 2. the occurrence of a cache miss in the Branch Cache (BC) during a branch in program execution flow. See 8032 MCU CORE PERFORMANCE ENHANCEMENTS, page 17 or more details. But generally speaking, during typical program execution, the PFQ is not empty and the BC has no misses, producing very good performance without extending the duration of any machine cycles. The uPSD33xx Programmers Guide describes each instruction operation in detail. Table 6. Arithmetic Instruction Set Note: 1. All mnemonics copyrighted ©Intel Corporation 1980. Mnemonic(1) and Use Description Length/Cycles ADD A, Rn Add register to ACC 1 byte/1 cycle ADD A, Direct Add direct byte to ACC 2 byte/1 cycle ADD A, @Ri Add indirect SRAM to ACC 1 byte/1 cycle ADD A, #data Add immediate data to ACC 2 byte/1 cycle ADDC A, Rn Add register to ACC with carry 1 byte/1 cycle ADDC A, direct Add direct byte to ACC with carry 2 byte/1 cycle ADDC A, @Ri Add indirect SRAM to ACC with carry 1 byte/1 cycle ADDC A, #data Add immediate data to ACC with carry 2 byte/1 cycle SUBB A, Rn Subtract register from ACC with borrow 1 byte/1 cycle SUBB A, direct Subtract direct byte from ACC with borrow 2 byte/1 cycle SUBB A, @Ri Subtract indirect SRAM from ACC with borrow 1 byte/1 cycle SUBB A, #data Subtract immediate data from ACC with borrow 2 byte/1 cycle INC A Increment A 1 byte/1 cycle INC Rn Increment register 1 byte/1 cycle INC direct Increment direct byte 2 byte/1 cycle INC @Ri Increment indirect SRAM 1 byte/1 cycle DEC A Decrement ACC 1 byte/1 cycle DEC Rn Decrement register 1 byte/1 cycle DEC direct Decrement direct byte 2 byte/1 cycle DEC @Ri Decrement indirect SRAM 1 byte/1 cycle INC DPTR Increment Data Pointer 1 byte/2 cycle MUL AB Multiply ACC and B 1 byte/4 cycle DIV AB Divide ACC by B 1 byte/4 cycle DA A Decimal adjust ACC 1 byte/1 cycle33/231 uPSD33xx Table 7. Logical Instruction Set Note: 1. All mnemonics copyrighted ©Intel Corporation 1980. Mnemonic(1) and Use Description Length/Cycles ANL A, Rn AND register to ACC 1 byte/1 cycle ANL A, direct AND direct byte to ACC 2 byte/1 cycle ANL A, @Ri AND indirect SRAM to ACC 1 byte/1 cycle ANL A, #data AND immediate data to ACC 2 byte/1 cycle ANL direct, A AND ACC to direct byte 2 byte/1 cycle ANL direct, #data AND immediate data to direct byte 3 byte/2 cycle ORL A, Rn OR register to ACC 1 byte/1 cycle ORL A, direct OR direct byte to ACC 2 byte/1 cycle ORL A, @Ri OR indirect SRAM to ACC 1 byte/1 cycle ORL A, #data OR immediate data to ACC 2 byte/1 cycle ORL direct, A OR ACC to direct byte 2 byte/1 cycle ORL direct, #data OR immediate data to direct byte 3 byte/2 cycle SWAP A Swap nibbles within the ACC 1 byte/1 cycle XRL A, Rn Exclusive-OR register to ACC 1 byte/1 cycle XRL A, direct Exclusive-OR direct byte to ACC 2 byte/1 cycle XRL A, @Ri Exclusive-OR indirect SRAM to ACC 1 byte/1 cycle XRL A, #data Exclusive-OR immediate data to ACC 2 byte/1 cycle XRL direct, A Exclusive-OR ACC to direct byte 2 byte/1 cycle XRL direct, #data Exclusive-OR immediate data to direct byte 3 byte/2 cycle CLR A Clear ACC 1 byte/1 cycle CPL A Compliment ACC 1 byte/1 cycle RL A Rotate ACC left 1 byte/1 cycle RLC A Rotate ACC left through the carry 1 byte/1 cycle RR A Rotate ACC right 1 byte/1 cycle RRC A Rotate ACC right through the carry 1 byte/1 cycleuPSD33xx 34/231 Table 8. Data Transfer Instruction Set Note: 1. All mnemonics copyrighted ©Intel Corporation 1980. Mnemonic(1) and Use Description Length/Cycles MOV A, Rn Move register to ACC 1 byte/1 cycle MOV A, direct Move direct byte to ACC 2 byte/1 cycle MOV A, @Ri Move indirect SRAM to ACC 1 byte/1 cycle MOV A, #data Move immediate data to ACC 2 byte/1 cycle MOV Rn, A Move ACC to register 1 byte/1 cycle MOV Rn, direct Move direct byte to register 2 byte/2 cycle MOV Rn, #data Move immediate data to register 2 byte/1 cycle MOV direct, A Move ACC to direct byte 2 byte/1 cycle MOV direct, Rn Move register to direct byte 2 byte/2 cycle MOV direct, direct Move direct byte to direct 3 byte/2 cycle MOV direct, @Ri Move indirect SRAM to direct byte 2 byte/2 cycle MOV direct, #data Move immediate data to direct byte 3 byte/2 cycle MOV @Ri, A Move ACC to indirect SRAM 1 byte/1 cycle MOV @Ri, direct Move direct byte to indirect SRAM 2 byte/2 cycle MOV @Ri, #data Move immediate data to indirect SRAM 2 byte/1 cycle MOV DPTR, #data16 Load Data Pointer with 16-bit constant 3 byte/2 cycle MOVC A, @A+DPTR Move code byte relative to DPTR to ACC 1 byte/2 cycle MOVC A, @A+PC Move code byte relative to PC to ACC 1 byte/2 cycle MOVX A, @Ri Move XDATA (8-bit addr) to ACC 1 byte/2 cycle MOVX A, @DPTR Move XDATA (16-bit addr) to ACC 1 byte/2 cycle MOVX @Ri, A Move ACC to XDATA (8-bit addr) 1 byte/2 cycle MOVX @DPTR, A Move ACC to XDATA (16-bit addr) 1 byte/2 cycle PUSH direct Push direct byte onto stack 2 byte/2 cycle POP direct Pop direct byte from stack 2 byte/2 cycle XCH A, Rn Exchange register with ACC 1 byte/1 cycle XCH A, direct Exchange direct byte with ACC 2 byte/1 cycle XCH A, @Ri Exchange indirect SRAM with ACC 1 byte/1 cycle XCHD A, @Ri Exchange low-order digit indirect SRAM with ACC 1 byte/1 cycle35/231 uPSD33xx Table 9. Boolean Variable Manipulation Instruction Set Note: 1. All mnemonics copyrighted ©Intel Corporation 1980. Mnemonic(1) and Use Description Length/Cycles CLR C Clear carry 1 byte/1 cycle CLR bit Clear direct bit 2 byte/1 cycle SETB C Set carry 1 byte/1 cycle SETB bit Set direct bit 2 byte/1 cycle CPL C Compliment carry 1 byte/1 cycle CPL bit Compliment direct bit 2 byte/1 cycle ANL C, bit AND direct bit to carry 2 byte/2 cycle ANL C, /bit AND compliment of direct bit to carry 2 byte/2 cycle ORL C, bit OR direct bit to carry 2 byte/2 cycle ORL C, /bit OR compliment of direct bit to carry 2 byte/2 cycle MOV C, bit Move direct bit to carry 2 byte/1 cycle MOV bit, C Move carry to direct bit 2 byte/2 cycle JC rel Jump if carry is set 2 byte/2 cycle JNC rel Jump if carry is not set 2 byte/2 cycle JB rel Jump if direct bit is set 3 byte/2 cycle JNB rel Jump if direct bit is not set 3 byte/2 cycle JBC bit, rel Jump if direct bit is set and clear bit 3 byte/2 cycleuPSD33xx 36/231 Table 10. Program Branching Instruction Set Note: 1. All mnemonics copyrighted ©Intel Corporation 1980. Table 11. Miscellaneous Instruction Set Note: 1. All mnemonics copyrighted ©Intel Corporation 1980. Table 12. Notes on Instruction Set and Addressing Modes Mnemonic(1) and Use Description Length/Cycles ACALL addr11 Absolute subroutine call 2 byte/2 cycle LCALL addr16 Long subroutine call 3 byte/2 cycle RET Return from subroutine 1 byte/2 cycle RETI Return from interrupt 1 byte/2 cycle AJMP addr11 Absolute jump 2 byte/2 cycle LJMP addr16 Long jump 3 byte/2 cycle SJMP rel Short jump (relative addr) 2 byte/2 cycle JMP @A+DPTR Jump indirect relative to the DPTR 1 byte/2 cycle JZ rel Jump if ACC is zero 2 byte/2 cycle JNZ rel Jump if ACC is not zero 2 byte/2 cycle CJNE A, direct, rel Compare direct byte to ACC, jump if not equal 3 byte/2 cycle CJNE A, #data, rel Compare immediate to ACC, jump if not equal 3 byte/2 cycle CJNE Rn, #data, rel Compare immediate to register, jump if not equal 3 byte/2 cycle CJNE @Ri, #data, rel Compare immediate to indirect, jump if not equal 3 byte/2 cycle DJNZ Rn, rel Decrement register and jump if not zero 2 byte/2 cycle DJNZ direct, rel Decrement direct byte and jump if not zero 3 byte/2 cycle Mnemonic(1) and Use Description Length/Cycles NOP No Operation 1 byte/1 cycle Rn Register R0 - R7 of the currently selected register bank. direct 8-bit address for internal 8032 DATA SRAM (locations 00h - 7Fh) or SFR registers (locations 80h - FFh). @Ri 8-bit internal 8032 SRAM (locations 00h - FFh) addressed indirectly through contents of R0 or R1. #data 8-bit constant included within the instruction. #data16 16-bit constant included within the instruction. addr16 16-bit destination address used by LCALL and LJMP. addr11 11-bit destination address used by ACALL and AJMP. rel Signed (two-s compliment) 8-bit offset byte. bit Direct addressed bit in internal 8032 DATA SRAM (locations 20h to 2Fh) or in SFR registers (88h, 90h, 98h, A8h, B0, B8h, C0h, C8h, D0h, D8h, E0h, F0h).37/231 uPSD33xx DUAL DATA POINTERS XDATA is accessed by the External Direct addressing mode, which uses a 16-bit address stored in the DPTR Register. Traditional 8032 architecture has only one DPTR Register. This is a burden when transferring data between two XDATA locations because it requires heavy use of the working registers to manipulate the source and destination pointers. However, the uPSD33xx has two data pointers, one for storing a source address and the other for storing a destination address. These pointers can be configured to automatically increment or decrement after each data transfer, further reducing the burden on the 8032 and making this kind of data movement very efficient. Data Pointer Control Register, DPTC (85h) By default, the DPTR Register of the uPSD33xx will behave no different than in a standard 8032 MCU. The DPSEL0 Bit of SFR register DPTC shown in Table 13, selects which one of the two “background” data pointer registers (DPTR0 or DPTR1) will function as the traditional DPTR Register at any given time. After reset, the DPSEL0 Bit is cleared, enabling DPTR0 to function as the DPTR, and firmware may access DPTR0 by reading or writing the traditional DPTR Register at SFR addresses 82h and 83h. When the DPSEL0 bit is set, then the DPTR1 Register functions as DPTR, and firmware may now access DPTR1 through SFR registers at 82h and 83h. The pointer which is not selected by the DPSEL0 bit remains in the background and is not accessible by the 8032. If the DPSEL0 bit is never set, then the uPSD33xx will behave like a traditional 8032 having only one DPTR Register. To further speed XDATA to XDATA transfers, the SFR bit, AT, may be set to automatically toggle the two data pointers, DPTR0 and DPTR1, each time the standard DPTR Register is accessed by a MOVX instruction. This eliminates the need for firmware to manually manipulate the DPSEL0 bit between each data transfer. Detailed description for the SFR register DPTC is shown in Table 13. Table 13. DPTC: Data Pointer Control Register (SFR 85h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – AT – – – – – DPSEL0 Details Bit Symbol R/W Definition 7 – – Reserved 6 AT R,W 0 = Manually Select Data Pointer 1 = Auto Toggle between DPTR0 and DPTR1 5-1 – – Reserved 0 DPSE0 R,W 0 = DPTR0 Selected for use as DPTR 1 = DPTR1 Selected for use as DPTRuPSD33xx 38/231 Data Pointer Mode Register, DPTM (86h) The two “background” data pointers, DPTR0 and DPTR1, can be configured to automatically increment, decrement, or stay the same after a MOVX instruction accesses the DPTR Register. Only the currently selected pointer will be affected by the increment or decrement. This feature is controlled by the DPTM Register defined in Table 14. The automatic increment or decrement function is effective only for the MOVX instruction, and not MOVC or any other instruction that uses the DTPR Register. Firmware Example. The 8051 assembly code illustrated in Table 15 shows how to transfer a block of data bytes from one XDATA address region to another XDATA address region. Auto-address incrementing and auto-pointer toggling will be used. Table 14. DPTM: Data Pointer Mode Register (SFR 86h, reset value 00h) Table 15. 8051 Assembly Code Example Note: 1. The code loop where the data transfer takes place is only 3 lines of code. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – – MD11 MD10 MD01 MD00 Details Bit Symbol R/W Definition 7-4 – – Reserved 3-2 MD[11:10] R,W DPTR1 Mode Bits 00: DPTR1 No Change 01: Reserved 10: Auto Increment 11: Auto Decrement 1-0 MD[01:00] R,W DPTR0 Mode Bits 00: DPTR0 No Change 01: Reserved 10: Auto Increment 11: Auto Decrement MOV R7, #COUNT ; initialize size of data block to transfer MOV DPTR, #SOURCE_ADDR ; load XDATA source address base into DPTR0 MOV 85h, #01h ; load DPTC to access DPTR1 pointer MOV DPTR, #DEST_ADDR ; load XDATA destination address base into DPTR1 MOV 85h, #40h ; load DPTC to access DPTR0 pointer and auto toggle MOV 86h, #0Ah ; load DPTM to auto-increment both pointers LOOP: MOVX(1) A, @DPTR ; load XDATA byte from source into ACC. ; after load completes, DPTR0 increments and DPTR ; switches DPTR1 MOVX(1) @DPTR, A ; store XDATA byte from ACC to destination. ; after store completes, DPTR1 increments and DPTR ; switches to DPTR0 DJNZ(1) R7, LOOP ; continue until done MOV 86h, #00 ; disable auto-increment MOV 85h, #00 ; disable auto-toggle, now back to single DPTR mode39/231 uPSD33xx DEBUG UNIT The 8032 MCU Module supports run-time debugging through the JTAG interface. This same JTAG interface is also used for In-System Programming (ISP) and the physical connections are described in the PSD Module section, JTAG ISP and JTAG Debug, page 195. Debugging with a serial interface such as JTAG is a non-intrusive way to gain access to the internal state of the 8032 MCU core and various memories. A traditional external hardware emulator cannot be completely effective on the uPSD33xx because of the Pre-Fetch Queue and Branch Cache. The nature of the PFQ and BC hide the visibility of actual program flow through traditional external bus connections, thus requiring on-chip serial debugging instead. Debugging is supported by Windows PC based software tools used for 8051 code development from 3rd party vendors listed at www.st.com/psm. Debug capabilities include: ■ Halt or Start MCU execution ■ Reset the MCU ■ Single Step ■ 3 Match Breakpoints ■ 1 Range Breakpoint (inside or outside range) ■ Program Tracing ■ Read or Modify MCU core registers, DATA, IDATA, SFR, XDATA, and Code ■ External Debug Event Pin, Input or Output Some key points regarding use of the JTAG Debugger. – The JTAG Debugger can access MCU registers, data memory, and code memory while the MCU is executing at full speed by cycle-stealing. This means “watch windows” may be displayed and periodically updated on the PC during full speed operation. Registers and data content may also be modified during full speed operation. – There is no on-chip storage for Program Trace data, but instead this data is scanned from the uPSD33xx through the JTAG channel at runtime to the PC host for proccessing. As such, full speed program tracing is possible only when the 8032 MCU is operating below approximately one MIPS of performance. Above one MIPS, the program will not run real-time while tracing. One MIPS performance is determined by the combination of choice for MCU clock frequency, and the bit settings in SFR registers BUSCON and CCON0. – Breakpoints can optionally halt the MCU, and/ or assert the external Debug Event pin. – Breakpoint definitions may be qualified with read or write operations, and may also be qualified with an address of code, SFR, DATA, IDATA, or XDATA memories. – Three breakpoints will compare an address, but the fourth breakpoint can compare an address and also data content. Additionally, the fouth breakpoint can be logically combined (AND/OR) with any of the other three breakpoints. – The Debug Event pin can be configured by the PC host to generate an output pulse for external triggering when a break condition is met. The pin can also be configured as an event input to the breakpoint logic, causing a break on the falling-edge of an external event signal. If not used, the Debug Event pin should be pulled up to VCC as described in the section, Debugging the 8032 MCU Module., page 201. – The duration of a pulse, generated when the Event pin configured as an output, is one MCU clock cycle. This is an active-low signal, so the first edge when an event occurs is high-to-low. – The clock to the Watchdog Timer, ADC, and I 2C interface are not stopped by a breakpoint halt. – The Watchdog Timer should be disabled while debugging with JTAG, else a reset will be generated upon a watchdog time-out.uPSD33xx 40/231 INTERRUPT SYSTEM The uPSD33xx has an 11-source, two priority level interrupt structure summarized in Table 16. Firmware may assign each interrupt source either high or low priority by writing to bits in the SFRs named, IP and IPA, shown in Table 16. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority interrupt is being serviced, it will be stopped and the new interrupt is serviced. When the new interrupt is finished, the lower priority interrupt that was stopped will be completed. If new interrupt requests are of the same priority level and are received simultaneously, an internal polling sequence determines which request is selected for service. Thus, within each of the two priority levels, there is a second priority structure determined by the polling sequence. Firmware may individually enable or disable interrupt sources by writing to bits in the SFRs named, IE and IEA, shown in Table 16., page 41. The SFR named IE contains a global disable bit (EA), which can be cleared to disable all 11 interrupts at once, as shown in Table 17., page 43. Figure 13., page 42 illustrates the interrupt priority, polling, and enabling process. Each interrupt source has at least one interrupt flag that indicates whether or not an interrupt is pending. These flags reside in bits of various SFRs shown in Table 16., page 41. All of the interrupt flags are latched into the interrupt control system at the beginning of each MCU machine cycle, and they are polled at the beginning of the following machine cycle. If polling determines one of the flags was set, the interrupt control system automatically generates an LCALL to the user’s Interrupt Service Routine (ISR) firmware stored in program memory at the appropriate vector address. The specific vector address for each of the interrupt sources are listed in Table 16., page 41. However, this LCALL jump may be blocked by any of the following conditions: – An interrupt of equal or higher priority is already in progress – The current machine cycle is not the final cycle in the execution of the instruction in progress – The current instruction involves a write to any of the SFRs: IE, IEA, IP, or IPA – The current instruction is an RETI Note: Interrupt flags are polled based on a sample taken in the previous MCU machine cycle. If an interrupt flag is active in one cycle but is denied serviced due to the conditions above, and then later it is not active when the conditions above are finally satisfied, the previously denied interrupt will not be serviced. This means that active interrupts are not remembered. Every poling cycle is new. Assuming all of the listed conditions are satisfied, the MCU executes the hardware generated LCALL to the appropriate ISR. This LCALL pushes the contents of the PC onto the stack (but it does not save the PSW) and loads the PC with the appropriate interrupt vector address. Program execution then jumps to the ISR at the vector address. Execution precedes in the ISR. It may be necessary for the ISR firmware to clear the pending interrupt flag for some interrupt sources, because not all interrupt flags are automatically cleared by hardware when the ISR is called, as shown in Table 16., page 41. If an interrupt flag is not cleared after servicing the interrupt, an unwanted interrupt will occur upon exiting the ISR. After the interrupt is serviced, the last instruction executed by the ISR is RETI. The RETI informs the MCU that the ISR is no longer in progress and the MCU pops the top two bytes from the stack and loads them into the PC. Execution of the interrupted program continues where it left off. Note: An ISR must end with a RETI instruction, not a RET. An RET will not inform the interrupt control system that the ISR is complete, leaving the MCU to think the ISR is still in progress, making future interrupts impossible.41/231 uPSD33xx Table 16. Interrupt Summary Interrupt Source Polling Priority Vector Addr Flag Bit Name (SFR.bit position) 1 = Intr Pending 0 = No Interrupt Flag Bit AutoCleared by Hardware? Enable Bit Name (SFR.bit position) 1 = Intr Enabled 0 = Intr Disabled Priority Bit Name (SFR.bit position) 1= High Priority 0 = Low Priority Reserved 0 (high) 0063h – – – – External Interrupt INT0 1 0003h IE0 (TCON.1) Edge - Yes Level - No EX0 (IE.0) PX0 (IP.0) Timer 0 Overflow 2 000Bh TF0 (TCON.5) Yes ET0 (IE.1) PT0 (IP.1) External Interrupt INT1 3 0013h IE1 (TCON.3 Edge - Yes Level - No EX1 (IE.2) PX1 (IP.2) Timer 1 Overflow 4 001Bh TF1 (TCON.7) Yes ET1 (IE.3) PT1 (IP.3) UART0 5 0023h RI (SCON0.0) TI (SCON0.1) No ES0 (IE.4) PS0 (IP.4) Timer 2 Overflow or TX2 Pin 6 002Bh TF2 (T2CON.7) EXF2 (T2CON.6) No ET2 (IE.5) PT2 (IP.5) SPI 7 0053h TEISF, RORISF, TISF, RISF (SPISTAT[3:0]) Yes ESPI (IEA.6) PSPI (IPA.6) Reserved 8 0033h – – – – I 2C 9 0043h INTR (S1STA.5) Yes EI2C (IEA.1) PI2C (IPA.1) ADC 10 003Bh AINTF (ACON.7) No EADC (IEA.7) PADC (IPA.7) PCA 11 005Bh OFVx, INTFx (PCASTA[0:7]) No EPCA (IEA.5) PPCA (IPA.5) UART1 12 (low) 004Bh RI (SCON1.0) TI (SCON1.1) No ES1 (IEA.4) PS1 (IPA.4)uPSD33xx 42/231 Figure 13. Enabling and Polling Interrupts Reserved Ext INT0 Ext INT1 Timer 0 UART0 Timer 1 SPI USB Timer 2 High LowInterrupt Polling Sequence Interrupt Sources IE/IEA IP/IPA Priority Global Enable ADC PCA I 2 C UART1 AI0784443/231 uPSD33xx Individual Interrupt Sources External Interrupts Int0 and Int1. External interrupt inputs on pins EXTINT0 and EXTINT1 (pins 3.2 and 3.3) are either edge-triggered or level-triggered, depending on bits IT0 and IT1 in the SFR named TCON. When an external interrupt is generated from an edge-triggered (falling-edge) source, the appropriate flag bit (IE0 or IE1) is automatically cleared by hardware upon entering the ISR. When an external interrupt is generated from a level-triggered (low-level) source, the appropriate flag bit (IE0 or IE1) is NOT automatically cleared by hardware. Timer 0 and 1 Overflow Interrupt. Timer 0 and Timer 1 interrupts are generated by the flag bits TF0 and TF1 when there is an overflow condition in the respective Timer/Counter register (except for Timer 0 in Mode 3). Timer 2 Overflow Interrupt. This interrupt is generated to the MCU by a logical OR of flag bits, TF2 and EXE2. The ISR must read the flag bits to determine the cause of the interrupt. – TF2 is set by an overflow of Timer 2. – EXE2 is generated by the falling edge of a signal on the external pin, T2X (pin P1.1). UART0 and UART1 Interrupt. Each of the UARTs have identical interrupt structure. For each UART, a single interrupt is generated to the MCU by the logical OR of the flag bits, RI (byte received) and TI (byte transmitted). The ISR must read flag bits in the SFR named SCON0 for UART0, or SCON1 for UART1 to determine the cause of the interrupt. SPI Interrupt. The SPI interrupt has four interrupt sources, which are logically ORed together when interrupting the MCU. The ISR must read the flag bits to determine the cause of the interrupt. A flag bit is set for: end of data transmit (TEISF); data receive overrun (RORISF); transmit buffer empty (TISF); or receive buffer full (RISF). I 2C Interrupt. The flag bit INTR is set by a variety of conditions occurring on the I2C interface: received own slave address (ADDR flag); received general call address (GC flag); received STOP condition (STOP flag); or successful transmission or reception of a data byte.The ISR must read the flag bits to determine the cause of the interrupt. ADC Interrupt. The flag bit AINTF is set when an A-to-D conversion has completed. PCA Interrupt. The PCA has eight interrupt sources, which are logically ORed together when interrupting the MCU.The ISR must read the flag bits to determine the cause of the interrupt. – Each of the six TCMs can generate a "match or capture" interrupt on flag bits OFV5..0 respectively. – Each of the two 16-bit counters can generate an overflow interrupt on flag bits INTF1 and INTF0 respectively. Tables 17 through Table 20., page 45 have detailed bit definitions of the interrupt system SFRs. Table 17. IE: Interrupt Enable Register (SFR A8h, reset value 00h) Note: 1. 1 = Enable Interrupt, 0 = Disable Interrupt Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EA – ET2 ES0 ET1 EX1 ET0 EX0 Details Bit Symbol R/W Function 7 EA R,W Global disable bit. 0 = All interrupts are disabled. 1 = Each interrupt source can be individually enabled or disabled by setting or clearing its enable bit. 6 – R,W Do not modify this bit. It is used by the JTAG debugger for instruction tracing. Always read the bit and write back the same bit value when writing this SFR. 5(1) ET2 R,W Enable Timer 2 Interrupt 4(1) ES0 R,W Enable UART0 Interrupt 3(1) ET1 R,W Enable Timer 1 Interrupt 2(1) EX1 R,W Enable External Interrupt INT1 1(1) ET0 R,W Enable Timer 0 Interrupt 0(1) EX0 R,W Enable External Interrupt INT0uPSD33xx 44/231 Table 18. IEA: Interrupt Enable Addition Register (SFR A7h, reset value 00h) Note: 1. 1 = Enable Interrupt, 0 = Disable Interrupt Table 19. IP: Interrupt Priority Register (SFR B8h, reset value 00h) Note: 1. 1 = Assigns high priority level, 0 = Assigns low priority level Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EADC ESPI EPCA ES1 – – EI2C – Details Bit Symbol R/W Function 7(1) EADC R,W Enable ADC Interrupt 6(1) ESPI R,W Enable SPI Interrupt 5(1) EPCA R,W Enable Programmable Counter Array Interrupt 4(1) ES1 R,W Enable UART1 Interrupt 3 – – Reserved, do not set to logic '1.' 2 – – Reserved, do not set to logic '1.' 1(1) EI2C R,W Enable I2C Interrupt 0 – – Reserved, do not set to logic '1.' Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – PT2 PS0 PT1 PX1 PT0 PX0 Details Bit Symbol R/W Function 7 – – Reserved 6 – – Reserved 5(1) PT2 R,W Timer 2 Interrupt priority level 4(1) PS0 R,W UART0 Interrupt priority level 3(1) PT1 R,W Timer 1 Interrupt priority level 2(1) PX1 R,W External Interrupt INT1 priority level 1(1) PT0 R,W Timer 0 Interrupt priority level 0(1) PX0 R,W External Interrupt INT0 priority level45/231 uPSD33xx Table 20. IPA: Interrupt Priority Addition register (SFR B7h, reset value 00h) Note: 1. 1 = Assigns high priority level, 0 = Assigns low priority level Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PADC PSPI PPCA PS1 – – PI2C – Details Bit Symbol R/W Function 7(1) PADC R,W ADC Interrupt priority level 6(1) PSPI R,W SPI Interrupt priority level 5(1) PPCA R,W PCA Interrupt level 4(1) PS1 R,W UART1 Interrupt priority level 3 – – Reserved 2 – – Reserved 1(1) PI2C R,W I 2C Interrupt priority level 0 – – ReserveduPSD33xx 46/231 MCU CLOCK GENERATION Internal system clocks generated by the clock generation unit are derived from the signal, XTAL1, shown in Figure 14. XTAL1 has a frequency fOSC, which comes directly from the external crystal or oscillator device. The SFR named CCON0 (Table 21., page 47) controls the clock generation unit. There are two clock signals produced by the clock generation unit: ■ MCU_CLK ■ PERIPH_CLK MCU_CLK This clock drives the 8032 MCU core and the Watchdog Timer (WDT). The frequency of MCU_CLK is equal to fOSC by default, but it can be divided by as much as 2048, shown in Figure 14. The bits CPUPS[2:0] select one of eight different divisors, ranging from 2 to 2048. The new frequency is available immediately after the CPUPS[2:0] bits are written. The final frequency of MCU_CLK is fMCU. MCU_CLK is blocked by either bit, PD or IDL, in the SFR named PCON during MCU Power-down Mode or Idle Mode respectively. MCU_CLK clock can be further divided as required for use in the WDT. See details of the WDT in SUPERVISORY FUNCTIONS, page 65. PERIPH_CLK This clock drives all the uPSD33xx peripherals except the WDT. The Frequency of PERIPH_CLK is always fOSC. Each of the peripherals can independently divide PERIPH_CLK to scale it appropriately for use. PERIPH_CLK runs at all times except when blocked by the PD bit in the SFR named PCON during MCU Power-down Mode. JTAG Interface Clock. The JTAG interface for ISP and for Debugging uses the externally supplied JTAG clock, coming in on pin TCK. This means the JTAG ISP interface is always available, and the JTAG Debug interface is available when enabled, even during MCU Idle mode and Powerdown Mode. However, since the MCU participates in the JTAG debug process, and MCU_CLK is halted during Idle and Power-down Modes, the majority of debug functions are not available during these low power modes. But the JTAG debug interface is capable of executing a reset command while in these low power modes, which will exit back to normal operating mode where all debug commands are available again. The CCON0 SFR contains a bit, DBGCE, which enables the breakpoint comparators inside the JTAG Debug Unit when set. DBGCE is set by default after reset, and firmware may clear this bit at run-time. Disabling these comparators will reduce current consumption on the MCU Module, and it’s recommended to do so if the Debug Unit will not be used (such as in the production version of an end-product). Figure 14. Clock Generation Logic XTAL1 /2 XTAL1 /4 XTAL1 /2048 Q Q Q M U X XTAL1 (default) XTAL1 /8 XTAL1 /16 Q Q XTAL1 /32 XTAL1 /1024 Q Q 0 1 2 3 4 5 6 7 XTAL1 (fOSC) PCON[1]: PD, Power-Down Mode PCON[2:0]: CPUPS[2:0], Clock Pre-Scaler Select PCON[0]: IDL, Idle Mode Clock Divider MCU_CLK (fMCU) (to: 8032, WDT) PERIPH_CLK (fOSC) (to: TIMER0/1/2, UART0/1, PCA0/1, SPI, I2C, ADC) 3 AI0919747/231 uPSD33xx Table 21. CCON0: Clock Control Register (SFR F9h, reset value 10h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – DBGCE CPUAR CPUPS[2:0] Details Bit Symbol R/W Definition 7 – – Reserved 6 – – Reserved 5 – – Reserved 4 DBGCE R,W Debug Unit Breakpoint Comparator Enable 0 = JTAG Debug Unit comparators are disabled 1 = JTAG Debug Unit comparators are enabled (Default condition after reset) 3 CPUAR R,W Automatic MCU Clock Recovery 0 = There is no change of CPUPS[2:0] when an interrupt occurs. 1 = Contents of CPUPS[2:0] automatically become 000b whenever any interrupt occurs. 2:0 CPUPS R,W MCUCLK Pre-Scaler 000b: fMCU = fOSC (Default after reset) 001b: fMCU = fOSC/2 010b: fMCU = fOSC/4 011b: fMCU = fOSC/8 100b: fMCU = fOSC/16 101b: fMCU = fOSC/32 110b: fMCU = fOSC/1024 111b: fMCU = fOSC/2048uPSD33xx 48/231 POWER SAVING MODES The uPSD33xx is a combination of two die, or modules, each module having it’s own current consumption characteristics. This section describes reduced power modes for the MCU Module. See the section, Power Management, page 137 for reduced power modes of the PSD Module. Total current consumption for the combined modules is determined in the DC specifications at the end of this document. The MCU Module has three software-selectable modes of reduced power operation. ■ Idle Mode ■ Power-down Mode ■ Reduced Frequency Mode Idle Mode Idle Mode will halt the 8032 MCU core while leaving the MCU peripherals active (Idle Mode blocks MCU_CLK only). For lowest current consumption in this mode, it is recommended to disable all unused peripherals, before entering Idle mode (such as the ADC and the Debug Unit breakpoint comparators). The following functions remain fully active during Idle Mode (except if disabled by SFR settings). ■ External Interrupts INT0 and INT1 ■ Timer 0, Timer 1 and Timer 2 ■ Supervisor reset from: LVD, JTAG Debug, External RESET_IN_, but not the WTD ■ ADC ■ I 2C Interface ■ UART0 and UART1 Interfaces ■ SPI Interface ■ Programmable Counter Array An interrupt generated by any of these peripherals, or a reset generated from the supervisor, will cause Idle Mode to exit and the 8032 MCU will resume normal operation. The output state on I/O pins of MCU ports 1, 3, and 4 remain unchanged during Idle Mode. To enter Idle Mode, the 8032 MCU executes an instruction to set the IDL bit in the SFR named PCON, shown in Table 24., page 50. This is the last instruction executed in normal operating mode before Idle Mode is activated. Once in Idle Mode, the MCU status is entirely preserved, and there are no changes to: SP, PSW, PC, ACC, SFRs, DATA, IDATA, or XDATA. The following are factors related to Idle Mode exit: – Activation of any enabled interrupt will cause the IDL bit to be cleared by hardware, terminating Idle Mode. The interrupt is serviced, and following the Return from Interrupt instruction (RETI), the next instruction to be executed will be the one which follows the instruction that set the IDL bit in the PCON SFR. – After a reset from the supervisor, the IDL bit is cleared, Idle Mode is terminated, and the MCU restarts after three MCU machine cycles. Power-down Mode Power-down Mode will halt the 8032 core and all MCU peripherals (Power-down Mode blocks MCU_CLK and PERIPH_CLK). This is the lowest power state for the MCU Module. When the PSD Module is also placed in Power-down mode, the lowest total current consumption for the combined die is achieved for the uPSD33xx. See Power Management, page 137 in the PSD Module section for details on how to also place the PSD Module in Power-down mode. The sequence of 8032 instructions is important when placing both modules into Power-down Mode. The instruction that sets the PD Bit in the SFR named PCON (Table 24., page 50) is the last instruction executed prior to the MCU Module going into Power-down Mode. Once in Power-down Mode, the on-chip oscillator circuitry and all clocks are stopped. The SFRs, DATA, IDATA, and XDATA are preserved. Power-down Mode is terminated only by a reset from the supervisor, originating from the RESET_IN_ pin, the Low-Voltage Detect circuit (LVD), or a JTAG Debug reset command. Since the clock to the WTD is not active during Powerdown mode, it is not possible for the supervisor to generate a WDT reset. Table 22., page 49 summarizes the status of I/O pins and peripherals during Idle and Power-down Modes on the MCU Module. Table 23., page 49 shows the state of 8032 MCU address, data, and control signals during these modes. Reduced Frequency Mode The 8032 MCU consumes less current when operating at a lower clock frequency. The MCU can reduce it’s own clock frequency at run-time by writing to three bits, CPUPS[2:0], in the SFR named CCON0 described in Table 21., page 47. These bits effectively divide the clock frequency (fOSC) coming in from the external crystal or oscillator device. The clock division range is from 1/2 to 1/2048, and the resulting frequency is fMCU. This MCU clock division does not affect any of the peripherals, except for the WTD. The clock driving the WTD is the same clock driving the 8032 MCU core as shown in Figure 14., page 46.49/231 uPSD33xx MCU firmware may reduce the MCU clock frequency at run-time to consume less current when performing tasks that are not time critical, and then restore full clock frequency as required to perform urgent tasks. Returning to full clock frequency is done automatically upon an MCU interrupt, if the CPUAR Bit in the SFR named CCON0 is set (the interrupt will force CPUPS[2:0] = 000). This is an excellent way to conserve power using a low frequency clock until an event occurs that requires full performance. See Table 21., page 47 for details on CPUAR. See the DC Specifications at the end of this document to estimate current consumption based on the MCU clock frequency. Note: Some of the bits in the PCON SFR shown in Table 24., page 50 are not related to power control. Table 22. MCU Module Port and Peripheral Status during Reduced Power Modes Note: 1. The Watchdog Timer is not active during Idle Mode. Other supervisor functions are active: LVD, external reset, JTAG Debug reset Table 23. State of 8032 MCU Bus Signals during Power-down and Idle Modes Mode Ports 1, 3, 4 PCA SPI I 2C ADC SUPERVISOR UART0, UART1 TIMER 0,1,2 EXT INT0, 1 Idle Maintain Data Active Active Active Active Active(1) Active Active Active Power-down Maintain Data Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Mode ALE PSEN_ RD_ WR_ AD0-7 A8-15 Idle 0 1 1 1 FFh FFh Power-down 0 1 1 1 FFh FFhuPSD33xx 50/231 Table 24. PCON: Power Control Register (SFR 87h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMOD0 SMOD1 – POR RCLK1 TCLK1 PD IDL Details Bit Symbol R/W Function 7 SMOD0 R,W Baud Rate Double Bit (UART0) 0 = No Doubling 1 = Doubling (See UART Baud Rates, page 84 for details.) 6 SMOD1 R,W Baud Rate Double Bit for 2nd UART (UART1) 0 = No Doubling 1 = Doubling (See UART Baud Rates, page 84 for details.) 5 – – Reserved 4 POR R,W Only a power-on reset sets this bit (cold reset). Warm reset will not set this bit. '0,' Cleared to zero with firmware '1,' Is set only by a power-on reset generated by Supervisory circuit (see Power-up Reset, page 66 for details). 3 RCLK1 R,W Received Clock Flag (UART1) (See Table 41., page 75 for flag description.) 2 TCLK1 R,W Transmit Clock Flag (UART1) (See Table 41., page 75 for flag description) 1 PD R,W Activate Power-down Mode 0 = Not in Power-down Mode 1 = Enter Power-down Mode 0 IDL R,W Activate Idle Mode 0 = Not in Idle Mode 1 = Enter Idle Mode51/231 uPSD33xx OSCILLATOR AND EXTERNAL COMPONENTS The oscillator circuit of uPSD33xx devices is a single stage, inverting amplifier in a Pierce oscillator configuration. The internal circuitry between pins XTAL1 and XTAL2 is basically an inverter biased to the transfer point. Either an external quartz crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuit. Both are operated in parallel resonance. Ceramic resonators are lower cost, but typically have a wider frequency tolerance than quartz crystals. Alternatively, an external clock source from an oscillator or other active device may drive the uPSD33xx oscillator circuit input directly, instead of using a crystal or resonator. The minimum frequency of the quartz crystal, ceramic resonator, or external clock source is 1MHz if the I2C interface is not used. The minimum is 8MHz if I2C is used. The maximum is 40MHz in all cases. This frequency is fOSC, which can be divided internally as described in MCU CLOCK GENERATION, page 46. The pin XTAL1 is the high gain amplifier input, and XTAL2 is the output. To drive the uPSD33xx device externally from an oscillator or other active device, XTAL1 is driven and XTAL2 is left opencircuit. This external source should drive a logic low at the voltage level of 0.3 VCC or below, and logic high at 0.7V VCC or above, up to 5.5V VCC. The XTAL1 input is 5V tolerant. Most of the quartz crystals in the range of 25MHz to 40MHz operate in the third overtone frequency mode. An external LC tank circuit at the XTAL2 output of the oscillator circuit is needed to achieve the third overtone frequency, as shown in Figure 15., page 52. Without this LC circuit, the crystal will oscillate at a fundamental frequency mode that is about 1/3 of the desired overtone frequency. Note: In Figure 15., page 52 crystals which are specified to operate in fundamental mode (not overtone mode) do not need the LC circuit components. Since quartz crystals and ceramic resonators have their own characteristics based on their manufacturer, it is wise to also consult the manufacturer’s recommended values for external components.uPSD33xx 52/231 Figure 15. Oscillator and Clock Connections Crystal or Resonator Usage Direct Drive XTAL1 (in) XTAL1 (in) XTAL2 (out) XTAL2 (out) C1 C2 XTAL (fOSC) L1 C3 External Ocsillator or No Connect Active Clock Source XTAL (fOSC) C1 = C2 C3 L1 Ceramic Resonator 40 - 50pF None Crystal, fundamental mode (3-40MHz) 15-33pF None None None Crystal, overtone mode (25-40MHz) 20pF 10nF 2.2µH AI0919853/231 uPSD33xx I/O PORTS OF MCU MODULE The MCU Module has three 8-bit I/O ports: Port 1, Port 3, and Port 4. The PSD Module has four other I/O ports: Port A, B, C, and D. This section describes only the I/O ports on the MCU Module. I/O ports will function as bi-directional General Purpose I/O (GPIO), but the port pins can have alternate functions assigned at run-time by writing to specific SFRs. The default operating mode (during and after reset) for all three ports is GPIO input mode. Port pins that have no external connection will not float because each pin has an internal weak pull-up (~150K ohms) to VCC. I/O ports 3 and 4 are 5V tolerant, meaning they can be driven/pulled externally up to 5.5V without damage. The pins on Port 4 have a higher current capability than the pins on Ports 1 and 3. Three additional MCU ports (only on 80-pin uPSD33xx devices) are dedicated to bring out the 8032 MCU address, data, and control signals to external pins. One port, named MCUA[11:8], contains four MCU address signal outputs. Another port, named MCUAD[7:0], has eight multiplexed address/data bidirectional signals. The third port has MCU bus control outputs: read, write, program fetch, and address latch. These ports are typically used to connect external parallel peripherals and memory devices, but they may NOT be used as GPIO. Notice that only four of the eight upper address signals come out to pins on the port MCUA[11:8]. If additional high-order address signals are required on external pins (MCU addresses A[15:12]), then these address signals can be brought out as needed to PLD output pins or to the Address Out mode pins on PSD Module ports. See PSD Module section, “Latched Address Output Mode, page 177 for details. Figure 16., page 55 represents the flexibility of pin function routing controlled by the SFRs. Each of the 24 pins on three ports, P1, P3, and P4, may be individually routed on a pin-by-pin basis to a desired function. MCU Port Operating Modes MCU port pins can operate as GPIO or as alternate functions (see Figure 17., page 56 through Figure 19., page 57). Depending on the selected pin function, a particular pin operating mode will automatically be used: ■ GPIO - Quasi-bidirectional mode ■ UART0, UART1 - Quasi-bidirectional mode ■ SPI - Quasi-bidirectional mode ■ I2C - Open drain mode ■ ADC - Analog input mode ■ PCA output - Push-Pull mode ■ PCA input - Input only (Quasi-bidirectional) ■ Timer 0,1,2 - Input only (Quasi-bidirectional) GPIO Function. Ports in GPIO mode operate as quasi-bidirectional pins, consistent with standard 8051 architecture. GPIO pins are individually controlled by three SFRs: ■ SFR, P1 (Table 25., page 57) ■ SFR, P3 (Table 26., page 58) ■ SFR, P4 (Table 27., page 58) These SFRs can be accessed using the Bit Addressing mode, an efficient way to control individual port pins. GPIO Output. Simply stated, when a logic '0' is written to a bit in any of these port SFRs while in GPIO mode, the corresponding port pin will enable a low-side driver, which pulls the pin to ground, and at the same time releases the high-side driver and pull-ups, resulting in a logic'0' output. When a logic '1' is written to the SFR, the low-side driver is released, the high-side driver is enabled for just one MCU_CLK period to rapidly make the 0-to1 transition on the pin, while weak active pull-ups (total ~150K ohms) to VCC are enabled. This structure is consistent with standard 8051 architecture. The high side driver is momentarily enabled only for 0-to-1 transitions, which is implemented with the delay function at the latch output as pictured in Figure 17., page 56 through Figure 19., page 57. After the high-side driver is disabled, the two weak pull-ups remain enabled resulting in a logic '1' output at the pin, sourcing IOH uA to an external device. Optionally, an external pull-up resistor can be added if additional source current is needed while outputting a logic '1.'uPSD33xx 54/231 GPIO Input. To use a GPIO port pin as an input, the low-side driver to ground must be disabled, or else the true logic level being driven on the pin by an external device will be masked (always reads logic '0'). So to make a port pin “input ready”, the corresponding bit in the SFR must have been set to a logic '1' prior to reading that SFR bit as an input. A reset condition forces SFRs P1, P3, and P4 to FFh, thus all three ports are input ready after reset. When a pin is used as an input, the stronger pullup “A” maintains a solid logic '1' until an external device drives the input pin low. At this time, pull-up “A” is automatically disabled, and only pull-up “B” will source the external device IIH uA, consistent with standard 8051 architecture. GPIO Bi-Directional. It is possible to operate individual port pins in bi-directional mode. For an output, firmware would simply write the corresponding SFR bit to logic '1' or '0' as needed. But before using the pin as an input, firmware must first ensure that a logic '1' was the last value written to the corresponding SFR bit prior to reading that SFR bit as an input. GPIO Current Capability. A GPIO pin on Port 4 can sink twice as much current than a pin on either Port 1 or Port 3 when the low-side driver is outputting a logic '0' (IOL). See the DC specifications at the end of this document for full details. Reading Port Pin vs. Reading Port Latch. When firmware reads the GPIO ports, sometimes the actual port pin is sampled in hardware, and sometimes the port SFR latch is read and not the actual pin, depending on the type of MCU instruction used. These two data paths are shown in Figure 17., page 56 through Figure 19., page 57. SFR latches are read (and not the pins) only when the read is part of a read-modify-write instruction and the write destination is a bit or bits in a port SFR. These instructions are: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ, MOV, CLR, and SETB. All other types of reads to port SFRs will read the actual pin logic level and not the port latch. This is consistent with 8051 architecture.55/231 uPSD33xx Figure 16. MCU Module Port Pin Function Routing 8 P3 P1 P4 M C U A D M C U A GPIO (8) UART0 (2) TIMER0/1 (4) I 2C (2) GPIO (8) GPIO (8) TIMER2 (2) UART1 (2) SPI (4) ADC (8) PCA (8) 8032 MCU CORE Low Addr & Data[7:0] 8 Available on PSD Hi Address [15:12] Hi Address [11:8] 4 Module Pins MCU Module 4 On 80-pin Devices Only Ports C N T L RD, WR, PSEN, ALE 4 SFR 8 8 SFR SFR SFR SFR SFR AI09199uPSD33xx 56/231 Figure 17. MCU I/O Cell Block Diagram for Port 1 Figure 18. MCU I/O Cell Block Diagram for Port 3 P1.X Pin Analog_Alt_Func_En Analog_Pin_In D Q PRE SFR P1.X Latch 8032 Data Bus Bit GPIO P1.X SFR Write Latch MCU_Reset P1.X SFR Read Latch (for R-M-W instructions) P1.X SFR Read Pin Select_Alternate_Func Digital_Pin_Data_In IN 1 IN 0 MUX Y VCC VCC VCC SEL WEAK PULL-UP, B STONGER PULL-UP, A LOW SIDE HIGH SIDE DELAY, 1 MCU_CLK DELAY, 1 MCU_CLK Q Digital_Alt_Func_Data_Out AI09600 P3.X Pin Digital_Pin_Data_In D Q PRE SFR P3.X Latch 8032 Data Bus Bit GPIO P3.X SFR Write Latch MCU_Reset P3.X SFR Read Latch (for R-M-W instructions) P3.X SFR Read Pin Select_Alternate_Func Disables High-Side Driver IN 1 IN 0 MUX Y VCC VCC VCC SEL Enable_I2C WEAK PULL-UP, B STONGER PULL-UP, A LOW SIDE HIGH SIDE DELAY, 1 MCU_CLK DELAY, 1 MCU_CLK Q Digital_Alt_Func_Data_Out AI0960157/231 uPSD33xx Figure 19. MCU I/O Cell Block Diagram for Port 4 Table 25. P1: I/O Port 1 Register (SFR 90h, reset value FFh) Note: 1. Write '1' or '0' for pin output. Read for pin input, but prior to READ, this bit must have been set to '1' by firmware or by a reset event. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Details Bit Symbol R/W Function(1) 7 P1.7 R,W Port pin 1.7 6 P1.6 R,W Port pin 1.6 5 P1.5 R,W Port pin 1.5 4 P1.4 R,W Port pin 1.4 3 P1.3 R,W Port pin 1.3 2 P1.2 R,W Port pin 1.2 1 P1.1 R,W Port pin 1.1 0 P1.0 R,W Port pin 1.0 P4.X Pin Digital_Pin_Data_In D Q PRE SFR P4.X Latch 8032 Data Bus Bit GPIO P4.X SFR Write Latch MCU_Reset P4.X SFR Read Latch (for R-M-W instructions) P4.X SFR Read Pin Select_Alternate_Func For PCA Alternate Function IN 1 IN 0 MUX Y VCC VCC VCC SEL Enable_Push_Pull WEAK PULL-UP, B STONGER PULL-UP, A LOW SIDE HIGH SIDE DELAY, 1 MCU_CLK DELAY, 1 MCU_CLK Q Digital_Alt_Func_Data_Out AI09602uPSD33xx 58/231 Table 26. P3: I/O Port 3 Register (SFR B0h, reset value FFh) Note: 1. Write '1' or '0' for pin output. Read for pin input, but prior to READ, this bit must have been set to '1' by firmware or by a reset event. Table 27. P4: I/O Port 4 Register (SFR C0h, reset value FFh) Note: 1. Write '1' or '0' for pin output. Read for pin input, but prior to READ, this bit must have been set to '1' by firmware or by a reset event. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 Details Bit Symbol R/W Function(1) 7 P3.7 R,W Port pin 3.7 6 P3.6 R,W Port pin 3.6 5 P3.5 R,W Port pin 3.5 4 P3.4 R,W Port pin 3.4 3 P3.3 R,W Port pin 3.3 2 P3.2 R,W Port pin 3.2 1 P3.1 R,W Port pin 3.1 0 P3.0 R,W Port pin 3.0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 Details Bit Symbol R/W Function(1) 7 P4.7 R,W Port pin 4.7 6 P4.6 R,W Port pin 4.6 5 P4.5 R,W Port pin 4.5 4 P4.4 R,W Port pin 4.4 3 P4.3 R,W Port pin 4.3 2 P4.2 R,W Port pin 4.2 1 P4.1 R,W Port pin 4.1 0 P4.0 R,W Port pin 4.059/231 uPSD33xx Alternate Functions. There are five SFRs used to control the mapping of alternate functions onto MCU port pins, and these SFRs are depicted as switches in Figure 16., page 55. ■ Port 3 uses the SFR, P3SFS (Table 28., page 60). ■ Port 1 uses SFRs, P1SFS0 (Table 29., page 60) and P1SFS1 (Table 30., page 60). ■ Port 4 uses SFRs, P4SFS0 (Table 32., page 61) and P4SFS1 (Table 33., page 61). Since these SFRs are cleared by a reset, then by default all port pins function as GPIO (not the alternate function) until firmware initializes these SFRs. Each pin on each of the three ports can be independently assigned a different function on a pinby-pin basis. The peripheral functions Timer 2, UART1, and I2C may be split independently between Port 1 and Port 4 for additional flexibility by giving a wider choice of peripheral usage on a limited number of device pins. When the selected alternate function is UART0, UART1, or SPI, then the related pins are in quasibidirectional mode, including the use of the highside driver for rapid 0-to-1 output transitions. The high-side driver is enabled for just one MCU_CLK period on 0-to-1 transitions by the delay function at the “digital_alt_func_data_out” signal pictured in Figure 17., page 56 through Figure 19., page 57. If the alternate function is Timer 0, Timer 1, Timer 2, or PCA input, then the related pins are in quasibidirectional mode, but input only. If the alternate function is ADC, then for each pin the pull-ups, the high-side driver, and the low-side driver are disabled. The analog input is routed directly to the ADC unit. Only Port 1 supports analog functions (Figure 17., page 56). Port 1 is not 5V tolerant. If the alternate function is I2C, the related pins will be in open drain mode, which is just like quasi-bidirectional mode but the high-side driver is not enabled for one cycle when outputting a 0-to-1 transition. Only the low-side driver and the internal weak pull-ups are used. Only Port 3 supports open-drain mode (Figure 18., page 56). I2C requires the use of an external pull-up resistor on each bus signal, typically 4.7KΩ to VCC. If the alternate function is PCA output, then the related pins are in push-pull mode, meaning the pins are actively driven and held to logic '1' by the highside driver, or actively driven and held to logic '0' by the low-side driver. Only Port 4 supports pushpull mode (Figure 19., page 57). Port 4 push-pull pins can source IOH current when driving logic '1,' and sink IOL current when driving logic '0.' This current is significantly more than the capability of pins on Port 1 or Port 3 (see Table 129., page 207). For example, to assign these port functions: ■ Port 1: UART1, ADC[1:0], P1[7:4] are GPIO ■ Port 3: UART0, I2C, P3[5:2] are GPIO ■ Port 4: TCM0, SPI, P4[3:1] are GPIO The following values need to be written to the SFRs: P1SFS0 = 00001111b, or 0Fh P1SFS1 = 00000011b , or 03h P3SFS = 11000011b, or C3h P4SFS0 = 11110001b, or F1h P4SFS1 = 11110000b, or F0huPSD33xx 60/231 Table 28. P3SFS: Port 3 Special Function Select Register (SFR 91h, reset value 00h) Table 29. P1SFS0: Port 1 Special Function Select 0 Register (SFR 8Eh, reset value 00h) Table 30. P1SFS1: Port 1 Special Function Select 1 Register (SFR 8Fh, reset value 00h) Table 31. P1SFS0 and P1SFS1 Details Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3SFS7 P3SFS6 P3SFS5 P3SFS4 P3SFS3 P3SFS2 P3SFS1 P3SFS0 Details Port 3 Pin R/W Default Port Function Alternate Port Function P3SFS[i] - 0; Port 3 Pin, i = 0..7 P3SFS[i] - 1; Port 3 Pin, i = 0..7 0 R,W GPIO UART0 Receive, RXD0 1 R,W GPIO UART0 Transmit, TXD0 2 R,W GPIO Ext Intr 0/Timer 0 Gate, EXT0INT/TG0 3 R,W GPIO Ext Intr 1/Timer 1 Gate, EXT1INT/TG1 4 R,W GPIO Counter 0 Input, C0 5 R,W GPIO Counter 0 Input, C1 6 R,W GPIO I 2C Data, I2CSDA 7 R,W GPIO I 2C Clock, I2CCL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1SF07 P1SF06 P1SF05 P1SF04 P1SF03 P1SF02 P1SF01 P1SF00 Details Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1SF17 P1SF16 P1SF15 P1SF14 P1SF13 P1SF12 P1SF11 P1SF10 Port 1 Pin R/W Default Port Function Alternate 1 Port Function Alternate 2 Port Function P1SFS0[i] = 0 P1SFS1[i] = x P1SFS0[i] = 1 P1SFS1[i] = 0 P1SFS0[i] = 1 P1SFS1[i] = 1 Port 1 Pin, i = 0.. 7 Port 1 Pin, i = 0.. 7 Port 1 Pin, i = 0.. 7 0 R,W GPIO Timer 2 Count Input, T2 ADC Chn 0 Input, ADC0 1 R,W GPIO Timer 2 Trigger Input, TX2 ADC Chn 1 Input, ADC1 2 R,W GPIO UART1 Receive, RXD1 ADC Chn 2 Input, ADC2 3 R,W GPIO UART1 Transmit, TXD1 ADC Chn 3 Input, ADC3 4 R,W GPIO SPI Clock, SPICLK ADC Chn 4 Input, ADC4 5 R,W GPIO SPI Receive, SPIRXD ADC Chn 5 Input, ADC5 6 R,W GPIO SPI Transmit, SPITXD ADC Chn 6 Input, ADC6 7 R,W GPIO SPI Select, SPISEL_ ADC Chn 7 Input, ADC761/231 uPSD33xx Table 32. P4SFS0: Port 4 Special Function Select 0 Register (SFR 92h, reset value 00h) Table 33. P4SFS1: Port 4 Special Function Select 1 Register (SFR 93h, reset value 00h) Table 34. P4SFS0 and P4SFS1 Details Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4SF07 P4SF06 P4SF05 P4SF04 P4SF03 P4SF02 P4SF01 P4SF00 Details Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4SF17 P4SF16 P4SF15 P4SF14 P4SF13 P4SF12 P4SF11 P4SF10 Port 4 Pin R/W Default Port Function Alternate 1 Port Function Alternate 2 Port Function P4SFS0[i] = 0 P4SFS1[i] = x P4SFS0[i] = 1 P4SFS1[i] = 0 P4SFS0[i] = 1 P4SFS1[i] = 1 Port 4 Pin, i = 0.. 7 Port 4 Pin, i = 0.. 7 Port 4 Pin, i = 0.. 7 0 R,W GPIO PCA0 Module 0, TCM0 Timer 2 Count Input, T2 1 R,W GPIO PCA0 Module 1, TCM1 Timer 2 Trigger Input, TX2 2 R,W GPIO PCA0 Module 2, TCM2 UART1 Receive, RXD1 3 R,W GPIO PCA0 Ext Clock, PCACLK0 UART1 Transmit, TXD1 4 R,W GPIO PCA1 Module 3, TCM3 SPI Clock, SPICLK 5 R,W GPIO PCA1 Module 4, TCM4 SPI Receive, SPIRXD 6 R,W GPIO PCA1 Module 5, TCM5 SPI Transmit, SPITXD 7 R,W GPIO PCA1 Ext Clock, PCACLK1 SPI Select, SPISEL_uPSD33xx 62/231 MCU BUS INTERFACE The MCU Module has a programmable bus interface. It is based on a standard 8032 bus, with eight data signals multiplexed with eight low-order address signals (AD[7:0]). It also has eight high-order non-multiplexed address signals (A[15:8]). Time multiplexing is controlled by the address latch signal, ALE. This bus connects the MCU Module to the PSD Module, and also connects to external pins only on 80-pin devices. See the AC specifications section at the end of this document for external bus timing on 80-pin devices. Four types of data transfers are supported, each transfer is to/from a memory location external to the MCU Module: – Code Fetch cycle using the PSEN signal: fetch a code byte for execution – Code Read cycle using PSEN: read a code byte using the MOVC (Move Constant) instruction – XDATA Read cycle using the RD signal: read a data byte using the MOVX (Move eXternal) instruction – XDATA Write cycle using the WR signal: write a data byte using the MOVX instruction The number of MCU_CLK periods for these transfer types can be specified at runtime by firmware writing to the SFR register named BUSCON (Table 35., page 63). Here, the number of MCU_CLK clock pulses per bus cycle are specified to maximize performance. Important: By default, the BUSCON Register is loaded with long bus cycle times (6 MCU_CLK periods) after a reset condition. It is important that the post-reset initialization firmware sets the bus cycle times appropriately to get the most performance, according to Table 36., page 64. Keep in mind that the PSD Module has a faster Turbo Mode (default) and a slower but less power consuming Non-Turbo Mode. The bus cycle times must be programmed in BUSCON to optimize for each mode as shown in Table 36., page 64. See PLD NonTurbo Mode, page 192 for more details. Bus Read Cycles (PSEN or RD) When the PSEN signal is used to fetch a byte of code, the byte is read from the PSD Module or external device and it enters the MCU Pre-Fetch Queue (PFQ). When PSEN is used during a MOVC instruction, or when the RD signal is used to read a byte of data, the byte is routed directly to the MCU, bypassing the PFQ. Bits in the BUSCON Register determine the number of MCU_CLK periods per bus cycle for each of these kinds of transfers to all address ranges. It is not possible to specify in the BUSCON Register a different number of MCU_CLK periods for various address ranges. For example, the user cannot specify 4 MCU_CLK periods for RD read cycles to one address range on the PSD Module, and 5 MCU_CLK periods for RD read cycles to a different address range on an external device. However, the user can specify one number of clock periods for PSEN read cycles and a different number of clock periods for RD read cycles. Note 1: A PSEN bus cycle in progress may be aborted before completion if the PFQ and Branch Cache (BC) determines the current code fetch cycle is not needed. Note 2: Whenever the same number of MCU_CLK periods is specified in BUSCON for both PSEN and RD cycles, the bus cycle timing is typically identical for each of these types of bus cycles. In this case, the only time PSEN read cycles are longer than RD read cycles is when the PFQ issues a stall while reloading. PFQ stalls do not affect RD read cycles. By comparison, in many traditional 8051 architectures, RD bus cycles are always longer than PSEN bus cycles. Bus Write Cycles (WR) When the WR signal is used, a byte of data is written directly to the PSD Module or external device, no PFQ or caching is involved. Bits in the BUSCON Register determine the number of MCU_CLK periods for bus write cycles to all addresses. It is not possible to specify in BUSCON a different number of MCU_CLK periods for writes to various address ranges. Controlling the PFQ and BC The BUSCON Register allows firmware to enable and disable the PFQ and BC at run-time. Sometimes it may be desired to disable the PFQ and BC to ensure deterministic execution. The dynamic action of the PFQ and BC may cause varying program execution times depending on the events that happen prior to a particular section of code of interest. For this reason, it is not recommended to implement timing loops in firmware, but instead use one of the many hardware timers in the uPSD33xx. By default, the PFQ and BC are enabled after a reset condition. Important: Disabling the PFQ or BC will seriously reduce MCU performance.63/231 uPSD33xx Table 35. BUSCON: Bus Control Register (SFR 9Dh, reset value EBh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EPFQ EBC WRW[1:0] RDW[1:0] CW[1:0] Details Bit Symbol R/W Definition 7 EPFQ R,W Enable Pre-Fetch Queue 0 = PFQ is disabled 1 = PFQ is enabled (default) 6 EBC R,W Enable Branch Cache 0 = BC is disabled 1 = BC is enabled (default) 5:4 WRW[1:0] R,W WR Wait, number of MCU_CLK periods for WR write bus cycle during any MOVX instruction 00b: 4 clock periods 01b: 5 clock periods 10b: 6 clock periods (default) 11b: 7 clock periods 3:2 RDW[1:0] R,W RD Wait, number of MCU_CLK periods for RD read bus cycle during any MOVX instruction 00b: 4 clock periods 01b: 5 clock periods 10b: 6 clock periods (default) 11b: 7 clock periods 1:0 CW[1:0] R,W Code Wait, number of MCU_CLK periods for PSEN read bus cycle during any code byte fetch or during any MOVC code byte read instruction. Periods will increase with PFQ stall 00b: 3 clock periods - exception, for MOVC instructions this setting results 4 clock periods 01b: 4 clock periods 10b: 5 clock periods 11b: 6 clock periods (default)uPSD33xx 64/231 Table 36. Number of MCU_CLK Periods Required to Optimize Bus Transfer Rate Note: 1. VDD of the PSD Module 2. “Turbo mode PSD” means that the PSD Module is in the faster, Turbo mode (default condition). A PSD Module in Non-Turbo mode is slower, but consumes less current. See PSD Module section, titled “PLD Non-Turbo Mode” for details. MCU Clock Frequency, MCU_CLK (fMCU) CW[1:0] Clk Periods RDW[1:0] Clk Periods WRW[1:0] Clk Periods 3.3V(1) 5V(1) 3.3V(1) 5V(1) 3.3V(1) 5V(1) 40MHz, Turbo mode PSD(2) 545454 40MHz, Non-Turbo mode PSD 6 5 6 5 6 5 36MHz, Turbo mode PSD 545454 36MHz, Non-Turbo mode PSD 6 4 6 4 6 4 32MHz, Turbo mode PSD 545454 32MHz, Non-Turbo mode PSD 5 4 5 4 5 4 28MHz, Turbo mode PSD 434444 28MHz, Non-Turbo mode PSD 5 4 5 4 5 4 24MHz, Turbo mode PSD 434444 24MHz, Non-Turbo mode PSD 4 3 4 4 4 4 20MHz and below, Turbo mode PSD 334444 20MHz and below, Non-Turbo mode PSD 3 3 4 4 4 465/231 uPSD33xx SUPERVISORY FUNCTIONS Supervisory circuitry on the MCU Module will issue an internal reset signal to the MCU Module and simultaneously to the PSD Module as a result of any of the following four events: – The external RESET_IN pin is asserted – The Low Voltage Detect (LVD) circuitry has detected a voltage on VCC below a specific threshold (power-on or voltage sags) – The JTAG Debug interface has issued a reset command – The Watch Dog Timer (WDT) has timed out The resulting internal reset signal, MCU_RESET, will force the 8032 into a known reset state while asserted, and then 8032 program execution will jump to the reset vector at program address 0000h just after MCU_RESET is deasserted. The MCU Module will also assert an active low internal reset signal, RESET, to the PSD Module. If needed, the signal RESET can be driven out to external system components through any PLD output pin on the PSD Module. When driving this “RESET_OUT” signal from a PLD output, the user can choose to make it either active-high or activelow logic, depending on the PLD equation. External Reset Input Pin, RESET_IN The RESET_IN pin can be connected directly to a mechanical reset switch or other device which pulls the signal to ground to invoke a reset. RESET_IN is pulled up internally and enters a Schmitt trigger input buffer with a voltage hysteresis of VRST_HYS for immunity to the effects of slow signal rise and fall times, as shown in Figure 20. RESET_IN is also filtered to reject a voltage spike less than a duration of tRST_FIL. The RESET_IN signal must be maintained at a logic '0' for at least a duration of tRST_LO_IN while the oscillator is running. The resulting MCU_RESET signal will last only as long as the RESET_IN signal is active (it is not stretched). Refer to the Supervisor AC specifications in Table 150., page 221 at the end of this document for these parameter values. Figure 20. Supervisor Reset Generation S Q MCU Clock Sync Noise Filter VCC PIN PULL-UP DELAY, tRST_ACTV R AI09603 RESET_IN RESET to PSD Module MCU_RESET to MCU and Peripherals LVD JTAG Debug WDTuPSD33xx 66/231 Low VCC Voltage Detect, LVD An internal reset is generated by the LVD circuit when VCC drops below the reset threshold, VLV_THRESH. After VCC returns to the reset threshold, the MCU_RESET signal will remain asserted for tRST_ACTV before it is released. The LVD circuit is always enabled (cannot be disabled by SFR), even in Idle Mode and Power-down Mode. The LVD input has a voltage hysteresis of VRST_HYS and will reject voltage spikes less than a duration of tRST_FIL. Important: The LVD voltage threshold is VLV_THRESH, suitable for monitoring both the 3.3V VCC supply on the MCU Module and the 3.3V VDD supply on the PSD Module for 3.3V uPSD33xxV devices, since these supplies are one in the same on the circuit board. However, for 5V uPSD33xx devices, VLV_THRESH is not suitable for monitoring the 5V VDD voltage supply (VLV_THRESH is too low), but good for monitoring the 3.3V VCC supply. In the case of 5V uPSD33xx devices, an external means is required to monitor the separate 5V VDD supply, if desired. Power-up Reset At power up, the internal reset generated by the LVD circuit is latched as a logic '1' in the POR bit of the SFR named PCON (Table 24., page 50). Software can read this bit to determine whether the last MCU reset was the result of a power up (cold reset) or a reset from some other condition (warm reset). This bit must be cleared with software. JTAG Debug Reset The JTAG Debug Unit can generate a reset for debugging purposes. This reset source is also available when the MCU is in Idle Mode and PowerDown Mode (the JTAG debugger can be used to exit these modes). Watchdog Timer, WDT When enabled, the WDT will generate a reset whenever it overflows. Firmware that is behaving correctly will periodically clear the WDT before it overflows. Run-away firmware will not be able to clear the WDT, and a reset will be generated. By default, the WDT is disabled after each reset. Note: The WDT is not active during Idle mode or Power-down Mode. There are two SFRs that control the WDT, they are WDKEY (Table 37., page 68) and WDRST (Table 38., page 68). If WDKEY contains 55h, the WDT is disabled. Any value other than 55h in WDKEY will enable the WDT. By default, after any reset condition, WDKEY is automatically loaded with 55h, disabling the WDT. It is the responsibility of initialization firmware to write some value other than 55h to WDKEY after each reset if the WDT is to be used. The WDT consists of a 24-bit up-counter (Figure 21), whose initial count is 000000h by default after every reset. The most significant byte of this counter is controlled by the SFR, WDRST. After being enabled by WDKEY, the 24-bit count is increased by 1 for each MCU machine cycle. When the count overflows beyond FFFFFh (224 MCU machine cycles), a reset is issued and the WDT is automatically disabled (WDKEY = 55h again). To prevent the WDT from timing out and generating a reset, firmware must repeatedly write some value to WDRST before the count reaches FFFFFh. Whenever WDRST is written, the upper 8 bits of the 24-bit counter are loaded with the written value, and the lower 16 bits of the counter are cleared to 0000h. The WDT time-out period can be adjusted by writing a value other that 00h to WDRST. For example, if WDRST is written with 04h, then the WDT will start counting 040000h, 040001h, 040002h, and so on for each MCU machine cycle. In this example, the WDT time-out period is shorter than if WDRST was written with 00h, because the WDT is an up-counter. A value for WDRST should never be written that results in a WDT time-out period shorter than the time required to complete the longest code task in the application, else unwanted WDT overflows will occur. Figure 21. Watchdog Counter 23 15 7 0 8-bits 8-bits 8-bits SFR, WDRST AI0960467/231 uPSD33xx The formula to determine WDT time-out period is: WDTPERIOD = tMACH_CYC x NOVERFLOW NOVERFLOW is the number of WDT up-counts required to reach FFFFFFh. This is determined by the value written to the SFR, WDRST. tMACH_CYC is the average duration of one MCU machine cycle. By default, an MCU machine cycle is always 4 MCU_CLK periods for uPSD33xx, but the following factors can sometimes add more MCU_CLK periods per machine cycle: – The number of MCU_CLK periods assigned to MCU memory bus cycles as determined in the SFR, BUSCON. If this setting is greater than 4, then machine cycles have additional MCU_CLK periods during memory transfers. – Whether or not the PFQ/BC circuitry issues a stall during a particular MCU machine cycle. A stall adds more MCU_CLK periods to a machine cycle until the stall is removed. tMACH_CYC is also affected by the absolute time of a single MCU_CLK period. This number is fixed by the following factors: – Frequency of the external crystal, resonator, or oscillator: (fOSC) – Bit settings in the SFR CCON0, which can divide fOSC and change MCU_CLK As an example, assume the following: 1. fOSC is 40MHz, thus its period is 25ns. 2. CCON0 is 10h, meaning no clock division, so the period of MCU_CLK is also 25ns. 3. BUSCON is C1h, meaning the PFQ and BC are enabled, and each MCU memory bus cycle is 4 MCU_CLK periods, adding no additional MCU_CLK periods to MCU machine cycles during memory transfers. 4. Assume there are no stalls from the PFQ/BC. In reality, there are occational stalls but their occurance has minimal impact on WDT timeout period. 5. WDRST contains 00h, meaning a full 224 upcounts are required to reach FFFFFh and generate a reset. In this example, tMACH_CYC = 100ns (4 MCU_CLK periods x 25ns) NOVERFLOW = 224 = 16777216 up-counts WDTPERIOD = 100ns X 16777216 = 1.67 seconds The actual value will be slightly longer due to PFQ/ BC. Firmware Example: The following 8051 assembly code illustrates how to operate the WDT. A simple statement in the reset initialization firmware enables the WDT, and then a periodic write to clear the WDT in the main firmware is required to keep the WDT from overflowing. This firmware is based on the example above (40MHz fOSC, CCON0 = 10h, BUSCON = C1h). For example, in the reset initialization firmware (the function that executes after a jump to the reset vector): Somewhere in the flow of the main program, this statement will execute periodically to reset the WDT before it’s time-out period of 1.67 seconds. For example: MOV AE, #AA ; enable WDT by writing value to ; WDKEY other than 55h MOV A6, #00 ; reset WDT, loading 000000h. ; Counting will automatically ; resume as long as 55h in not in ; WDKEYuPSD33xx 68/231 Table 37. WDKEY: Watchdog Timer Key Register (SFR AEh, reset value 55h) Table 38. WDRST: Watchdog Timer Reset Counter Register (SFR A6h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDKEY[7:0] Details Bit Symbol R/W Definition [7:0] WDKEY W 55h disables the WDT from counting. 55h is automatically loaded in this SFR after any reset condition, leaving the WDT disabled by default. Any value other than 55h written to this SFR will enable the WDT, and counting begins. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDRST[7:0] Details Bit Symbol R/W Definition [7:0] WDRST W This SFR is the upper byte of the 24-bit WDT up-counter. Writing this SFR sets the upper byte of the counter to the written value, and clears the lower two bytes of the counter to 0000h. Counting begins when WDKEY does not contain 55h.69/231 uPSD33xx STANDARD 8032 TIMER/COUNTERS There are three 8032-style 16-bit Timer/Counter registers (Timer 0, Timer 1, Timer 2) that can be configured to operate as timers or event counters. There are two additional 16-bit Timer/Counters in the Programmable Counter Array (PCA), seePCA Block, page 123 for details. Standard Timer SFRs Timer 0 and Timer 1 have very similar functions, and they share two SFRs for control: ■ TCON (Table 39., page 70) ■ TMOD (Table 40., page 72). Timer 0 has two SFRs that form the 16-bit counter, or that can hold reload values, or that can scale the clock depending on the timer/counter mode: ■ TH0 is the high byte, address 8Ch ■ TL0 is the low byte, address 8Ah Timer 1 has two similar SFRs: ■ TH1 is the high byte, address 8Dh ■ TL1 is the low byte, address 8Bh Timer 2 has one control SFR: ■ T2CON (Table 41., page 75) Timer 2 has two SFRs that form the 16-bit counter, and perform other functions: ■ TH2 is the high byte, address CDh ■ TL2 is the low byte, address CCh Timer 2 has two SFRs for capture and reload: ■ RCAP2H is the high byte, address CBh ■ RCAP2L is the low byte, address CAh Clock Sources When enabled in the “Timer” function, the Registers THx and TLx are incremented every 1/12 of the oscillator frequency (fOSC). This timer clock source is not effected by MCU clock dividers in the CCON0, stalls from PFQ/BC, or bus transfer cycles. Timers are always clocked at 1/12 of fOSC. When enabled in the “Counter” function, the Registers THx and TLx are incremented in response to a 1-to-0 transition sampled at their corresponding external input pin: pin C0 for Timer 0; pin C1 for Timer 1; or pin T2 for Timer 2. In this function, the external clock input pin is sampled by the counter at a rate of 1/12 of fOSC. When a logic '1' is determined in one sample, and a logic '0' in the next sample period, the count is incremented at the very next sample period (period1: sample=1, period2: sample=0, period3: increment count while continuing to sample). This means the maximum count rate is 1/24 of the fOSC. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be active for at least one full sample period (12 / fOSC, seconds). However, if MCU_CLK is divided by the SFR CCON0, then the sample period must be calculated based on the resultant, longer, MCU_CLK frequency. In this case, an external clock signal on pins C0, C1, or T2 should have a duration longer than one MCU machine cycle, tMACH_CYC. The section, Watchdog Timer, WDT, page 66 explains how to estimate tMACH_CYC.uPSD33xx 70/231 Table 39. TCON: Timer Control Register (SFR 88h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Details Bit Symbol R/W Definition 7 TF1 R Timer 1 overflow interrupt flag. Set by hardware upon overflow. Automatically cleared by hardware after firmware services the interrupt for Timer 1. 6 TR1 R,W Timer 1 run control. 1 = Timer/Counter 1 is on, 0 = Timer/Counter 1 is off. 5 TF0 R Timer 0 overflow interrupt flag. Set by hardware upon overflow. Automatically cleared by hardware after firmware services the interrupt for Timer 0. 4 TR0 R,W Timer 0 run control. 1 = Timer/Counter 0 is on, 0 = Timer/Counter 0 is off. 3 IE1 R Interrupt flag for external interrupt pin, EXTINT1. Set by hardware when edge is detected on pin. Automatically cleared by hardware after firmware services EXTINT1 interrupt. 2 IT1 R,W Trigger type for external interrupt pin EXTINT1. 1 = falling edge, 0 = lowlevel 1 IE0 R Interrupt flag for external interrupt pin, EXTINT0. Set by hardware when edge is detected on pin. Automatically cleared by hardware after firmware services EXTINT0 interrupt. 0 IT0 R,W Trigger type for external interrupt pin EXTINT0. 1 = falling edge, 0 = lowlevel71/231 uPSD33xx SFR, TCON Timer 0 and Timer 1 share the SFR, TCON, that controls these timers and provides information about them. See Table 39., page 70. Bits IE0 and IE1 are not related to Timer/Counter functions, but they are set by hardware when a signal is active on one of the two external interrupt pins, EXTINT0 and EXTINT1. For system information on all of these interrupts, see Table 16., page 41, Interrupt Summary. Bits IT0 and IT1 are not related to Timer/Counter functions, but they control whether or not the two external interrupt input pins, EXTINT0 and EXTINT1 are edge or level triggered. SFR, TMOD Timer 0 and Timer 1 have four modes of operation controlled by the SFR named TMOD (Table 40). Timer 0 and Timer 1 Operating Modes The “Timer” or “Counter” function is selected by the C/T control bits in TMOD. The four operating modes are selected by bit-pairs M[1:0] in TMOD. Modes 0, 1, and 2 are the same for both Timer/ Counters. Mode 3 is different. Mode 0. Putting either Timer/Counter into Mode 0 makes it an 8-bit Counter with a divide-by-32 prescaler. Figure 22 shows Mode 0 operation as it applies to Timer 1 (same applies to Timer 0). In this mode, the Timer Register is configured as a 13-bit register. As the count rolls over from all '1s' to all '0s,' it sets the Timer Interrupt flag TF1. The counted input is enabled to the Timer when TR1 = 1 and either GATE = 0 or EXTINT1 = 1. (Setting GATE = 1 allows the Timer to be controlled by external input pin, EXTINT1, to facilitate pulse width measurements). TR1 is a control bit in the SFR, TCON. GATE is a bit in the SFR, TMOD. The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Setting the run flag, TR1, does not clear the registers. Mode 0 operation is the same for the Timer 0 as for Timer 1. Substitute TR0, TF0, C0, TL0, TH0, and EXTINT0 for the corresponding Timer 1 signals in Figure 22. There are two different GATE Bits, one for Timer 1 and one for Timer 0. Mode 1. Mode 1 is the same as Mode 0, except that the Timer Register is being run with all 16 bits. Mode 2. Mode 2 configures the Timer Register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 23., page 73. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset with firmware. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0. Mode 3. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 24., page 73. TL0 uses the Timer 0 control Bits: C/T, GATE, TR0, and TF0, as well as the pin EXTINT0. TH0 is locked into a timer function (counting at a rate of 1/12 fOSC) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the “Timer 1“ interrupt flag. Mode 3 is provided for applications requiring an extra 8-bit timer on the counter (see Figure 24., page 73). With Timer 0 in Mode 3, a uPSD33xx device can look like it has three Timer/ Counters (not including the PCA). When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt.uPSD33xx 72/231 Table 40. TMOD: Timer Mode Register (SFR 89h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GATE C/T M[1:0] GATE C/T M[1:0] Details Bit Symbol R/W Timer Definition (T/C is abbreviation for Timer/Counter) 7 GATE R,W Timer 1 Gate control. When GATE = 1, T/C is enabled only while pin EXTINT1 is '1' and the flag TR1 is '1.' When GATE = 0, T/C is enabled whenever the flag TR1 is '1.' 6 C/T R,W Counter or Timer function select. When C/T = 0, function is timer, clocked by internal clock. C/T = 1, function is counter, clocked by signal sampled on external pin, C1. [5:4] M[1:0] R,W Mode Select. 00b = 13-bit T/C. 8 bits in TH1 with TL1 as 5-bit prescaler. 01b = 16-bit T/C. TH1 and TL1 are cascaded. No prescaler. 10b = 8-bit auto-reload T/C. TH1 holds a constant and loads into TL1 upon overflow. 11b = Timer Counter 1 is stopped. 3 GATE R,W Timer 0 Gate control. When GATE = 1, T/C is enabled only while pin EXTINT0 is '1' and the flag TR0 is '1.' When GATE = 0, T/C is enabled whenever the flag TR0 is '1.' 2 C/T R,W Counter or Timer function select. When C/T = 0, function is timer, clocked by internal clock. C/T = 1, function is counter, clocked by signal sampled on external pin, C0. [1:0] M[1:0] R,W Mode Select. 00b = 13-bit T/C. 8 bits in TH0 with TL0 as 5-bit prescaler. 01b = 16-bit T/C. TH0 and TL0 are cascaded. No prescaler. 10b = 8-bit auto-reload T/C. TH0 holds a constant and loads into TL0 upon overflow. 11b = TL0 is 8-bit T/C controlled by standard Timer 0 control bits. TH0 is a separate 8-bit timer that uses Timer 1 control bits.73/231 uPSD33xx Figure 22. Timer/Counter Mode 0: 13-bit Counter Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload Figure 24. Timer/Counter Mode 3: Two 8-bit Counters AI06622 f OSC TF1 Interrupt Gate TR1 EXTINT1 pin C1 pin Control TL1 (5 bits) TH1 (8 bits) C/T = 0 C/T = 1 ÷ 12 AI06623 f OSC TF1 Interrupt Gate TR1 EXTINT1 pin C1 pin Control TL1 (8 bits) TH1 (8 bits) C/T = 0 C/T = 1 ÷ 12 AI06624 f OSC TF0 Interrupt Gate TR0 EXTINT0 pin C0 pin Control TL0 (8 bits) C/T = 0 C/T = 1 ÷ 12 f OSC TF1 Interrupt Control TH0 (8 bits) ÷ 12 TR1uPSD33xx 74/231 Timer 2 Timer 2 can operate as either an event timer or as an event counter. This is selected by the bit C/T2 in the SFR named, T2CON (Table 41., page 75). Timer 2 has three operating modes selected by bits in T2CON, according to Table 42., page 76. The three modes are: ■ Capture mode ■ Auto re-load mode ■ Baud rate generator mode Capture Mode. In Capture Mode there are two options which are selected by the bit EXEN2 in T2CON. Figure 25., page 79 illustrates Capture mode. If EXEN2 = 0, then Timer 2 is a 16-bit timer if C/T2 = 0, or it’s a 16-bit counter if C/T2 = 1, either of which sets the interrupt flag bit TF2 upon overflow. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input pin T2X causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into Registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2X causes interrupt flag bit EXF2 in T2CON to be set. Either flag TF2 or EXF2 will generate an interrupt and the MCU must read both flags to determine the cause. Flags TF2 and EXF2 are not automatically cleared by hardware, so the firmware servicing the interrupt must clear the flag(s) upon exit of the interrupt service routine. Auto-reload Mode. In the Auto-reload Mode, there are again two options, which are selected by the bit EXEN2 in T2CON. Figure 26., page 79 shows Auto-reload mode. If EXEN2 = 0, then when Timer 2 counts up and rolls over from FFFFh it not only sets the interrupt flag TF2, but also causes the Timer 2 registers to be reloaded with the 16-bit value contained in Registers RCAP2L and RCAP2H, which are preset with firmware. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2X will also trigger the 16-bit reload and set the interrupt flag EXF2. Again, firmware servicing the interrupt must read both TF2 and EXF2 to determine the cause, and clear the flag(s) upon exit. Note: The uPSD33xx does not support selectable up/down counting in Auto-reload mode (this feature was an extension to the original 8032 architecture).75/231 uPSD33xx Table 41. T2CON: Timer 2 Control Register (SFR C8h, reset value 00h) Note: 1. The RCLK1 and TCLK1 Bits in the SFR named PCON control UART1, and have the exact same function as RCLK and TCLK. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 Details Bit Symbol R/W Definition 7 TF2 R,W Timer 2 flag, causes interrupt if enabled. TF2 is set by hardware upon overflow. Must be cleared by firmware. TF2 will not be set when either RCLK or TCLK =1. 6 EXF2 R,W Timer 2 flag, causes interrupt if enabled. EXF2 is set when a capture or reload is caused by a negative transition on T2X pin and EXEN2 = 1. EXF2 must be cleared by firmware. 5 RCLK(1) R,W UART0 Receive Clock control. When RCLK = 1, UART0 uses Timer 2 overflow pulses for its receive clock in Modes 1 and 3. RCLK=0, Timer 1 overflow is used for its receive clock 4 TCLK(1) R,W UART0 Transmit Clock control. When TCLK = 1, UART0 uses Timer 2 overflow pulses for its transmit clock in Modes 1 and 3. TCLK=0, Timer 1 overflow is used for transmit clock 3 EXEN2 R,W Timer 2 External Enable. When EXEN2 = 1, capture or reload results when negative edge on pin T2X occurs. EXEN2 = 0 causes Timer 2 to ignore events at pin T2X. 2 TR2 R,W Timer 2 run control. 1 = Timer/Counter 2 is on, 0 = Timer Counter 2 is off. 1 C/T2 R,W Counter or Timer function select. When C/T2 = 0, function is timer, clocked by internal clock. When C/T2 = 1, function is counter, clocked by signal sampled on external pin, T2. 0 CP/RL2 R,W Capture/Reload. When CP/RL2 = 1, capture occurs on negative transition at pin T2X if EXEN2 = 1. When CP/RL2 = 0, auto-reload occurs when Timer 2 overflows, or on negative transition at pin T2X when EXEN2=1. When RCLK = 1 or TCLK = 1, CP/RL2 is ignored, and Timer 2 is forced to autoreload upon Timer 2 overflowuPSD33xx 76/231 Table 42. Timer/Counter 2 Operating Modes Note: ↓ = falling edge Mode Bits in T2CON SFR Pin T2X Remarks Input Clock RCLK or TCLK CP/ RL2 TR2 EXEN2 Timer, Internal Counter, External (Pin T2, P1.0) 16-bit Autoreload 001 0 x reload [RCAP2H, RCAP2L] to [TH2, TL2] upon overflow (up counting) fOSC/12 MAX fOSC/24 001 1 ↓ reload [RCAP2H, RCAP2L] to [TH2, TL2] at falling edge on pin T2X 16-bit Capture 0 1 1 0 x 16-bit Timer/Counter (up counting) fOSC/12 MAX fOSC/24 011 1 ↓ Capture [TH2, TL2] and store to [RCAP2H, RCAP2L] at falling edge on pin T2X Baud Rate Generator 1 x 1 0 x No overflow interrupt request (TF2) fOSC/2 – 1x1 1 ↓ Extra Interrupt on pin T2X, sets TF2 Off x x 0 x x Timer 2 stops – –77/231 uPSD33xx Baud Rate Generator Mode. The RCLK and/or TCLK Bits in the SFR T2CON allow the transmit and receive baud rates on serial port UART0 to be derived from either Timer 1 or Timer 2. Figure 27., page 80 illustrates Baud Rate Generator Mode. When TCLK = 0, Timer 1 is used as UART0’s transmit baud generator. When TCLK = 1, Timer 2 will be the transmit baud generator. RCLK has the same effect for UART0’s receive baud rate. With these two bits, UART0 can have different receive and transmit baud rates - one generated by Timer 1, the other by Timer 2. Note: Bits RCLK1 and TCLK1 in the SFR named PCON (see PCON: Power Control Register (SFR 87h, reset value 00h), page 50) have identical functions as RCLK and TCLK but they apply to UART1 instead. For simplicity in the following discussions about baud rate generation, no suffix will be used when referring to SFR registers and bits related to UART0 or UART1, since each UART interface has identical operation. Example, TCLK or TCLK1 will be referred to as just TCLK. The Baud Rate Generator Mode is similar to the Auto-reload Mode, in that a roll over in TH2 causes the Timer 2 registers, TH2 and TL2, to be reloaded with the 16-bit value in Registers RCAP2H and RCAP2L, which are preset with firmware. The baud rates in UART Modes 1 and 3 are determined by Timer 2’s overflow rate as follows: UART Mode 1,3 Baud Rate = Timer 2 Overflow Rate / 16 The timer can be configured for either “timer” or “counter” operation. In the most typical applications, it is configured for “timer” operation (C/T2 = 0). “Timer” operation is a little different for Timer 2 when it's being used as a baud rate generator. In this case, the baud rate is given by the formula: UART Mode 1,3 Baud Rate = fOSC/(32 x [65536 – [RCAP2H, RCAP2L])) where [RCAP2H, RCAP2L] is the content of the SFRs RCAP2H and RCAP2L taken as a 16-bit unsigned integer. A roll-over in TH2 does not set TF2, and will not generate an interrupt. Therefore, the Timer Interrupt does not have to be disabled when Timer 2 is in the Baud Rate Generator Mode. If EXEN2 is set, a 1-to-0 transition on pin T2X will set the Timer 2 interrupt flag EXF2, but will not cause a reload from RCAP2H and RCAP2L to TH2 and TL2. Thus when Timer 2 is in use as a baud rate generator, the pin T2X can be used as an extra external interrupt, if desired. When Timer 2 is running (TR2 = 1) in a “timer” function in the Baud Rate Generator Mode, firmware should not read or write TH2 or TL2. Under these conditions the results of a read or write may not be accurate. However, SFRs RCAP2H and RCAP2L may be read, but should not be written, because a write might overlap a reload and cause write and/or reload errors. Timer 2 should be turned off (clear TR2) before accessing Timer 2 or Registers RCAP2H and RCAP2L, in this case. Table 43., page 78 shows commonly used baud rates and how they can be obtained from Timer 2, with T2CON = 34h.uPSD33xx 78/231 Table 43. Commonly Used Baud Rates Generated from Timer2 (T2CON = 34h) fOSC MHz Desired Baud Rate Timer 2 SFRs Resulting Baud Rate Baud Rate Deviation RCAP2H (hex) RCAP2L(hex) 40.0 115200 FF F5 113636 -1.36% 40.0 57600 FF EA 56818 -1.36% 40.0 28800 FF D5 29070 0.94% 40.0 19200 FF BF 19231 0.16% 40.0 9600 FF 7E 9615 0.16% 36.864 115200 FF F6 115200 0 36.864 57600 FF EC 57600 0 36.864 28800 FF D8 28800 0 36.864 19200 FF C4 19200 0 36.864 9600 FF 88 9600 0 36.0 28800 FF D9 28846 0.16% 36.0 19200 FF C5 19067 -0.69% 36.0 9600 FF 8B 9615 0.16% 24.0 57600 FF F3 57692 0.16% 24.0 28800 FF E6 28846 0.16% 24.0 19200 FF D9 19231 0.16% 24.0 9600 FF B2 9615 0.16% 12.0 28800 FF F3 28846 0.16% 12.0 9600 FF D9 9615 0.16% 11.0592 115200 FF FD 115200 0 11.0592 57600 FF FA 57600 0 11.0592 28800 FF F4 28800 0 11.0592 19200 FF EE 19200 0 11.0592 9600 FF DC 9600 0 3.6864 115200 FF FF 115200 0 3.6864 57600 FF FE 57600 0 3.6864 28800 FF FC 28800 0 3.6864 19200 FF FA 19200 0 3.6864 9600 FF F4 9600 0 1.8432 19200 FF FD 19200 0 1.8432 9600 FF FA 9600 079/231 uPSD33xx Figure 25. Timer 2 in Capture Mode Figure 26. Timer 2 in Auto-Reload Mode AI06625 f OSC TF2 Capture TR2 T2 pin Control TL2 (8 bits) TH2 (8 bits) C/T2 = 0 C/T2 = 1 ÷ 12 EXP2 Control EXEN2 RCAP2L RCAP2H T2X pin Timer 2 Interrupt Transition Detector AI06626 f OSC TF2 Reload TR2 T2 pin Control TL2 (8 bits) TH2 (8 bits) C/T2 = 0 C/T2 = 1 ÷ 12 EXP2 Control EXEN2 RCAP2L RCAP2H T2X pin Timer 2 Interrupt Transition DetectoruPSD33xx 80/231 Figure 27. Timer 2 in Baud Rate Generator Mode AI09605 f OSC Reload TR2 T2 pin Control Note: Oscillator frequency is divided by 2, not 12 like in other timer modes. Note: Availability of additional external interrupt. TL2 (8 bits) TH2 (8 bits) C/T2 = 0 C/T2 = 1 ÷ 12 ÷ 2 ÷ 16 ÷ 16 EXF2 Control EXEN2 RCAP2L RCAP2H T2X pin Timer 2 Interrupt TX CLK RX CLK Timer 1 Overflow SMOD RCLK '1' '0' '0' '1' '1' '0' TCLK Transition Detector81/231 uPSD33xx SERIAL UART INTERFACES uPSD33xx devices provide two standard 8032 UART serial ports. – The first port, UART0, is connected to pins RxD0 (P3.0) and TxD0 (P3.1) – The second port, UART1 is connected to pins RxD1 (P1.2) and TxD1 (P1.3). UART1 can optionally be routed to pins P4.2 and P4.3 as described in Alternate Functions, page 59. The operation of the two serial ports are the same and are controlled by two SFRs: ■ SCON0 (Table 45., page 82) for UART0 ■ SCON1 (Table 46., page 83) for UART1 Each UART has its own data buffer accessed through an SFR listed below: ■ SBUF0 for UART0, address 99h ■ SBUF1 for UART1, address D9h When writing SBU0 or SBUF1, the data automatically loads into the associated UART transmit data register. When reading this SFR, data comes from a different physical register, which is the receive register of the associated UART. Note: For simplicity in the remaining UART discussions, the suffix “0” or “1” will be dropped when referring to SFR registers and bits related to UART0 or UART1, since each UART interface has identical operation. Example, SBUF0 and SBUF1 will be referred to as just SBUF. Each UART serial port can be full-duplex, meaning it can transmit and receive simultaneously. Each UART is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the SBUF Register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost. UART Operation Modes Each UART can operate in one of four modes, one mode is synchronous, and the others are asynchronous as shown in Table 44. Mode 0. Mode 0 provides asynchronous, half-duplex operation. Serial data is both transmitted, and received on the RxD pin. The TxD pin outputs a shift clock for both transmit and receive directions, thus the MCU must be the master. Eight bits are transmitted/received LSB first. The baud rate is fixed at 1/12 of fOSC. Mode 1. Mode 1 provides standard asynchronous, full-duplex communication using a total of 10 bits per data byte. Data is transmitted through TxD and received through RxD with: a Start Bit (logic '0'), eight data bits (LSB first), and a Stop Bit (logic '1'). Upon receive, the eight data bits go into the SFR SBUF, and the Stop Bit goes into bit RB8 of the SFR SCON. The baud rate is variable and derived from overflows of Timer 1 or Timer 2. Mode 2. Mode 2 provides asynchronous, full-duplex communication using a total of 11 bits per data byte. Data is transmitted through TxD and received through RxD with: a Start Bit (logic '0'); eight data bits (LSB first); a programmable 9th data bit; and a Stop Bit (logic '1'). Upon Transmit, the 9th data bit (from bit TB8 in SCON) can be assigned the value of '0' or '1.' Or, for example, the Parity Bit (P, in the PSW) could be moved into TB8. Upon receive, the 9th data bit goes into RB8 in SCON, while the Stop Bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of fOSC. Mode 3. Mode 3 is the same as Mode 2 in all respects except the baud rate is variable like it is in Mode 1. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming Start Bit if REN = 1. Table 44. UART Operating Modes Mode Synchronization Bits of SFR, SCON Baud Clock Data Bits Start/Stop Bits See Figure SM0 SM1 0 Synchronous 0 0 fOSC/12 8 None Figure 28., page 86 1 Asynchronous 0 1 Timer 1 or Timer 2 Overflow 8 1 Start, 1 Stop Figure 30., page 88 2 Asynchronous 1 0 fOSC/32 or fOSC/64 9 1 Start, 1 Stop Figure 32., page 90 3 Asynchronous 1 1 Timer 1 or Timer 2 Overflow 9 1 Start, 1 Stop Figure 34., page 91uPSD33xx 82/231 Multiprocessor Communications. Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into bit RB8, then comes a stop bit. The port can be programmed such that when the stop bit is received, the UART interrupt will be activated only if bit RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multi-processor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that were not being addressed leave their SM2 bits set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1, SM2 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. Serial Port Control Registers The SFR SCON0 controls UART0, and SCON1 controls UART1, shown in Table 45 and Table 46. These registers contain not only the mode selection bits, but also the 9th data bit for transmit and receive (bits TB8 and RB8), and the UART Interrupt flags, TI and RI. Table 45. SCON0: Serial Port UART0 Control Register (SFR 98h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SM0 SM1 SM2 REN TB8 RB8 TI RI Details Bit Symbol R/W Definition 7 SM0 R,W Serial Mode Select, See Table 44., page 81. Important, notice bit order of SM0 and SM1. [SM0:SM1] = 00b, Mode 0 [SM0:SM1] = 01b, Mode 1 [SM0:SM1] = 10b, Mode 2 [SM0:SM1] = 11b, Mode 3 6 SM1 R,W 5 SM2 R,W Serial Multiprocessor Communication Enable. Mode 0: SM2 has no effect but should remain 0. Mode 1: If SM2 = 0 then stop bit ignored. SM2 =1 then RI active if stop bit = 1. Mode 2 and 3: Multiprocessor Comm Enable. If SM2=0, 9th bit is ignored. If SM2=1, RI active when 9th bit = 1. 4 REN R,W Receive Enable. If REN=0, UART reception disabled. If REN=1, reception is enabled 3 TB8 R,W TB8 is assigned to the 9th transmission bit in Mode 2 and 3. Not used in Mode 0 and 1. 2 RB8 R,W Mode 0: RB8 is not used. Mode 1: If SM2 = 0, the RB8 is the level of the received stop bit. Mode 2 and 3: RB8 is the 9th data bit that was received in Mode 2 and 3. 1 TI R,W Transmit Interrupt flag. Causes interrupt at end of 8th bit time when transmitting in Mode 0, or at beginning of stop bit transmission in other modes. Must clear flag with firmware. 0 RI R,W Receive Interrupt flag. Causes interrupt at end of 8th bit time when receiving in Mode 0, or halfway through stop bit reception in other modes (see SM2 for exception). Must clear this flag with firmware.83/231 uPSD33xx Table 46. SCON1: Serial Port UART1 Control Register (SFR D8h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SM0 SM1 SM2 REN TB8 RB8 TI RI Details Bit Symbol R/W Definition 7 SM0 R,W Serial Mode Select, See Table 44., page 81. Important, notice bit order of SM0 and SM1. [SM0:SM1] = 00b, Mode 0 [SM0:SM1] = 01b, Mode 1 [SM0:SM1] = 10b, Mode 2 [SM0:SM1] = 11b, Mode 3 6 SM1 R,W 5 SM2 R,W Serial Multiprocessor Communication Enable. Mode 0: SM2 has no effect but should remain 0. Mode 1: If SM2 = 0 then stop bit ignored. SM2 =1 then RI active if stop bit = 1. Mode 2 and 3: Multiprocessor Comm Enable. If SM2=0, 9th bit is ignored. If SM2=1, RI active when 9th bit = 1. 4 REN R,W Receive Enable. If REN=0, UART reception disabled. If REN=1, reception is enabled 3 TB8 R,W TB8 is assigned to the 9th transmission bit in Mode 2 and 3. Not used in Mode 0 and 1. 2 RB8 R,W Mode 0: RB8 is not used. Mode 1: If SM2 = 0, the RB8 is the level of the received stop bit. Mode 2 and 3: RB8 is the 9th data bit that was received in Mode 2 and 3. 1 TI R,W Transmit Interrupt flag. Causes interrupt at end of 8th bit time when transmitting in Mode 0, or at beginning of stop bit transmission in other modes. Must clear flag with firmware. 0 RI R,W Receive Interrupt flag. Causes interrupt at end of 8th bit time when receiving in Mode 0, or halfway through stop bit reception in other modes (see SM2 for exception). Must clear this flag with firmware.uPSD33xx 84/231 UART Baud Rates The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = fOSC / 12 The baud rate in Mode 2 depends on the value of the bit SMOD in the SFR named PCON. If SMOD = 0 (default value), the baud rate is 1/64 the oscillator frequency, fOSC. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. Mode 2 Baud Rate = (2SMOD / 64) x fOSC Baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate. Using Timer 1 to Generate Baud Rates. When Timer 1 is used as the baud rate generator (bits RCLK = 0, TCLK = 0), the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Mode 1,3 Baud Rate = (2SMOD / 32) x (Timer 1 overflow rate) The Timer 1 Interrupt should be disabled in this application. The Timer itself can be configured for either “timer” or “counter” operation, and in any of its 3 running modes. In the most typical applications, it is configured for “timer” operation, in the Auto-reload Mode (high nibble of the SFR TMOD = 0010B). In that case the baud rate is given by the formula: Mode 1,3 Baud Rate = (2SMOD / 32) x (fOSC / (12 x [256 – (TH1)])) Table 47 lists various commonly used baud rates and how they can be obtained from Timer 1. Using Timer/Counter 2 to Generate Baud Rates. See Baud Rate Generator Mode, page 77. Table 47. Commonly Used Baud Rates Generated from Timer 1 UART Mode fOSC MHz Desired Baud Rate Resultant Baud Rate Baud Rate Deviation SMOD bit in PCON Timer 1 C/T Bit in TMOD Timer Mode in TMOD TH1 Reload value (hex) Mode 0 Max 40.0 3.33MHz 3.33MHz 0 X X X X Mode 2 Max 40.0 1250 k 1250 k 0 1 X X X Mode 2 Max 40.0 625 k 625 k 0 0 X X X Modes 1 or 3 40.0 19200 18939 -1.36% 1 0 2 F5 Modes 1 or 3 40.0 9600 9470 -1.36% 1 0 2 EA Modes 1 or 3 36.0 19200 18570 -2.34% 1 0 2 F6 Modes 1 or 3 33.333 57600 57870 0.47% 1 0 2 FD Modes 1 or 3 33.333 28800 28934 0.47% 1 0 2 FA Modes 1 or 3 33.333 19200 19290 0.47% 1 0 2 F7 Modes 1 or 3 33.333 9600 9645 0.47% 1 0 2 EE Modes 1 or 3 24.0 9600 9615 0.16% 1 0 2 F3 Modes 1 or 3 12.0 4800 4808 0.16% 1 0 2 F3 Modes 1 or 3 11.0592 57600 57600 0 1 0 2 FF Modes 1 or 3 11.0592 28800 28800 0 1 0 2 FE Modes 1 or 3 11.0592 19200 19200 0 1 0 2 FD Modes 1 or 3 11.0592 9600 9600 0 1 0 2 FA Modes 1 or 3 3.6864 19200 19200 0 1 0 2 FF Modes 1 or 3 3.6864 9600 9600 0 1 0 2 FE Modes 1 or 3 1.8432 9600 9600 0 1 0 2 FF Modes 1 or 3 1.8432 4800 4800 0 1 0 2 FE85/231 uPSD33xx More About UART Mode 0 Refer to the block diagram in Figure 28., page 86, and timing diagram in Figure 29., page 86. Transmission is initiated by any instruction which writes to the SFR named SBUF. At the end of a write operation to SBUF, a 1 is loaded into the 9th position of the transmit shift register and tells the TX Control unit to begin a transmission. Transmission begins on the following MCU machine cycle, when the “SEND” signal is active in Figure 29. SEND enables the output of the shift register to the alternate function on the port containing pin RxD, and also enables the SHIFT CLOCK signal to the alternate function on the port containing the pin, TxD. At the end of each SHIFT CLOCK in which SEND is active, the contents of the transmit shift register are shifted to the right one position. As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the '1' that was initially loaded into the 9th position, is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift, then deactivate SEND, and then set the interrupt flag TI. Both of these actions occur at S1P1. Reception is initiated by the condition REN = 1 and RI = 0. At the end of the next MCU machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enables the SHIFT CLOCK signal to the alternate function on the port containing the pin, TxD. Each pulse of SHIFT CLOCK moves the contents of the receive shift register one position to the left while RECEIVE is active. The value that comes in from the right is the value that was sampled at the RxD pin. As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the left-most position in the shift register, it flags the RX Control unit to do one last shift, and then it loads SBUF. After this, RECEIVE is cleared, and the receive interrupt flag RI is set.uPSD33xx 86/231 Figure 28. UART Mode 0, Block Diagram Figure 29. UART Mode 0, Timing Diagram AI06824 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Shift Clock Serial Port Interrupt f OSC/12 REN R1 Rx Clock Start Tx Clock Start Shift Shift Send Receive T R CL D S Q 7 6 5 4 3 2 1 0 RxD P3.0 Alt Input Function RxD Pin TxD Pin AI06825 Write to SBUF Send Shift RxD (Data Out) TxD (Shift Clock) TI Write to SCON RI Receive Shift RxD (Data In) TxD (Shift Clock) Clear RI Receive Transmit D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D787/231 uPSD33xx More About UART Mode 1 Refer to the block diagram in Figure 30., page 88, and timing diagram in Figure 31., page 88. Transmission is initiated by any instruction which writes to SBUF. At the end of a write operation to SBUF, a '1' is loaded into the 9th position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually starts at the end of the MCU the machine cycle following the next rollover in the divide-by-16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the writing of SBUF. Transmission begins with activation of SEND which puts the start bit at pin TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to pin TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivates SEND, and sets the interrupt flag, TI. This occurs at the 10th divide-by-16 rollover after a write to SBUF. Reception is initiated by a detected 1-to-0 transition at the pin RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not '0,' the receive circuits are reset and the unit goes back to looking for another '1'-to- '0' transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the reset of the rest of the frame will proceed. As data bits come in from the right, '1s' shift out to the left. When the start bit arrives at the left-most position in the shift register (which in mode 1 is a 9-bit register), it flags the RX Control unit to do one last shift, load SBUF and RB8, and set the receive interrupt flag RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. RI = 0, and 2. Either SM2 = 0, or the received stop bit = 1. If either of these two conditions are not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a '1'-to-'0' transition on pin RxD.uPSD33xx 88/231 Figure 30. UART Mode 1, Block Diagram Figure 31. UART Mode 1, Timing Diagram AI06826 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Serial Port Interrupt Rx Clock Start Tx Clock Start Shift Shift Send Load SBUF TI RI CL D S Q 1FFh TxD Pin Data Rx Detector RxD Pin 1-to-0 Transition Detector ÷16 Sample ÷16 ÷2 TB8 Timer1 Overflow Timer2 Overflow 0 0 1 1 0 1 TCLK RCLK SMOD AI06843 Write to SBUF Data Shift TxD TI Rx Clock RxD Bit Detector Sample Times Shift RI Receive Transmit D0 D1 D2 D3 D4 D5 D6 D7 Send Tx Clock Start Bit Stop Bit D0 D1 D2 D3 D4 D5 D6 D7 Start Bit Stop Bit89/231 uPSD33xx More About UART Modes 2 and 3 For Mode 2, refer to the block diagram in Figure 32., page 90, and timing diagram in Figure 33., page 90. For Mode 3, refer to the block diagram in Figure 34., page 91, and timing diagram in Figure 35., page 91. Keep in mind that the baud rate is programmable to either 1/32 or 1/64 of fOSC in Mode 2, but Mode 3 uses a variable baud rate generated from Timer 1 or Timer 2 rollovers. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction which writes to SBUF. At the end of a write operation to SBUF, the TB8 Bit is loaded into the 9th position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually starts at the end of the MCU the machine cycle following the next rollover in the divideby-16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the writing of SBUF. Transmission begins with activation of SEND which puts the start bit at pin TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to pin TxD. The first shift pulse occurs one bit time after that. The first shift clocks a '1' (the stop bit) into the 9th bit position of the shift register. There-after, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When bit TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND, and set the interrupt flag, TI. This occurs at the 11th divide-by 16 rollover after writing to SBUF. Reception is initiated by a detected 1-to-0 transition at pin RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not '0,' the receive circuits are reset and the unit goes back to looking for another '1'-to- '0' transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, '1s' shift out to the left. When the start bit arrives at the left-most position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control unit to do one last shift, load SBUF and RB8, and set the interrupt flag RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. RI = 0, and 2. Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a '1'-to-'0' transition on pin RxD.uPSD33xx 90/231 Figure 32. UART Mode 2, Block Diagram Figure 33. UART Mode 2, Timing Diagram AI06844 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Serial Port Interrupt Rx Clock Start Tx Clock Start Shift Shift Send Load SBUF TI RI CL D S Q 1FFh TxD Pin Data Rx Detector RxD Pin 1-to-0 Transition Detector ÷16 Sample ÷16 ÷2 TB8 f OSC/32 0 1 SMOD AI06845 Write to SBUF Data Shift TxD TI Rx Clock RxD Bit Detector Sample Times Shift RI Receive Transmit D0 D1 D2 D3 D4 D5 D6 D7 Send Tx Clock Start Bit TB8 Stop Bit D0 D1 D2 D3 D4 D5 D6 D7 Start Bit RB8 Stop Bit Stop Bit Generator91/231 uPSD33xx Figure 34. UART Mode 3, Block Diagram Figure 35. UART Mode 3, Timing Diagram AI06846 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Serial Port Interrupt Rx Clock Start Tx Clock Start Shift Shift Send Load SBUF TI RI CL D S Q 1FFh TxD Pin Data Rx Detector RxD Pin 1-to-0 Transition Detector ÷16 Sample ÷16 ÷2 TB8 Timer1 Overflow Timer2 Overflow 0 0 1 1 0 1 TCLK RCLK SMOD AI06847 Write to SBUF Data Shift TxD TI Rx Clock RxD Bit Detector Sample Times Shift RI Receive Transmit D0 D1 D2 D3 D4 D5 D6 D7 Send Tx Clock Start Bit TB8 Stop Bit D0 D1 D2 D3 D4 D5 D6 D7 Start Bit RB8 Stop Bit Stop Bit GeneratoruPSD33xx 92/231 IrDA INTERFACE uPSD33xx devices provide an internal IrDA interface that will allow the connection of the UART1 serial interface directly to an external infrared transceiver device. The IrDA interface does this by automatically shortening the pulses transmitted on UART1’s TxD1 pin, and stretching the incoming pulses received on the RxD1 pin. Reference Figures 36 and 37. When the IrDA interface is enabled, the output signal from UART1’s transmitter logic on pin TxD1 is compliant with the IrDA Physical Layer Link Specification v1.4 (www.irda.org) operating from 1.2k bps up to 115.2k bps. The pulses received on the RxD1 pin are stretched by the IrDA interface to be recognized by UART1’s receiver logic, also adhering to the IrDA specification up to 115.2k bps. Note: In Figure 37 a logic '0' in the serial data stream of a UART Frame corresponds to a logic high pulse in an IR Frame. A logic '1' in a UART Frame corresponds to no pulse in an IR Frame. Figure 36. IrDA Interface Figure 37. Pulse Shaping by the IrDA Interface UART1 IrDA Interface TxD RxD uPSD33XX IrDA Transceiver TxD1-IrDA RxD1-IrDA SIRClk AI07851 Start Bit 0101 11 1 00 0 Stop Bit UART Frame Data Bits Bit Time Pulse Width = 3/16 Bit Time Start Bit 0101 11 1 00 0 Stop Bit UART Frame IR Frame IR Frame Data Bits AI0962493/231 uPSD33xx The UART1 serial channel can operate in one of four different modes as shown in Table 44., page 81 in the section, SERIAL UART INTERFACES, page 81. However, when UART1 is used for IrDA communication, UART1 must operate in Mode 1 only, to be compatible with IrDA protocol up to 115.2k bps. The IrDA interface will support baud rates generated from Timer 1 or Timer 2, just like standard UART serial communication, but with one restriction. The transmit baud rate and receive baud rate must be the same (cannot be different rates as is allowed by standard UART communications). The IrDA Interface is disabled after a reset and is enabled by setting the IRDAEN Bit in the SFR named IRDACON (Table 48., page 93). When IrDA is disabled, the UART1's RxD and TxD signals will bypass the internal IrDA logic and instead they are routed directly to the pins RxD1 and TxD1 respectively. When IrDA is enabled, the IrDA pulse shaping logic is active and resides between UART1 and the pins RxD1 and TxD1 as shown in Figure 36., page 92. Table 48. IRDACON Register Bit Definition (SFR CEh, Reset Value 0Fh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – IRDAEN PULSE CDIV4 CDIV3 CDIV2 CDIV1 CDIV0 Details Bit Symbol R/W Definition 7 – – Reserved 6 IRDAEN RW IrDA Enable 0 = IrDA Interface is disabled 1 = IrDA is enabled, UART1 outputs are disconnected from Port 1 (or Port 4) 5 PULSE RW IrDA Pulse Modulation Select 0 = 1.627µs 1 = 3/16 bit time pulses 4-0 CDIV[4:0] RW Specify Clock Divider (see Table 49., page 94)uPSD33xx 94/231 Pulse Width Selection The IrDA interface has two ways to modulate the standard UART1 serial stream: 1. An IrDA data pulse will have a constant pulse width for any bit time, regardless of the selected baud rate. 2. An IrDA data pulse will have a pulse width that is proportional to the the bit time of the selected baud rate. In this case, an IrDA data pulse width is 3/16 of its bit time, as shown in Figure 37., page 92. The PULSE bit in the SFR named IRDACON determines which method above will be used. According to the IrDA physical layer specification, for all baud rates at 115.2k bps and below, the minimum data pulse width is 1.41µs. For a baud rate of 115.2k bps, the maximum pulse width 2.23µs. If a constant pulse width is to be used for all baud rates (PULSE bit = 0), the ideal general pulse width is 1.63µs, derived from the bit time of the fastest baud rate (8.68µs bit time for 115.2k bps rate), multiplied by the proportion, 3/16. To produce this fixed data pulse width when the PULSE bit = 0, a prescaler is needed to generate an internal reference clock, SIRClk, shown in Figure 36., page 92. SIRClk is derived by dividing the oscillator clock frequency, fOSC, using the five bits CDIV[4:0] in the SFR named IRDACON. A divisor must be chosen to produce a frequency for SIRClk that lies between 1.34 MHz and 2.13 MHz, but it is best to choose a divisor value that produces SIRClk frequency as close to 1.83MHz as possible, because SIRClk at 1.83MHz will produce an fixed IrDA data pulse width of 1.63µs. Table 49 provides recommended values for CDIV[4:0] based on several different values of fOSC. For reference, SIRClk of 2.13MHz will generate a fixed IrDA data pulse width of 1.41µs, and SIRClk of 1.34MHz will generate a fixed data pulse width of 2.23µs. Table 49. Recommended CDIV[4:0] Values to Generate SIRClk (default CDIV[4:0] = 0Fh, 15 decimal) Note: 1. When PULSE bit = 0 (fixed data pulse width), this is minimum recommended fOSC because CDIV[4:0] must be 4 or greater. fOSC (MHz) Value in CDIV[4:0] Resulting fSIRCLK (MHz) 40.00 16h, 22 decimal 1.82 36.864, or 36.00 14h, 20 decimal 1.84, or 1.80 24.00 0Dh, 13 decimal 1.84 11.059, or 12.00 06h, 6 decimal 1.84, or 2.00 7.3728(1) 04h, 4 decimal 1.8495/231 uPSD33xx I 2C INTERFACE uPSD33xx devices support one serial I2C interface. This is a two-wire communication channel, having a bi-directional data signal (SDA, pin P3.6) and a clock signal (SCL, pin P3.7) based on opendrain line drivers, requiring external pull-up resistors, RP, each with a typical value of 4.7kΩ (see Figure 38). I 2C Interface Main Features Byte-wide data is transferred, MSB first, between a Master device and a Slave device on two wires. More than one bus Master is allowed, but only one Master may control the bus at any given time. Data is not lost when another Master requests the use of a busy bus because I2C supports collision detection and arbitration. The bus Master initiates all data movement and generates the clock that permits the transfer. Once a transfer is initiated by the Master, any device addressed is considered a Slave. Automatic clock synchronization allows I2C devices with different bit rates to communicate on the same physical bus. A single device can play the role of Master or Slave, or a single device can be a Slave only. Each Slave device on the bus has a unique address, and a general broadcast address is also available. A Master or Slave device has the ability to suspend data transfers if the device needs more time to transmit or receive data. This I2C interface has the following features: – Serial I/O Engine (SIOE): serial/parallel conversion; bus arbitration; clock generation and synchronization; and handshaking are all performed in hardware – Interrupt or Polled operation – Multi-master capability – 7-bit Addressing – Supports standard speed I2C (SCL up to 100kHz), fast mode I2C (101KHz to 400kHz), and high-speed mode I2C (401KHz to 833kHz) Figure 38. Typical I2C Bus Configuration Note: 1. For 3.3V system, connect RP to 3.3V VCC. For 5.0V system, connect RP to 5.0V VDD. I 2C BUS SDA SCL RP RP VCC or VDD(1) Device with I2C Interface Device with I2C Interface SDA/P3.6 SCL/P3.7 uPSD33XX(V) Device with I2C Interface AI09623uPSD33xx 96/231 Communication Flow I 2C data flow control is based on the fact that all I 2C compatible devices will drive the bus lines with open-drain (or open-collector) line drivers pulled up with external resistors, creating a wired-AND situation. This means that either bus line (SDA or SCL) will be at a logic '1' level only when no I2C device is actively driving the line to logic '0.' The logic for handshaking, arbitration, synchronization, and collision detection is implemented by each I2C device having: 1. The ability to hold a line low against the will of the other devices who are trying to assert the line high. 2. The ability of a device to detect that another device is driving the line low against its will. Assert high means the driver releases the line and external pull-ups passively raise the signal to logic '1.' Holding low means the open-drain driver is actively pulling the signal to ground for a logic '0.' For example, if a Slave device cannot transmit or receive a byte because it is distracted by and interrupt or it has to wait for some process to complete, it can hold the SCL clock line low. Even though the Master device is generating the SCL clock, the Master will sense that the Slave is holding the SCL line low against the will of the Master, indicating that the Master must wait until the Slave releases SCL before proceeding with the transfer. Another example is when two Master devices try to put information on the bus simultaneously, the first one to release the SDA data line looses arbitration while the winner continues to hold SDA low. Two types of data transfers are possible with I2C depending on the R/W bit, see Figure 39., page 97. 1. Data transfer from Master Transmitter to Slave Receiver (R/W = 0). In this case, the Master generates a START condition on the bus and it generates a clock signal on the SCL line. Then the Master transmits the first byte on the SDA line containing the 7-bit Slave address plus the R/W bit. The Slave who owns that address will respond with an acknowledge bit on SDA, and all other Slave devices will not respond. Next, the Master will transmit a data byte (or bytes) that the addressed Slave must receive. The Slave will return an acknowledge bit after each data byte it successfully receives. After the final byte is transmitted by the Master, the Master will generate a STOP condition on the bus, or it will generate a RESTART conditon and begin the next transfer. There is no limit to the number of bytes that can be transmitted during a transfer session. 2. Data transfer from Slave Transmitter to Master Receiver (R/W = 1). In this case, the Master generates a START condition on the bus and it generates a clock signal on the SCL line. Then the Master transmits the first byte on the SDA line containing the 7-bit Slave address plus the R/W bit. The Slave who owns that address will respond with an acknowledge bit on SDA, and all other Slave devices will not respond. Next, the addressed Slave will transmit a data byte (or bytes) to the Master. The Master will return an acknowledge bit after each data byte it successfully receives, unless it is the last byte the Master desires. If so, the Master will not acknowledge the last byte and from this, the Slave knows to stop transmitting data bytes to the Master. The Master will then generate a STOP condition on the bus, or it will generate a RE-START conditon and begin the next transfer. There is no limit to the number of bytes that can be transmitted during a transfer session. A few things to know related to these transfers: – Either the Master or Slave device can hold the SCL clock line low to indicate it needs more time to handle a byte transfer. An indefinite holding period is possible. – A START condition is generated by a Master and recognized by a Slave when SDA has a 1- to-0 transition while SCL is high (Figure 39., page 97). – A STOP condition is generated by a Master and recognized by a Slave when SDA has a 0- to1 transition while SCL is high (Figure 39., page 97). – A RE-START (repeated START) condition generated by a Master can have the same function as a STOP condition when starting another data transfer immediately following the previous data transfer (Figure 39., page 97). – When transferring data, the logic level on the SDA line must remain stable while SCL is high, and SDA can change only while SCL is low. However, when not transferring data, SDA may change state while SCL is high, which creates the START and STOP bus conditions.97/231 uPSD33xx – An Acknowlegde bit is generated from a Master or a Slave by driving SDA low during the “ninth” bit time, just following each 8-bit byte that is transfered on the bus (Figure 39., page 97). A Non-Acknowledge occurs when SDA is asserted high during the ninth bit time. All byte transfers on the I2C bus include a 9th bit time reserved for an Acknowlege (ACK) or Non-Acknowledge (NACK). – An additional Master device that desires to control the bus should wait until the bus is not busy before generating a START condition so that a possible Slave operation is not interrupted. – If two Master devices both try to generate a START condition simultaneously, the Master who looses arbitration will switch immediately to Slave mode so it can recoginize it’s own Slave address should it appear on the bus. Figure 39. Data Transfer on an I2C Bus MSB 7-bit Slave Address READ/WRITE Indicator Acknowledge bits from receiver Start Condition Clock can be held low to stall transfer. Repeated if more data bytes are transferred. Repeated Start Condition Stop Condition 12 789 3-6 1 2 9 3-8 ACK MSB ACK NACK R/W AI09625uPSD33xx 98/231 Operating Modes The I2C interface supports four operating modes: ■ Master-Transmitter ■ Master-Receiver ■ Slave-Transmitter ■ Slave-Receiver The interface may operate as either a Master or a Slave within a given application, controlled by firmware writing to SFRs. By default after a reset, the I2C interface is in Master Receiver mode, and the SDA/P3.6 and SCL/ P3.7 pins default to GPIO input mode, high impedance, so there is no I2C bus interference. Before using the I2C interface, it must be initialized by firmware, and the pins must be configured. This is discussed in I 2C Operating Sequences, page 108. Bus Arbitration A Master device always samples the I2C bus to ensure a bus line is high whenever that Master is asserting a logic 1. If the line is low at that time, the Master recognizes another device is overriding it’s own transmission. A Master may start a transfer only if the I2C bus is not busy. However, it’s possible that two or more Masters may generate a START condition simultaneously. In this case, arbitration takes place on the SDA line each time SCL is high. The Master that first senses that its bus sample does not correspond to what it is driving (SDA line is low while it’s asserting a high) will immediately change from Master-Transmitter to Slave-Receiver mode. The arbitration process can carry on for many bit times if both Masters are addressing the same Slave device, and will continue into the data bits if both Masters are trying to be Master-Transmitter. It is also possible for arbitration to carry on into the acknowledge bits if both Masters are trying to be Master-Receiver. Because address and data information on the bus is determined by the winning Master, no information is lost during the arbitration process. Clock Synchronization Clock synchronization is used to synchronize arbitrating Masters, or used as a handshake by a devices to slow down the data transfer. Clock Sync During Arbitration. During bus arbitration between competing Masters, Master_X, with the longest low period on SCL, will force Master_Y to wait until Master_X finishes its low period before Master_Y proceeds to assert its high period on SCL. At this point, both Masters begin asserting their high period on SCL simultaneously, and the Master with the shortest high period will be the first to drive SCL for the next low period. In this scheme, the Master with the longest low SCL period paces low times, and the Master with the shortest high SCL period paces the high times, making synchronized arbitration possible. Clock Sync During Handshaking. This allows receivers in different devices to handle various transfer rates, either at the byte-level, or bit-level. At the byte-level, a device may pause the transfer between bytes by holding SCL low to have time to store the latest received byte or fetch the next byte to transmit. At the bit-level, a Slave device may extend the low period of SCL by holding it low. Thus the speed of any Master device will adapt to the internal operation of the Slave. General Call Address A General Call (GC) occurs when a Master-Transmitter initiates a transfer containing a Slave address of 0000000b, and the R/W bit is logic 0. All Slave devices capable of responding to this broadcast message will acknowledge the GC simultaneously and then behave as a Slave-Receiver. The next byte transmitted by the Master will be accepted and acknowledged by all Slaves capable of handling the special data bytes. A Slave that cannot handle one of these data bytes must ignore it by not acknowledging it. The I2C specification lists the possible meanings of the special bytes that follow the first GC address byte, and the actions to be taken by the Slave device(s) upon receiving them. A common use of the GC by a Master is to dynamically assign device addresses to Slave devices on the bus capable of a programmable device address. The uPSD33xx can generate a GC as a MasterTransmitter, and it can receive a GC as a Slave. When receiving a GC address (00h), an interrupt will be generated so firmware may respond to the special GC data bytes if desired.99/231 uPSD33xx Serial I/O Engine (SIOE) At the heart of the I2C interface is the hardware SIOE, shown in Figure 40. The SIOE automatically handles low-level I2C bus protocol (data shifting, handshaking, arbitration, clock generation and synchronization) and it is controlled and monitored by five SFRs. The five SFRs shown in Figure 40 are: ■ S1CON - Interface Control (Table 50., page 100) ■ S1STA - Interface Status (Table 52., page 103) ■ S1DAT - Data Shift Register (Table 53., page 104) ■ S1ADR - Device Address (Table 54., page 104) ■ S1SETUP - Sampling Rate (Table 55., page 105) Figure 40. I2C Interface SIOE Block Diagram OpenDrain Output Input OpenDrain Output Input Comparator S1SETUP - Sample Rate Control (START Condition) S1STA - Interface Status S1CON - Interface Control ACK Bit SCL / P3.7 Timing and Control Clock Generation Arbitration and Sync Periph Clock (fOSC) SDA / P3.6 8032 MCU Bus INTR to 8032 S1DAT - Shift Register Serial DATA IN Serial DATA OUT Shift Direction 8 8 8 8 8 7 7 b7 b0 S1ADR - Device Address b7 b0 AI09626uPSD33xx 100/231 I 2C Interface Control Register (S1CON) Table 50. Serial Control Register S1CON (SFR DCh, Reset Value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CR2 ENI1 STA STO ADDR AA CR[1:0] Details Bit Symbol R/W Function 7 CR2 R,W This bit, along with bits CR1 and CR0, determine the SCL clock frequency (fSCL) when SIOE is in Master mode. These bits create a clock divisor for fOSC. See Table 51. 6 ENI1 R,W I 2C Interface Enable 0 = SIOE disabled, 1 = SIOE enabled. When disabled, both SDA and SCL signals are in high impedance state. 5 STA R,W START flag. When set, Master mode is entered and SIOE generates a START condition only if the I2C bus is not busy. When a START condition is detected on the bus, the STA flag is cleared by hardware. When the STA bit is set during an interrupt service, the START condition will be generated after the interrupt service. 4 STO R,W STOP flag When STO is set in Master mode, the SIOE generates a STOP condition. When a STOP condition is detected, the STO flag is cleared by hardware. When the STO bit is set during an interrupt service, the STOP condition will be generated after the interrupt service. 3 ADDR R,W This bit is set when an address byte received in Slave mode matches the device address programmed into the S1ADR register. The ADDR bit must be cleared with firmware. 2 AA R,W Assert Acknowledge enable If AA = 1, an acknowledge signal (low on SDA) is automatically returned during the acknowledge bit-time on the SCL line when any of the following three events occur: 1. SIOE in Slave mode receives an address that matches contents of S1ADR register 2. A data byte has been received while SIOE is in Master Receiver mode 3. A data byte has been received while SIOE is a selected Slave Receiver When AA = 0, no acknowledge is returned (high on SDA during acknowledge bit-time). 1, 0 CR1, CR0 R,W These bits, along with bit CR2, determine the SCL clock frequency (fSCL) when SIOE is in Master mode. These bits create a clock divisor for fOSC. See Table 51 for values.101/231 uPSD33xx Table 51. Selection of the SCL Frequency in Master Mode based on fOSC Examples Note: 1. These values are beyond the bit rate supported by uPSD33xx. CR2 CR1 CR0 fOSC Divided by: Bit Rate (kHz) @ fOSC 12MHz fOSC 24MHz fOSC 36MHz fOSC 40MHz fOSC 0 0 0 32 375 750 X(1) X(1) 0 0 1 48 250 500 750 833 0 1 0 60 200 400 600 666 0 1 1 120 100 200 300 333 1 0 0 240 50 100 150 166 1 0 1 480 25 50 75 83 1 1 0 960 12.5 25 37.5 41 1 1 1 1920 6.25 12.5 18.75 20uPSD33xx 102/231 I 2C Interface Status Register (S1STA) The S1STA register provides status regarding immediate activity and the current state of operation on the I2C bus. All bits in this register are read-only except bit 5, INTR, which is the interrupt flag. Interrupt Conditions. If the I2C interrupt is enabled (EI2C = 1 in SFR named IEA, and EA =1 in SFR named IE), and the SIOE is initialized, then an interrupt is automatically generated when any one of the following five events occur: – When the SIOE receives an address that matches the contents of the SFR, S1ADR. Requirements: SIOE is in Slave Mode, and bit AA = 1 in the SFR S1CON. – When the SIOE receives General Call address. Requirments: SIOE is in Slave Mode, bit AA = 1 in the SFR S1CON – When a complete data byte has been received or transmitted by the SIOE while in Master mode. The interrupt will occur even if the Master looses arbitration. – When a complete data byte has been received or transmitted by the SIOE while in selected Slave mode. – A STOP condition on the bus has been recognized by the SIOE while in selected Slave mode. Selected Slave mode means the device address sent by the Master device at the beginning of the current data transfer matched the address stored in the S1ADR register. If the I2C interrupt is not enabled, the MCU may poll the INTR flag in S1STA.103/231 uPSD33xx Table 52. S1STA: I2C Interface Status Register (SFR DDh, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GC STOP INTR TX_MODE BBUSY BLOST ACK_RESP SLV Details Bit Symbol R/W Function 7 GC R General Call flag GC = 1 if the General Call address of 00h was received when SIOE is in Slave mode, and GC is cleared by a START or STOP condition on the bus. If the SIOE is in Master mode when GC = 1, the Bus Lost condition exists, and BLOST = 1. 6 STOP R STOP flag STOP = 1 while SIOE detects a STOP condition on the bus when in Master or Slave mode. 5 INTR R,W Interrupt flag INTR is set to 1 by any of the five I2C interrupt conditions listed above. INTR must be cleared by firmware. 4 TX_MODE R Transmission Mode flag TX_MODE = 1 whenever the SIOE is in Master-Transmitter or SlaveTransmitter mode. TX_MODE = 0 when SIOE is in any receiver mode. 3 BBUSY R Bus Busy flag BBUSY = 1 when the I2C bus is in use. BBUSY is set by the SIOE when a START condition exists on the bus and BBUSY is cleared by a STOP condition. 2 BLOST R Bus Lost flag BLOST is set when the SIOE is in Master mode and it looses the arbitration process to another Master device on the bus. 1 ACK_RESP R Not Acknowledge Response flag While SIOE is in Transmitter mode: – After SIOE sends a byte, ACK_RESP = 1 whenever the external I2C device receives the byte, but that device does NOT assert an ackowledge signal (external device asserted a high on SDA during the acknowledge bit-time). – After SIOE sends a byte, ACK_RESP = 0 whenever the external I2C device receives the byte, and that device DOES assert an ackowledge signal (external device drove a low on SDA during the acknowledge bit-time) Note: If SIOE is in Master-Transmitter mode, and ACK_RESP = 1 due to a Slave-Transmitter not sending an Acknowledge, a STOP condition will not automatically be generated by the SIOE. The STOP condition must be generated with S1CON.STO = 1. 0 SLV R Slave Mode flag SLV = 1 when the SIOE is in Slave mode. SLV = 0 when the SIOE is in Master mode (default).uPSD33xx 104/231 I 2C Data Shift Register (S1DAT) The S1ADR register (Table 53) holds a byte of serial data to be transmitted or it holds a serial byte that has just been received. The MCU may access S1DAT while the SIOE is not in the process of shifting a byte (the INTR flag indicates shifting is complete). While transmitting, bytes are shifted out MSB first, and when receiving, bytes are shifted in MSB first, through the Acknowledge Bit register as shown in Figure 40., page 99. Bus Wait Condition. After the SIOE finishes receiving a byte in Receive mode, or transmitting a byte in Transmit mode, the INTR flag (in S1STA) is set and automatically a wait condition is imposed on the I2C bus (SCL held low by SIOE). In Transmit mode, this wait condition is released as soon as the MCU writes any byte to S1DAT. In Receive mode, the wait condition is released as soon as the MCU reads the S1DAT register. This method allows the user to handle transmit and receive operations within an interrupt service routine. The SIOE will automatically stall the I2C bus at the appropriate time, giving the MCU time to get the next byte ready to transmit or time to read the byte that was just received. Table 53. S1DAT: I2C Data Shift register (SFR DEh, reset value 00h) I 2C Address Register (S1ADR) The S1ADR register (Table 54) holds the 7-bit device address used when the SIOE is operating as a Slave. When the SIOE receives an address from a Master, it will compare this address to the contents of S1ADR, as shown in Figure 40., page 99. If the 7 bits match, the INTR Interrupt flag (in S1STA) is set, and the ADDR Bit (in S1CON) is set. The SIOE cannot modify the contents S1ADR, and S1ADR is not used during Master mode. Table 54. S1ADR: I2C Address register (SFR DFh, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S1DAT[7:0] Details Bit Symbol R/W Function 7:0 S1DAT[7:0] R/W Holds the data byte to be transmitted in Transmit mode, or it holds the data byte received in Receiver mode. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 – Details Bit Symbol R/W Function 7:1 SLA[6:0] R/W Stores desired 7-bit device address, used when SIOE is in Slave mode. 0 – – Not used105/231 uPSD33xx I 2C START Sample Setting (S1SETUP) The S1SETUP register (Table 55) determines how many times an I2C bus START condition will be sampled before the SIOE validates the START condition, giving the SIOE the ability to reject noise or illegal transmissions. Because the minimum duration of an START condition varies with I2C bus speed (fSCL), and also because the uPSD33xx may be operated with a wide variety of frequencies (fOSC), it is necessary to scale the number of samples per START condition based on fOSC and fSCL. In Slave mode, the SIOE recognizes the beginning of a START condition when it detects a '1'-to-'0' transition on the SDA bus line while the SCL line is high (see Figure 39., page 97). The SIOE must then validate the START condition by sampling the bus lines to ensure SDA remains low and SCL remains high for a minimum amount of hold time, tHLDSTA. Once validated, the SIOE begins receiving the address byte that follows the START condition. If the EN_SS Bit (in the S1SETUP Register) is not set, then the SIOE will sample only once after detecting the '1'-to-'0' transition on SDA. This single sample is taken 1/fOSC seconds after the initial 1- to-0 transition was detected. However, more samples should be taken to ensure there is a valid START condition. To take more samples, the SIOE should be initialized such that the EN_SS Bit is set, and a value is written to the SMPL_SET[6:0] field of the S1SETUP Register to specify how many samples to take. The goal is to take a good number of samples during the minimum START condition hold time, tHLDSTA, but no so many samples that the bus will be sampled after tHLDSTA expires. Table 56., page 106 describes the relationship between the contents of S1SETUP and the resulting number of I2C bus samples that SIOE will take after detecting the 1-to-0 transition on SDA of a START condition. Important: Keep in mind that the time between samples is always 1/fOSC. The minimum START condition hold time, tHLDSTA, is different for the three common I2C speed categories per Table 57., page 106. Table 55. S1SETUP: I2C START Condition Sample Setup register (SFR DBh, reset value 00h) Note: 1. Sampling SCL and SDA lines begins after '1'-to-'0' transition on SDA occurred while SCL is high. Time between samples is 1/fOSC. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN_SS SMPL_SET[6:0] Details Bit Symbol R/W Function 7 EN_SS R/W Enable Sample Setup EN_SS = 1 will force the SIOE to sample(1) a START condition on the bus the number of times specified in SMPL_SET[6:0]. EN_SS = 0 means the SIOE will sample(1) a START condition only one time, regardless of the contents of SMPL_SET[6:0]. 6:0 SMPL_SET [6:0] – Sample Setting Specifies the number of bus samples(1) taken during a START condition. See Table 56 for values.uPSD33xx 106/231 Table 56. Number of I2C Bus Samples Taken after 1-to-0 Transition on SDA (START Condition) Table 57. Start Condition Hold Time Note: 1. 833KHz is maximum for uPSD33xx devices. Contents of S1SETUP Resulting value for S1SETUP Resulting Number of Samples Taken After 1-to-0 on SDA Line SS_EN bit SMPL_SET[6:0] 0 XXXXXXXb 00h (default) 1 1 0000000b 80h 1 1 0000001b 81h 2 1 0000010b 82h 3 ... ... ... ... 1 0001011b 8Bh 12 1 0010111b 97h 24 ... ... ... ... 1 1111111b FFh 128 I 2C Bus Speed Range of I2C Clock Speed (fSCL) Minimum START Condition Hold Time (tHLDSTA) Standard Up to 100KHz 4000ns Fast 101KHz to 400KHz 600ns High 401KHz to 833KHz(1) 160ns107/231 uPSD33xx Table 58 provides recommended settings for S1SETUP based on various combinations of fOSC and fSCL. Note that the “Total Sample Period” times in Table 57., page 106 are typically slightly less than the minimum START condition hold time, tHLDSTA for a given I2C bus speed. Important: The SCL bit rate fSCL must first be determined by bits CR[2:0] in the SFR S1CON before a value is chosen for SMPL_SET[6:0] in the SFR S1SETUP. Table 58. S1SETUP Examples for Various I2C Bus Speeds and Oscillator Frequencies Note: 1. Not compatible with High Speed I2C. I 2C Bus Speed, fSCL Parameter Oscillator Frequency, fOSC 6 MHz 12 MHz 24 MHz 33 MHz 40 MHz Standard Recommended S1SETUP Value 93h A7h CFh EEh FFh Number of Samples 20 40 80 111 128 Time Between Samples 166.6ns 83.3ns 41.6ns 30ns 25ns Total Sampled Period 3332ns 3332ns 3332ns 3333ns 3200ns Fast Recommended S1SETUP Value 82h 85h 8Bh 90h 93h Number of Samples 3 6 12 17 20 Time Between Samples 166.6ns 83.3ns 41.6ns 30ns 25ns Total Sampled Period 500ns 500ns 500ns 510ns 500ns High Recommended S1SETUP Value (Note 1) 80 82 83 84 Number of Samples - 1 3 4 5 Time Between Samples - 83.3ns 41.6ns 30ns 25ns Total Sampled Period - 83.3 125ns 120ns 125nsuPSD33xx 108/231 I 2C Operating Sequences The following pseudo-code explains hardware control for these I2C functions on the uPSD33xx: – Initialize the Interface – Function as Master-Transmitter – Function as Master-Receiver – Function as Slave-Transmitter – Function as Slave-Receiver – Interrupt Service Routine Full C code drivers for the uPSD33xx I2C interface, and other interfaces are available from the web at www.st.com\psm. Initialization after a uPSD33xx reset Ensure pins P3.6 and P3.7 are GPIO inputs – SFR P3.7 = 1 and SFR P3.6 = 1 Configure pins P3.6 and P3.7 as I2C – SFR P3SFS.6 = 1 and P3SFS.7 = 1 Set I2C clock prescaler to determine fSCL – SFR S1CON.CR[2:0] = desired SCL freq. Set bus START condition sampling – SFR S1SETUP[7:0] = number of samples Enable individual I2C interrupt and set priority – SFR IEA.I2C = 1 – SFR IPA.I2C = 1 if high priority is desired Set the Device address for Slave mode – SFR S1ADR = XXh, desired address Enable SIOE (as Slave) to return an ACK signal – SFR S1CON.AA = 1 Master-Transmitter Disable all interrupts – SFR IE.EA = 0 Set pointer to global data xmit buffer, set count – *xmit_buf = *pointer to data – buf_length = number of bytes to xmit Set global variables to indicate Master-Xmitter – I2C_master = 1, I2C_xmitter = 1 Disable Master from returning an ACK – SFR S1CON.AA = 0 Enable I2C SIOE – SFR S1CON.INI1 = 1 Transmit Address and R/W bit = 0 to Slave – Is bus not busy? (SFR S1STA.BBUSY = 0?) – SFR S1DAT[7:0] = Load Slave Address & FEh – SFR S1CON.STA = 1, send START on bus Enable All Interrupts and go do something else – SFR IE.EA = 1 Master-Receiver Disable all interrupts – SFR IE.EA = 0 Set pointer to global data recv buffer, set count – *recv_buf = *pointer to data – buf_length = number of bytes to recv Set global variables to indicate Master-Xmitter – I2C_master = 1, I2C_xmitter = 0 Disable Master from returning an ACK – SFR S1CON.AA = 0 Enable I2C SIOE – SFR S1CON.INI1 = 1 Transmit Address and R/W bit = 1 to Slave – Is bus not busy? (SFR S1STA.BBUSY = 0?) – SFR S1DAT[7:0] = Load Slave Address # 01h – SFR S1CON.STA = 1, send START on bus Enable All Interrupts and go do something else – SFR IE.EA = 1109/231 uPSD33xx Slave-Transmitter Disable all interrupts – SFR IE.EA = 0 Set pointer to global data xmit buffer, set count – *xmit_buf = *pointer to data – buf_length = number of bytes to xmit Set global variables to indicate Master-Xmitter – I2C_master = 0, I2C_xmitter = 1 Enable SIOE – SFR S1CON.INI1 = 1 Prepare to Xmit first data byte – SFR S1DAT[7:0] = xmit_buf[0] Enable All Interrupts and go do something else – SFR IE.EA = 1 Slave-Receiver Disable all interrupts – SFR IE.EA = 0 Set pointer to global data recv buffer, set count – *recv_buf = *pointer to data – buf_length = number of bytes to recv Set global variables to indicate Master-Xmitter – I2C_master = 0, I2C_xmitter = 0 Enable SIOE – SFR S1CON.INI1 = 1 Enable All Interrupts and go do something else – SFR IE.EA = 1 Interrupt Service Routine (ISR). A typical I2C interrupt service routine would handle a interrupt for any of the four combinations of Master/Slave and Transmitter/Receiver. In the example routines above, the firmware sets global variables, I2C_master and I2C_xmitter, before enabling interrupts. These flags tell the ISR which one of the four cases to process. Following is pseudo-code for high-level steps in the I2C ISR: Begin I2C ISR : Clear I2C interrupt flag: – S1STA.INTR = 0 Read status of SIOE, put in to variable, status – status = S1STA Read global variables that determine the mode – mode <= (I2C_master, I2C_slave) If mode is Master-Transmitter Bus Arbitration lost? (status.BLOST=1?) If Yes, Arbitration was lost: – S1DAT = dummy, write to release bus – Exit ISR, SIOE will switch to Slave Recv mode If No, Arbitration was not lost, continue: ACK recvd from Slave? (status.ACK_RESP=0?) If No, an ACK was not received: – S1CON.STO = 1, set STOP bus condition – – S1DAT = dummy, write to release bus – Exit ISR If Yes, ACK was received, then continue: – S1DAT = xmit_buf[buffer_index], transmit byte Was that the last byte of data to transmit? If No, it was not the last byte, then: – Exit ISR, transmit next byte on next interrupt If Yes, it was the last byte, then: – S1CON.STO = 1, set STOP bus condition – S1DAT = dummy, write to release bus – Exit ISRuPSD33xx 110/231 Else If mode is Master-Receiver: Bus Arbitration lost? (status.BLOST=1?) If Yes, Arbitration was lost: – S1DAT = dummy, write to release bus – Exit ISR, SIOE will switch to Slave Recv mode If No, Aribitration was not lost, continue: Is this Interrupt from sending an address to Slave, or is it from receiving a data byte from Slave? If its from sending Slave address, goto A: If its from receiving Slave data, goto B: A: (Interrupt is from Master sending addr to Slave) ACK recvd from Slave? (status.ACK_RESP=0?) If No, an ACK was not received: – S1CON.STO = 1, set STOP condition – dummy = S1DAT, read to release bus – Exit ISR If Yes, ACK was received, then continue: – dummy = S1DAT, read to release bus Does Master want to receive just one data byte? If Yes, do not allow Master to ACK on next interrupt: – Exit ISR, now ready to recv one byte from Slv If No, Master can ACK next byte from Slv – S1CON.AA = 1, allow Master to send ACK – Exit ISR, now ready to recv data from Slave B: (Interrupt is from Master recving data from Slv) – recv_buf[buffer_index] = S1DAT, read byte Is this the last data byte to receive from Slave? If Yes, tell Slave to stop transmitting: – S1CON.STO = 1, set STOP bus condition – Exit ISR, finished receiving data from Slave If No, continue: Is this the next to last byte to receive from Slave? If this is the next to last byte, do not allow Master to ACK on next interrupt. – S1CON.AA = 0, don’t let Master return ACK – Exit ISR, now ready to recv last byte from Slv If this is not next to last byte, let Master send ACK to Slave – Exit ISR, ready to recv more bytes from Slave Else If mode is Slave-Transmitter: Is this Intr from SIOE detecting a STOP on bus? If Yes, a STOP was detected: – S1DAT = dummy, write to release bus – Exit ISR, Master needs no more data bytes If No, a STOP was not detected, continue: ACK recvd from Master? (status.ACK_RESP=0?) If No, an ACK was not received: – S1DAT = dummy, write to release bus – Exit ISR, Master needs no more data bytes If Yes, ACK was received, then continue: – S1DAT = xmit_buf[buffer_index], transmit byte – Exit ISR, transmit next byte on next interrupt111/231 uPSD33xx Else If mode is Slave-Receiver: Is this Intr from SIOE detecting a STOP on bus? If Yes, a STOP was detected: – recv_buf[buffer_index] = S1DAT, get last byte – Exit ISR, Master has sent last byte If No, a STOP was not detected, continue: Determine if this Interrupt is from receiving an address or a data byte from a Master. Is (S1CON.ADDR = 1 and S1CON.AA =1)? If No, intr is from receiving data, goto C: If Yes, intr is from an address, continue: – slave_is_adressed = 1, local variable set true – S1CON.ADDR = 0, clear address match flag Determine if R/W bit indicates transmit or receive. Does status.TX_MODE = 1? If Yes, Master wants transmit mode – Exit ISR, indicate Master wants Slv-Xmit mode If No, Master wants Slave-Recv mode – dummy = S1DAT, read taran se bueuPSD33xx 112/231 SPI (SYNCHRONOUS PERIPHERAL INTERFACE) uPSD33xx devices support one serial SPI interface in Master Mode only. This is a three- or fourwire synchronous communication channel, capable of full-duplex operation on 8-bit serial data transfers. The four SPI bus signals are: ■ SPIRxD Pin P1.5 or P4.5 receives data from the Slave SPI device to the uPSD33xx ■ SPITxD Pin P1.6 or P4.6 transmits data from the uPSD33xx to the Slave SPI device ■ SPICLK Pin P1.4 or P4.4 clock is generated from the uPSD33xx to the SPI Slave device ■ SPISEL Pin P1.7 or P4.7 selects the signal from the uPSD33xx to an individual Slave SPI device This SPI interface supports single-Master/multiple-Slave connections. Multiple-Master connections are not directly supported by the uPSD33xx (no internal logic for collision detection). If more than one Slave device is required, the SPISEL signal may be generated from uPSD33xx GPIO outputs (one for each Slave) or from the PLD outputs of the PSD Module. Figure 41. illustrates three examples of SPI device connections using the uPSD33xx: ■ Single-Master/Single-Slave with SPISEL ■ Single-Master/Single-Slave without SPISEL ■ Single-Master/Multiple-Slave without SPISEL Figure 41. SPI Device Connection Examples SPI Bus SPI Bus SPI Bus SPITxD SPIRxD uPSD33xx SPI Master SPI Slave SPICLK Device SPISEL AI07853b MOSI MISO SCLK Single-Master/Single-Slave, with SPISEL Single-Master/Single-Slave, without SPISEL Single-Master/Multiple-Slave, without SPISEL SS SPI Slave Device MOSI MISO SCLK SS SPI Slave Device MOSI MISO SCLK SS SS SPITxD SPIRxD uPSD33xx SPI Master SPI Slave SPICLK Device SPITxD SPIRxD uPSD33xx SPI Master SPICLK GPIO or PLD GPIO or PLD MOSI MISO SCLK113/231 uPSD33xx SPI Bus Features and Communication Flow The SPICLK signal is a gated clock generated from the uPSD33xx (Master) and regulates the flow of data bits. The Master may transmit at a variety of baud rates, and the SPICLK signal will clock one period for each bit of transmitted data. Data is shifted on one edge of SPICLK and sampled on the opposite edge. The SPITxD signal is generated by the Master and received by the Slave device. The SPIRxD signal is generated by the Slave device and received by the Master. There may be no more than one Slave device transmitting data on SPIRxD at any given time in a multi-Slave configuration. Slave selection is accomplished when a Slave’s “Slave Select” (SS) input is permanently grounded or asserted active-low by a Master device. Slave devices that are not selected do not interfere with SPI activities. Slave devices ignore SPICLK and keep their MISO output pins in high-impedance state when not selected. The SPI specification allows a selection of clock polarity and clock phase with respect to data. The uPSD33xx supports the choice of clock polarity, but it does not support the choice of clock phase (phase is fixed at what is typically known as CPHA = 1). See Figure 43. and Figure 44., page 114 for SPI data and clock relationships. Referring to these figures (43 and 44), when the phase mode is defined as such (fixed at CPHA =1), in a new SPI data frame, the Master device begins driving the first data bit on SPITxD at the very first edge of the first clock period of SPICLK. The Slave device will use this first clock edge as a transmission start indicator, and therefore the Slave’s Slave Select input signal may remain grounded in a single-Master/single-Slave configuration (which means the user does not have to use the SPISEL signal from uPSD33xx in this case). The SPI specification does not specify high-level protocol for data exchange, only low-level bit-serial transfers are defined. Full-Duplex Operation When an SPI transfer occurs, 8 bits of data are shifted out on one pin while a different 8 bits of data are simultaneously shifted in on a second pin. Another way to view this transfer is that an 8-bit shift register in the Master and another 8-bit shift register in the Slave are connected as a circular 16-bit shift register. When a transfer occurs, this distributed shift register is shifted 8 bit positions; thus, the data in the Master and Slave devices are effectively exchanged (see Figure 42.). Bus-Level Activity Figure 43. details an SPI receive operation (with respect to bus Master) and Figure 44. details an SPI transmit operation. Also shown are internal flags available to firmware to manage data flow. These flags are accessed through a number of SFRs. Note: The uPSD33xx SPI interface SFRs allow the choice of transmitting the most significant bit (MSB) of a byte first, or the least significant bit (LSB) first. The same bit-order applies to data reception. Figures 43 and 44 illustrate shifting the LSB first. Figure 42. SPI Full-Duplex Data Exchange SPI Bus Master Device Slave Device AI10485 SS SPITxD SPIRxD Baud Rate Generator 8-Bit Shift Register 8-Bit Shift Register SPICLK MOSI MISO SCLKuPSD33xx 114/231 Figure 43. SPI Receive Operation Example Figure 44. SPI Transmit Operation Example Bit7 SPICLK (SPO=0) SPICLK (SPO=1) SPIRXD Bit0 Bit1 Bit7 Bit0 Bit1 Bit7 1 frame RISF RORIS BUSY SPIINTR SPIRDR Full interrupt requested Interrupt handler read data in SPIRDR SPIRDR Full interrupt requested Transmit End interrupt requested AI07855 Bit0 SPICLK (SPO=0) SPICLK (SPO=1) SPITXD Bit1 Bit7 Bit0 Bit1 Bit7 1 frame TISF TEISF BUSY SPIINTR SPITDR Empty interrupt requested Interrupt handler write data in TDR SPITDR Empty interrupt requested Transmit End interrupt requested SPISEL AI07854115/231 uPSD33xx SPI SFR Registers Six SFR registers control the SPI interface: ■ SPICON0 (Table 59., page 117) for interface control ■ SPICON1 (Table 60., page 118) for interrupt control ■ SPITDR (SFR D4h, Write only) holds byte to transmit ■ SPIRDR (SFR D5h, Read only) holds byte received ■ SPICLKD (Table 61., page 118) for clock divider ■ SPISTAT (Table 62., page 119) holds interface status The SPI interface functional block diagram (Figure 45.) shows these six SFRs. Both the transmit and receive data paths are double-buffered, meaning that continuous transmitting or receiving (back-toback transfer) is possible by reading from SPIRDR or writing data to SPITDR while shifting is taking place. There are a number of flags in the SPISTAT register that indicate when it is full or empty to assist the 8032 MCU in data flow management. When enabled, these status flags will cause an interrupt to the MCU. Figure 45. SPI Interface, Master Mode Only SPITDR - TRANSMIT REGISTER SPITxD / P1.6 or P4.6 TIMING AND CONTROL (fOSC) INTR to 8032 SPIRDR - RECEIVE REGISTER 8-bit SHIFT REGISTER 8 8 8 8 SPIRxD / P1.5 or P4.5 SPICON0, SPICON1 - CONTROL REGISTERS 8 SPISTAT - STATUS REGISTER 8 8032 MCU DATA BUS CLOCK GENERATE SPISEL / P1.7 or P4.7 CLOCK SPICLK / P1.4 or P4.4 DIVIDE ÷1 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 SPICLKD - DIVIDE SELECT 8 PERIPH_CLK AI10486uPSD33xx 116/231 SPI Configuration The SPI interface is reset by the MCU reset, and firmware needs to initialize the SFRs SPICON0, SPICON1, and SPICLKD to define several operation parameters. The SPO Bit in SPICON0 determines the clock polarity. When SPO is set to '0,' a data bit is transmitted on SPITxD from one rising edge of SPICLK to the next and is guaranteed to be valid during the falling edge of SPICLK. When SPO is set to '1,' a data bit is transmitted on SPITxD from one falling edge of SPICLK to the next and is guaranteed to be valid during the rising edge of SPICLK. The uPSD33xx will sample received data on the appropriate edge of SPICLK as determined by SPO. The effect of the SPO Bit can be seen in Figure 43. and Figure 44., page 114. The FLSB Bit in SPICON0 determines the bit order while transmitting and receiving the 8-bit data. When FLSB is '0,' the 8-bit data is transferred in order from MSB (first) to LSB (last). When FLSB Bit is set to '1,' the data is transferred in order from LSB (first) to MSB (last). The clock signal generated on SPICLK is derived from the internal PERIPH_CLK signal. PERIPH_CLK always operates at the frequency, fOSC, and runs constantly except when stopped in MCU Power Down mode. SPICLK is a result of dividing PERIPH_CLK by a sum of different divisors selected by the value contained in the SPICLKD register. The default value in SPICLKD after a reset divides PERIPH_CLK by a factor of 4. The bits in SPICLKD can be set to provide resulting divisor values in of sums of multiples of 4, such as 4, 8, 12, 16, 20, all the way up to 252. For example, if SPICLKD contains 0x24, SPICLK has the frequency of PERIH_CLK divided by 36 decimal. The SPICLK frequency must be set low enough to allow the MCU time to read received data bytes without loosing data. This is dependent upon many things, including the crystal frequency of the MCU and the efficiency of the SPI firmware. Dynamic Control At runtime, bits in registers SPICON0, SPICON1, and SPISTAT are managed by firmware for dynamic control over the SPI interface. The bits Transmitter Enable (TE) and Receiver Enable (RE) when set will allow transmitting and receiving respectively. If TE is disabled, both transmitting and receiving are disabled because SPICLK is driven to constant output logic ‘0’ (when SPO = 0) or logic '1' (when SPO = 1). When the SSEL Bit is set, the SPISEL pin will drive to logic '0' (active) to select a connected slave device at the appropriate time before the first data bit of a byte is transmitted, and SPISEL will automatically return to logic '1' (inactive) after transmitting the eight bit of data, as shown in Figure 44., page 114. SPISEL will continue to automatically toggle this way for each byte data transmission while the SSEL bit is set by firmware. When the SSEL Bit is cleared, the SPISEL pin will drive to constant logic '1' and stay that way (after a transmission in progress completes). The Interrupt Enable Bits (TEIE, RORIE,TIE, and RIE) when set, will allow an SPI interrupt to be generated to the MCU upon the occurrence of the condition enabled by these bits. Firmware must read the four corresponding flags in the SPISTAT register to determine the specific cause of interrupt. These flags are automatically cleared when firmware reads the SPISTAT register.117/231 uPSD33xx Table 59. SPICON0: Control Register 0 (SFR D6h, Reset Value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – TE RE SPIEN SSEL FLSB SBO – Details Bit Symbol R/W Definition 7 – – Reserved 6 TE RW Transmitter Enable 0 = Transmitter is disabled 1 = Transmitter is enabled 5 RE RW Receiver Enable 0 = Receiver is disabled 1 = Receiver is enabled 4 SPIEN RW SPI Enable 0 = Entire SPI Interface is disabled 1 = Entire SPI Interface is enabled 3 SSEL RW Slave Selection 0 = SPISEL output pin is constant logic '1' (slave device not selected) 1 = SPISEL output pin is logic '0' (slave device is selected) during data transfers 2 FLSB RW First LSB 0 = Transfer the most significant bit (MSB) first 1 = Transfer the least significant bit (LSB) first 1 SPO – Sampling Polarity 0 = Sample transfer data at the falling edge of clock (SPICLK is '0' when idle) 1 = Sample transfer data at the rising edge of clock (SPICLK is '1' when idle) 0 – – ReserveduPSD33xx 118/231 Table 60. SPICON1: SPI Interface Control Register 1 (SFR D7h, Reset Value 00h) Table 61. SPICLKD: SPI Prescaler (Clock Divider) Register (SFR D2h, Reset Value 04h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – – TEIE RORIE TIE RIE Details Bit Symbol R/W Definition 7-4 – – Reserved 3 TEIE RW Transmission End Interrupt Enable 0 = Disable Interrupt for Transmission End 1 = Enable Interrupt for Transmission End 2 RORIE RW Receive Overrun Interrupt Enable 0 = Disable Interrupt for Receive Overrun 1 = Enable Interrupt for Receive Overrun 1 TIE RW Transmission Interrupt Enable 0 = Disable Interrupt for SPITDR empty 1 = Enable Interrupt for SPITDR empty 0 RIE RW Reception Interrupt Enable 0 = Disable Interrupt for SPIRDR full 1 = Enable Interrupt for SPIRDR full Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DIV128 DIV64 DIV32 DIV16 DIV8 DIV4 – – Details Bit Symbol R/W Definition 7 DIV128 RW 0 = No division 1 = Divide fOSC clock by 128 6 DIV64 RW 0 = No division 1 = Divide fOSC clock by 64 5 DIV32 RW 0 = No division 1 = Divide fOSC clock by 32 4 DIV16 RW 0 = No division 1 = Divide fOSC clock by 16 3 DIV8 RW 0 = No division 1 = Divide fOSC clock by 8 2 DIV4 RW 0 = No division 1 = Divide fOSC clock by 4 1-0 Not Used –119/231 uPSD33xx Table 62. SPISTAT: SPI Interface Status Register (SFR D3h, Reset Value 02h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – BUSY TEISF RORISF TISF RISF Details Bit Symbol R/W Definition 7-5 – – Reserved 4 BUSY R SPI Busy 0 = Transmit or Receive is completed 1 = Transmit or Receive is in process 3 TEISF R Transmission End Interrupt Source flag 0 = Automatically resets to '0' when firmware reads this register 1 = Automatically sets to '1' when transmission end occurs 2 RORISF R Receive Overrun Interrupt Source flag 0 = Automatically resets to '0' when firmware reads this register 1 = Automatically sets to '1' when receive overrun occurs 1 TISF R Transfer Interrupt Source flag 0 = Automatically resets to '0' when SPITDR is full (just after the SPITDR is written) 1 = Automatically sets to '1' when SPITDR is empty (just after byte loads from SPITDR into SPI shift register) 0 RISF R Receive Interrupt Source flag 0 = Automatically resets to '0' when SPIRDR is empty (after the SPIRDR is read) 1 = Automatically sets to '1' when SPIRDR is fulluPSD33xx 120/231 ANALOG-TO-DIGITAL CONVERTOR (ADC) The ADC unit in the uPSD33xx is a SAR type ADC with an SAR register, an auto-zero comparator and three internal DACs. The unit has 8 input channels with 10-bit resolution. The A/D converter has its own VREF input (80-pin package only), which specifies the voltage reference for the A/D operations. The analog to digital converter (A/D) allows conversion of an analog input to a corresponding 10-bit digital value. The A/D module has eight analog inputs (P1.0 through P1.7) to an 8x1 multiplexor. One ADC channel is selected by the bits in the configuration register. The converter generates a 10-bits result via successive approximation. The analog supply voltage is connected to the VREF input, which powers the resistance ladder in the A/D module. The A/D module has 3 registers, the control register ACON, the A/D result register ADAT0, and the second A/D result register ADAT1. The ADAT0 Register stores Bits 0.. 7 of the converter output, Bits 8.. 9 are stored in Bits 0..1 of the ADAT1 Register. The ACON Register controls the operation of the A/D converter module. Three of the bits in the ACON Register select the analog channel inputs, and the remaining bits control the converter operation. ADC channel pin input is enabled by setting the corresponding bit in the P1SFS0 and P1SFS1 Registers to '1' and the channel select bits in the ACON Register. The ADC reference clock (ADCCLK) is generated from fOSC divided by the divider in the ADCPS Register. The ADC operates within a range of 2 to 16MHz, with typical ADCCLK frequency at 8MHz. The conversion time is 4µs typical at 8MHz. The processing of conversion starts when the Start Bit ADST is set to '1.' After one cycle, it is cleared by hardware. The ADC is monotonic with no missing codes. Measurement is by continuous conversion of the analog input. The ADAT Register contains the results of the A/D conversion. When conversion is complete, the result is loaded into the ADAT. The A/D Conversion Status Bit ADSF is set to '1.' The block diagram of the A/D module is shown in Figure 46. The A/D status bit ADSF is set automatically when A/D conversion is completed and cleared when A/D conversion is in process. In addition, the ADC unit sets the interrupt flag in the ACON Register after a conversion is complete (if AINTEN is set to '1'). The ADC interrupts the CPU when the enable bit AINTEN is set. Port 1 ADC Channel Selects The P1SFS0 and P1SFS1 Registers control the selection of the Port 1 pin functions. When the P1SFS0 Bit is '0,' the pin functions as a GPIO. When bits are set to '1,' the pins are configured as alternate functions. A new P1SFS1 Register selects which of the alternate functions is enabled. The ADC channel is enabled when the bit in P1SFS1 is set to '1.' Note: In the 52-pin package, there is no individual VREF pin because VREF is combined with AVCC pin. Figure 46. 10-Bit ADC ANALOG MUX SELECT ADC OUT - 10 BITS ACON REG ADAT 0 REG CONTROL 10-BIT SAR ADC ADAT1 REG ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 AVREF P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 AVREF AI07856121/231 uPSD33xx Table 63. ACON Register (SFR 97h, Reset Value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AINTF AINTEN ADEN ADS2 ADS1 ADS0 ADST ADSF Details Bit Symbol Function 7 AINTF ADC Interrupt flag. This bit must be cleared with software. 0 = No interrupt request 1 = The AINTF flag is set when ADSF goes from '0' to '1.' Interrupts CPU when both AINTF and AINTEN are set to '1.' 6 AINTEN ADC Interrupt Enable 0 = ADC interrupt is disabled 1 = ADC interrupt is enabled 5 ADEN ADC Enable Bit 0 = ADC shut off and consumes no operating current 1 = Enable ADC. After ADC is enabled, 16ms of calibration is needed before ADST Bit is set. 4.. 2 ADS2.. 0 Analog channel Select 000 Select channel 0 (P1.0) 001 Select channel 0 (P1.1) 010 Select channel 0 (P1.2) 011 Select channel 0 (P1.3) 101 Select channel 0 (P1.5) 110 Select channel 0 (P1.6) 111 Select channel 0 (P1.7) 1 ADST ADC Start Bit 0 = Force to zero 1 = Start ADC, then after one cycle, the bit is cleared to '0.' 0 ADSF ADC Status Bit 0 = ADC conversion is not completed 1 = ADC conversion is completed. The bit can also be cleared with software.uPSD33xx 122/231 Table 64. ADCPS Register Details (SFR 94h, Reset Value 00h) Table 65. ADAT0 Register (SFR 95H, Reset Value 00h) Table 66. ADAT1 Register (SFR 96h, Reset Value 00h) Bit Symbol Function 7:4 – Reserved 3 ADCCE ADC Conversion Reference Clock Enable 0 = ADC reference clock is disabled (default) 1 = ADC reference clock is enabled 2:0 ADCPS[2:0] ADC Reference Clock PreScaler Only three Prescaler values are allowed: ADCPS[2:0] = 0, for fOSC frequency 16MHz or less. Resulting ADC clock is fOSC. ADCPS[2:0] = 1, for fOSC frequency 32MHz or less. Resulting ADC clock is fOSC/2. ADCPS[2:0] = 2, for fOSC frequency 32MHz > 40MHz. Resulting ADC clock is fOSC/4. Bit Symbol Function 7:0 – Store ADC output, Bit 7 - 0 Bit Symbol Function 7:2 – Reserved 1.. 0 – Store ADC output, Bit 9, 8123/231 uPSD33xx PROGRAMMABLE COUNTER ARRAY (PCA) WITH PWM There are two Programmable Counter Array blocks (PCA0 and PCA1) in the uPSD33xx. A PCA block consists of a 16-bit up-counter, which is shared by three TCM (Timer Counter Module). A TCM can be programmed to perform one of the following four functions: 1. Capture Mode: capture counter values by external input signals 2. Timer Mode 3. Toggle Output Mode 4. PWM Mode: fixed frequency (8-bit or 16-bit), programmable frequency (8-bit only) PCA Block The 16-bit Up-Counter in the PCA block is a freerunning counter (except in PWM Mode with programmable frequency). The Counter has a choice of clock input: from an external pin, Timer 0 Overflow, or PCA Clock. A PCA block has 3 Timer Counter Modules (TCM) which share the 16-bit Counter output. The TCM can be configured to capture or compare counter value, generate a toggling output, or PWM functions. Except for the PWM function, the other TCM functions can generate an interrupt when an event occurs. Every TCM is connected to a port pin in Port 4; the TCM pin can be configured as an event input, a PWMs, a Toggle Output, or as External Clock Input. The pins are general I/O pins when not assigned to the TCM. The TCM operation is configured by Control registers and Capture/Compare registers. Table 67., page 124 lists the SFR registers in the PCA blocks. Figure 47. PCA0 Block Diagram TIMER0 OVERFLOW P4.3/ECI PCACH0 8-bit PCACL0 8-bit CLKSEL1 IDLE MODE (From CPU) OVF0 INT EOVFI TCM0 TCM1 TCM2 PWM FREQ COMPARE P4.0/CEX0 P4.1/CEX1 P4.2/CEX2 16-bit up Timer/Counter CLKSEL0 PCAIDLE PCA0CLK CLEAR COUNTER EN_PCA EN_ALL AI07857uPSD33xx 124/231 Table 67. PCA0 and PCA1 Registers SFR Address Register Name RW Register Function PCA0 PCA1 PCA0 PCA1 A2 BA PCACL0 PCACL1 RW The low 8 bits of PCA 16-bit counter. A3 BB PCACH0 PCACH1 RW The high 8 bits of PCA 16-bit counter. A4 BC PCACON0 PCACON1 RW Control Register – Enable PCA, Timer Overflow flag , PCA Idle Mode, and Select clock source. A5 A5 PCASTA N/A RW Status Register, Interrupt Status flags – Common for both PCA Block 0 and 1. A9, AA, AB BD, BE, BF TCMMODE0 TCMMODE1 TCMMODE2 TCMMODE3 TCMMODE4 TCMMODE5 RW TCM Mode – Capture, Compare, and Toggle Enable Interrupts – PWM Mode Select. AC AD C1 C2 CAPCOML0 CAPCOMH0 CAPCOML3 CAPCOMH3 RW Capture/Compare registers of TCM0 AF B1 C3 C4 CAPCOML1 CAPCOMH1 CAPCOML4 CAPCOMH4 RW Capture/Compare registers of TCM1 B2 B3 C5 C6 CAPCOML2 CAPCOMH2 CAPCOML5 CAPCOMH5 RW Capture/Compare registers of TCM2 B4 C7 PWMF0 PWMF1 RW The 8-bit register to program the PWM frequency. This register is used for programmable, 8-bit PWM Mode only. FB FC CCON2 CCON3 RW Specify the pre-scaler value of PCA0 or PCA1 clock input125/231 uPSD33xx PCA Clock Selection The clock input to the 16-bit up counter in the PCA block is user-programmable. The three clock sources are: – PCA Prescaler Clock (PCA0CLK, PCA1CLK) – Timer 0 Overflow – External Clock, Pin P4.3 or P4.7 The clock source is selected in the configuration register PCACON. The Prescaler output clock PCACLK is the fOSC divided by the divisor which is specified in the CCON2 or CCON3 Register. When External Clock is selected, the maximum clock frequency should not exceed fOSC/4. Table 68. CCON2 Register Bit Definition (SFR 0FBh, Reset Value 10h) Table 69. CCON3 Register Bit Definition (SFR 0FCh, Reset Value 10h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – PCA0CE PCA0PS3 PCA0PS2 PCA0PS1 PCA0PS0 Details Bit Symbol R/W Definition 4 PCA0CE R/W PCA0 Clock Enable 0 = PCA0CLK is disabled 1 = PCA0CLK is enabled (default) 3:0 PCA0PS [3:0] R/W PCA0 Prescaler fPCA0CLK = fOSC / (2 ^ PCA0PS[3:0]) Divisor range: 1, 2, 4, 8, 16... 16384, 32768 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – PCA1CE PCA1PS3 PCA1PS2 PCA1PS1 PCA1PS0 Details Bit Symbol R/W Definition 4 PCA1CE R/W PCA1 Clock Enable 0 = PCA1CLK is disabled 1 = PCA1CLK is enabled (default) 3:0 PCA1PS [3:0] R/W PCA1 Prescaler fPCA1CLK = fOSC / (2 ^ PCA1PS[3:0]) Divisor range: 1, 2, 4, 8, 16... 16384, 32768uPSD33xx 126/231 Operation of TCM Modes Each of the TCM in a PCA block supports four modes of operation. However, an exception is when the TCM is configured in PWM Mode with programmable frequency. In this mode, all TCM in a PCA block must be configured in the same mode or left to be not used. Capture Mode The CAPCOM registers in the TCM are loaded with the counter values when an external pin input changes state. The user can configure the counter value to be loaded by positive edge, negative edge or any transition of the input signal. At loading, the TCM can generate an interrupt if it is enabled. Timer Mode The TCM modules can be configured as software timers by enable the comparator. The user writes a value to the CAPCOM registers, which is then compared with the 16-bit counter. If there is a match, an interrupt can be generated to CPU. Toggle Mode In this mode, the user writes a value to the TCM's CAPCOM registers and enables the comparator. When there is a match with the Counter output, the output of the TCM pin toggles. This mode is a simple extension of the Timer Mode. PWM Mode - (X8), Fixed Frequency In this mode, one or all the TCM's can be configured to have a fixed frequency PWM output on the port pins. The PWM frequency depends on when the low byte of the Counter overflows (modulo 256). The duty cycle of each TCM module can be specified in the CAPCOMHn Register. When the PCA_Counter_L value is equal to or greater than the value in CAPCOMHn, the PWM output is switched to a high state. When the PCA_Counter_L Register overflows, the content in CAPCOMHn is loaded to CAPCOMLn and a new PWM pulse starts. Figure 48. Timer Mode Note: m = 0: n = 0, 1, or 2 m = 1: n = 3, 4, or 5 MATCH_TIMER INTR 0 0 0 TCMMODEn ENABLE 8 8 MATCH PCASTA CAPCOMLn PCACHm PCACLm 16-bit COMPARATOR CAPCOMHn INTFn 0 0 16-bit up Timer/Counter 8 8 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0 RESET WRITE to CAPCOMHn WRITE to CAPCOMLn 1 0 EN_FLAG C D AI07858127/231 uPSD33xx Figure 49. PWM Mode - (X8), Fixed Frequency Note: m = 0: n = 0, 1, or 2 m = 1: n = 3, 4, or 5 CAPCOMHn OVERFLOW ENABLE 8 PCACLm 8 CAPCOMLn 8-bit COMPARATORn CEXn MATCH S R Q Q SET CLR 0 0 TCMMODEn 0 0 0 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0 AI07859uPSD33xx 128/231 PWM Mode - (X8), Programmable Frequency In this mode, the PWM frequency is not determined by the overflow of the low byte of the Counter. Instead, the frequency is determined by the PWMFm Register. The user can load a value in the PWMFm Register, which is then compared to the low byte of the Counter. If there is a match, the Counter is cleared and the Load registers (PWMFm, CAPCOMHn) are re-loaded for the next PWM pulse. There is only one PWMFm Register which serves all 3 TCM in a PCA block. If one of the TCM modules is operating in this mode, the other modules in the PCA must be configured to the same mode or left not to be used. The duty cycle of the PWM can be specified in the CAPCOMHn Register as in the PWM with fixed frequency mode. Different TCM modules can have their own duty cycle. Note: The value in the Frequency Register (PWMFm) must be larger than the duty cycle register (CAPCOM). Figure 50. PWM Mode - (X8) Programmable Frequency Note: m = 0: n = 0, 1, or 2 m = 1: n = 3, 4, or 5 CLR PCACHm PWM FREQ COMPARE PWMFm = PCACLm PCACLm CAPCOMHn ENABLE ENABLE CEXn 8 8 PWMFm 8-bit COMPARATORm 8-bit COMPARATORn CAPCOMLn MATCH S R Q Q SET CLR 8 0 0 TCMMODEn 0 0 0 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0 AI07860129/231 uPSD33xx PWM Mode - Fixed Frequency, 16-bit The operation of the 16-bit PWM is the same as the 8-bit PWM with fixed frequency. In this mode, one or all the TCM can be configured to have a fixed frequency PWM output on the port pins. The PWM frequency is depending on the clock input frequency to the 16-bit Counter. The duty cycle of each TCM module can be specified in the CAPCOMHn and CAPCOMLn Registers. When the 16- bit PCA_Counter is equal or greater than the values in registers CAPCOMHn and CAPCOMLn, the PWM output is switched to a high state. When the PCA_Counter overflows, CEXn is asserted low. PWM Mode - Fixed Frequency, 10-bit The 10-bit PWM logic requires that all 3 TCMs in PCA0 or PCA1 operate in the same 10-bit PWM mode. The 10-bit PWM operates in a similar manner as the 16-bit PWM, except the PCACHm and PCACLm counters are reconfigured as 10-bit counters. The CAPCOMHn and CAPCOMLn Registers become 10-bit registers. PWM duty cycle of each TCM module can be specified in the 10-bit CAPCOMHn and CAPCOMLn Registers. When the 10-bit PCA counter is equal or greater than the values in the 10-bit registers CAPCOMHn and CAPCOMLn, the PWM output switches to a high state. When the 10-bit PCA counter overflows, the PWM pin is switched to a logic low and starts the next PWM pulse. The most-significant 6 bits in the PCACHm counter and CAPCOMH Register are “Don’t cares” and have no effect on the PWM generation. Writing to Capture/Compare Registers When writing a 16-bit value to the PCA Capture/ Compare registers, the low byte should always be written first. Writing to CAPCOMLn clears the E_COMP Bit to '0'; writing to CAPCOMHn sets E_COMP to '1' the largest duty cycle is 100% (CAPCOMHn CAPCOMLn = 0x0000), and the smallest duty cycle is 0.0015% (CAPCOMHn CAPCOMLn = 0xFFFF). A 0% duty cycle may be generated by clearing the E_COMP Bit to ‘0’. Control Register Bit Definition Each PCA has its own PCA_CONFIGn, and each module within the PCA block has its own TCM_Mode Register which defines the operation of that module (see Table 70., page 129 through Table 71., page 130). There is one PCA_STATUS Register that covers both PCA0 and PCA1 (see Table 72., page 131). Table 70. PCA0 Control Register PCACON0 (SFR 0A4h, Reset Value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN-ALL EN_PCA EOVFI PCAIDLE – – CLK_SEL[1:0] Details Bit Symbol Function 7 EN-ALL 0 = No impact on TCM modules 1 = Enable both PCA counters simultaneously (override the EN_PCA Bits) This bit is to start the two 16-bit counters in the PCA. For customers who want 5 PWM, for example, this bit can start all of the PWM outputs. 6 EN_PCA 0 = PCA counter is disabled 1 = PCA counter is enabled EN_PCA Counter Run Control Bit. Set with software to turn the PCA counter on. Must be cleared with software to turn the PCA counter off. 5 EOVFI 1 = Enable Counter Overflow Interrupt if overflow flag (OVF) is set 4 PCAIDLE 0 = PCA operates when CPU is in Idle Mode 1 = PCA stops running when CPU is in Idle Mode 3 – Reserved 2 10B_PWM 0 = Select 16-bit PWM 1 = Select 10-bit PWM 1-0 CLK_SEL [1:0] 00 Select Prescaler clock as Counter clock 01 Select Timer 0 Overflow 10 Select External Clock pin (P4.3 for PCA0) (MAX clock rate = fOSC/4)uPSD33xx 130/231 Table 71. PCA1 Control Register PCACON1 (SFR 0BCh, Reset Value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – EN_PCA EOVFI PCAIDLE – – CLK_SEL[1:0] Details Bit Symbol Function 6 EN_PCA 0 = PCA counter is disabled 1 = PCA counter is enabled EN_PCA Counter Run Control Bit. Set with software to turn the PCA counter on. Must be cleared with software to turn the PCA counter off. 5 EOVFI 1 = Enable Counter Overflow Interrupt if overflow flag (OVF) is set 4 PCAIDLE 0 = PCA operates when CPU is in Idle Mode 1 = PCA stops running when CPU is in Idle Mode 3 – Reserved 2 10B_PWM 0 = Select 16-bit PWM 1 = Select 10-bit PWM 1-0 CLK_SEL [1:0] 00 Select Prescaler clock as Counter clock 01 Select Timer 0 Overflow 10 Select External Clock pin (P4.7 for PCA1) (MAX clock rate = fOSC/4)131/231 uPSD33xx Table 72. PCA Status Register PCASTA (SFR 0A5h, Reset Value 00h)uPSD33xx 132/231 TCM Interrupts There are 8 TCM interrupts: 6 match or capture interrupts and two counter overflow interrupts. The 8 interrupts are “ORed” as one PCA interrupt to the CPU. By the nature of PCA application, it is unlikely that many of the interrupts occur simultaneously. If they do, the CPU has to read the interrupt flags and determine which one to serve. The software has to clear the interrupt flag in the Status Register after serving the interrupt. Table 73. TCMMODE0 - TCMMODE5 (6 Registers, Reset Value 00h) Table 74. TCMMODE Register Configurations Note: 1. 10-bit PWM mode requires the 10B_PWM Bit in the PCACON Register set to '1.' Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] Details Bit Symbol Function 7 EINTF 1 - Enable the interrupt flags (INTF) in the Status Register to generate an interrupt. 6 E_COMP 1 - Enable the comparator when set 5 CAP_PE 1 - Enable Capture Mode, a positive edge on the CEXn pin. 4 CAP_NE 1 - Enable Capture Mode, a negative edge on the CEXn pin. 3 MATCH 1 - A match from the comparator sets the INTF bits in the Status Register. 2 TOGGLE 1 - A match on the comparator results in a toggling output on CEXn pin. 1-0 PWM[1:0] 01 Enable PWM Mode (x8), fixed frequency. Enable the CEXn pin as a PWM output. 10 Enable PWM Mode (x8) with programmable frequency. Enable the CEXn pin as a PWM output. 11 Enable PWM Mode (x10 or x16), fixed frequency. Enable the CEXn pin as a PWM output. EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0 TCM FUNCTION 0 0 0 0 0 0 0 0 No operation (reset value) 0 1 0 0 0 0 0 1 8-bit PWM, fixed frequency 0 1 0 0 0 0 10 8-bit PWM, programmable frequency 0 1 0 0 0 0 11 10-bit or 16-bit PMW, fixed frequency(1) X 1 0 0 1 1 0 0 16-bit toggle X 1 0 0 1 0 0 0 16-bit Software Timer X X 0 1 0 0 0 0 16-bit capture, negative trigger X X 1 0 0 0 0 0 16-bit capture, positive trigger X X 1 1 0 0 0 0 16-bit capture, transition trigger133/231 uPSD33xx PSD MODULE The PSD Module is stacked with the MCU Module to form the uPSD33xx, see uPSD33xx HARDWARE DESCRIPTION, page 13. Details of the PSD Module are shown in Figure 51. The two separate modules interface with each other at the 8032 Address, Data, and Control interface blocks in Figure 51. Figure 51. PSD Module Block Diagram PD1 PD2 PORT D PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PORT B PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 GENERAL PLD 20 INPUT MACROCELLS A B 16 OUTPUT MACROCELLS A B A B A B A B A B A B A B B C B C B C B C B C B C B C B C SECURITY LOCK PLD INPUT BUS PIN FEEDBACK NODE FEEDBACK PSD Module: uPSD33XX DECODE PLD AND-OR ARRAY FS0-7 AAAAAAAA BBBBBBBB C C C C TO PLD INPUT BUS PORT C PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 JTAG-ISP TO ALL AREAS OF PSD MODULE ADDR, DATA, CONTROL BUS LINKED TO 8032 MCU RUNTIME CONTROL, 256 REGs GPIO, VM, PAGE POWER MNGMT CSIOP PLD CSBOOT0-3 EXTERNAL CHIPSELECTS MAIN FLASH MEMORY Up to 8 SEGMENTS FS0 Up to 256 KBytes TOTAL FS7 2nd FLASH MEMORY Up to 4 SEGMENTS Up to 32 KBytes TOTAL CSBOOT0 CSBOOT3 DATA ADDRESS LATCH LOW ADDR HIGH ADDR 8032 MUX ADDR/DATA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 8032 HI ADDR A8 A9 A10 A11 A12 A13 A14 A15 8032 CNTL RD WR PSEN ALE RST 8032 MCU Module PORT A (80-pin only) TO JTAG DEBUG ON MCU GPIO PLD GPIO GPIO GPIO 8 PIN INPUTS MCU READ or WRITE MCU READ PLD OUT PLD OUT PLD OUT PLD OUT PLD OUT JTAG CNTL 8 PIN INPUTS 4 PIN INPUTS MCU READ or WRITE RS0 Up to 32 KBytes SRAM PAGE REG JTAG OMC ALLOCATOR AND-OR ARRAY 69 INPUTS 69 INPUTS AI07872B PLD INPUT BUSuPSD33xx 134/231 PSD Module Functional Description Major functional blocks are shown in Figure 51., page 133. The next sections describe each major block. 8032 Address/Data/Control Interface. These signals attach directly to the MCU Module to implement a typical multiplexed 8051-style bus between the two stacked die. The MCU instruction prefetch and branch cache logic resides on the MCU Module, leaving a standard 8051-style memory interface on the PSD Module. The active-low reset signal originating from the MCU Module goes to the PSD Module reset input (RST). This reset signal can then be routed as an external output from the uPSD33xx to the system PC board, if needed, through any one of the PLD output pins as active-high or active-low logic by specifying logic equations in PSDsoft Express. The 8032 address and data busses are routed throughout the PSD Module as shown in Figure 51 connecting many elements on the PSD Module to the 8032 MCU. The 8032 bus is not only connected to the memories, but also to the General PLD, making it possible for the 8032 to directly read and write individual logic macrocells inside the General PLD. Dual Flash Memories and IAP. uPSD33xx devices contain two independent Flash memory arrays. This means that the 8032 can read instructions from one Flash memory array while erasing or writing the other Flash memory array. Concurrent operation like this enables robust remote updates of firmware, also known as In-Application Programming (IAP). IAP can occur using any uPSD33xx interface (e.g., UART, I2C, SPI). Concurrent memory operation also enables the designer to emulate EEPROM memory within either of the two Flash memory arrays for small data sets that have frequent updates. The 8032 can erase Flash memories by individual sectors or it can erase an entire Flash memory array at one time. Each sector in either Flash memory may be individually write protected, blocking any WRITEs from the 8032 (good for boot and start-up code protection). The Flash memories automatically go to standby between 8032 READ or WRITE accesses to conserve power. Minimum erase cycles is 100K and minimum data retention is 15 years. Flash memory, as well as the entire PSD Module may be programmed with the JTAG In-System Programming (ISP) interface with no 8032 involvement, good for manufacturing and lab development. Main Flash Memory. The Main Flash memory is divided into equal sized sectors that are individually selectable by the Decode PLD output signals, named FSx, one signal for each Main Flash memory sector. Each Flash sector can be located at any address within 8032 program address space (accessed with PSEN) or data address space, also known as 8032 XDATA space (accessed with RD or WR), as defined with the software development tool, PSDsoft Express. The user only has to specify an address range for each segment and specify if Main Flash memory will reside in 8032 data or program address space, and then PSEN, RD, or WR are automatically activated for the specified range. 8032 firmware is easily programmed into Main Flash memory using PSDsoft Express or other software tools. See Table 75., page 135 for Main Flash sector sizes on the various uPSD33xx devices. Secondary Flash Memory. The smaller Secondary Flash memory is also divided into equal sized sectors that are individually selectable by the Decode PLD signals, named CSBOOTx, one signal for each Secondary Flash memory sector. Each sector can be located at any address within 8032 program address space (accessed with PSEN) or XDATA space (accessed with RD or WR) as defined with PSDsoft Express. The user only has to specify an address range for each segment, and specify if Secondary Flash memory will reside in 8032 data or program address space, and then PSEN, RD, or WR are automatically activated for the specified range. 8032 firmware is easily programmed into Secondary Flash memory using PSDsoft Express and others. See Table 75., page 135 for Secondary Flash sector sizes. SRAM. The SRAM is selected by a single signal, named RS0, from the Decode PLD. SRAM may be located at any address within 8032 XDATA space (accessed with RD or WR), or optionally within 8032 program address space (accessed with PSEN) to execute code from SRAM. The default setting places SRAM in XDATA space only. These choices are specified using PSDSoft Express, where the user specifies an SRAM address range. The user would also specify (at run-time) if SRAM will additionally reside in 8032 program address space, and then PSEN, RD, or WR are automatically activated for the specified range. See Table 75., page 135 for SRAM sizes. The SRAM may optionally be backed up by an external battery (or other DC source) to make its contents non-volatile (see SRAM Standby Mode (battery backup), page 193).135/231 uPSD33xx Table 75. uPSD33xx Memory Configuration Runtime Control Registers, CSIOP. A block of 256 bytes is decoded inside the PSD Module for module control and status (see Table 79., page 145). The base address of these 256 locations is referred to in this data sheet as csiop (Chip Select I/O Port), and is selected by the Decode PLD output signal, CSIOP. The csiop registers are always viewed by the 8032 as XDATA, and are accessed with RD and WR signals. The address range of CSIOP is specified using PSDsoft Express where the user only has to specify an address range of 256 bytes, and then the RD or WR signals are automatically activated for the specified range. Individual registers within this block are accessed with an offset from the specified csiop base address. 39 registers are used out of the 256 locations to control the output state of I/ O pins, to read I/O pins, to set the memory page, to control 8032 program and data address space, to control power management, to READ/WRITE macrocells inside the General PLD, and other functions during runtime. Unused locations within csiop are reserved and should not be accessed. Memory Page Register. 8032 MCU architecture has an inherent size limit of 64K bytes in either program address space or XDATA space. Some uPSD33xx devices have much more memory that 64K, so special logic such as this page register is needed to access the extra memory. This 8-bit page register (Figure 52) can be loaded and read by the 8032 at runtime as one of the csiop registers. Page register outputs feed directly into both PLDs creating extended address signals used to “page” memory beyond the 64K byte limit (program space or XDATA). Most 8051 compilers directly support memory paging, also known as memory banking. If memory paging is not needed, or if not all eight page register bits are needed for memory paging, the remaining bits may be used in the General PLD for general logic. Page Register outputs are cleared to logic ’0’ at reset and powerup. Programmable Logic (PLDs) . The uPSD33xx contains two PLDs (Figure 63., page 157) that may optionally run in Turbo or Non-Turbo mode. PLDs operate faster (less propagation delay) while in Turbo mode but consume more power than in Non-Turbo mode. Non-Turbo mode allows the PLDs to go to standby automatically when no PLD inputs are changing to conserve power. The logic configuration (from equations) of both PLDs is stored with non-volatile Flash technology and the logic is active upon power-up. PLDs may NOT be programmed by the 8032, PLD programming only occurs through the JTAG interface. Figure 52. Memory Page Register Device Main Flash Memory Secondary Flash Memory SRAM Total Flash Size (bytes) Individual Sector Size (bytes) Number of Sectors (Sector Select Signal) Total Flash Size (bytes) Individual Sector Size (bytes) Number of Sectors (Sector Select Signal) SRAM Size (bytes) uPSD3312 64K 16K 4 (FS0-3) 16K 8K 2 (CSBOOT0-1) 2K uPSD3333 128K 16K 8 (FS0-7) 32K 8K 4 (CSBOOT0-3) 8K uPSD3334 256K 32K 8 (FS0-7) 32K 8K 4 (CSBOOT0-3) 8K uPSD3354 256K 32K 8 (FS0-7) 32K 8K 4 (CSBOOT0-3) 32K 8032 Data Bus Load or Read via csiop + offset E0h D0 D7 D6 D5 D4 D3 D2 D1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 DPLD and GPLD Page Register ChipSelects and General Logic RST (PSD Module Reset) RST PGR0-7 AI09172uPSD33xx 136/231 PLD #1, Decode PLD (DPLD). This programmable logic implements memory mapping and is used to select one of the individual Main Flash memory segments, one of individual Secondary Flash memory segments, the SRAM, or the group of csiop registers when the 8032 presents an address to DPLD inputs (see Figure 64., page 159). The DPLD can also optionally drive external chip select signals on Port D pins. The DPLD also optionally produces two select signals (PSEL0 and PSEL1) used to enable a special data bus repeater function on Port A, referred to as Peripheral I/O Mode. There are 69 DPLD input signals which include: 8032 address and control signals, Page Register outputs, PSD Module Port pin inputs, and GPLD logic feedback. PLD #2, General PLD (GPLD). This programmable logic is used to create both combinatorial and sequential general purpose logic (see Figure 65., page 161). The GPLD contains 16 Output Macrocells (OMCs) and 20 Input Macrocells (IMCs). Output Macrocell registers are unique in that they have direct connection to the 8032 data bus allowing them to be loaded and read directly by the 8032 at runtime through OMC registers in csiop. This direct access is good for making small peripheral devices (shifters, counters, state machines, etc.) that are accessed directly by the 8032 with little overhead. There are 69 GPLD inputs which include: 8032 address and control signals, Page Register outputs, PSD Module Port pin inputs, and GPLD feedback. OMCs. There are two banks of eight OMCs inside the GPLD, MCELLAB, and MCELLBC, totalling 16 OMCs all together. Each individual OMC is a base logic element consisting of a flip-flop and some AND-OR logic (Figure 66., page 162). The general structure of the GPLD with OMCs is similar in nature to a 22V10 PLD device with the familiar sum-of-products (AND-OR) construct. True and compliment versions of 69 input signals are available to the inputs of a large AND-OR array. ANDOR array outputs feed into an OR gate within each OMC, creating up to 10 product-terms for each OMC. Logic output of the OR gate can be passed on as combinatorial logic or combined with a flipflop within in each OMC to realize sequential logic. OMC outputs can be used as a buried nodes driving internal feedback to the AND-OR array, or OMC outputs can be routed to external pins on Ports A, B, or C through the OMC Allocator. OMC Allocator. The OMC allocator (Figure 67., page 163) will route eight of the OMCs from MCELLAB to pins on either Port A or Port B, and will route eight of the OMCs from MCELLBC to pins on either Port B or Port C, based on what is specified in PSDsoft Express. IMCs. Inputs from pins on Ports A, B, and C are routed to IMCs for conditioning (clocking or latching) as they enter the chip, which is good for sampling and debouncing inputs. Alternatively, IMCs can pass port input signals directly to PLD inputs without clocking or latching (Figure 68., page 167). The 8032 may read the IMCs asynchronously at any time through IMC registers in csiop. Note: The JTAG signals TDO, TDI, TCK, and TMS on Port C do not route through IMCs, but go directly to JTAG logic. I/O Ports. For 80-pin uPSD33xx devices, the PSD Module has 22 individually configurable I/O pins distributed over four ports (these I/O are in addition to I/O on MCU Module). For 52-pin uPSD33xx devices, the PSD Module has 13 individually configurable I/O pins distributed over three ports. See Figure 74., page 181 for I/O port pin availability on these two packages. I/O port pins on the PSD Module (Ports A, B, C, and D) are completely separate from the port pins on the MCU Module (Ports 1, 3, and 4). They even have different electrical characteristics. I/O port pins on the PSD Module are accessed by csiop registers, or they are controlled by PLD equations. Conversely, I/O Port pins on the MCU Module are controlled by the 8032 SFR registers. Table 76. General I/O pins on PSD Module Note: Four pins on Port C are dedicated to JTAG, leaving four pins for general I/O. Pkg Port A Port B Port D Port D Total 52-pin 0 8 4 1 13 80-pin 8 8 4 2 22137/231 uPSD33xx Each I/O pin on the PSD Module can be individually configured for different functions on a pin-bypin basis (Figure 69., page 169). Following are the available functions on PSD Module I/O pins. – MCU I/O: 8032 controls the output state of each port pin or it reads input state of each port pin, by accessing csiop registers at runtime. The direction (in or out) of each pin is also controlled by csiop registers at run-time. – PLD I/O: PSDsoft Express logic equations and pin configuration selections determine if pins are connected to OMC outputs or IMC inputs. This is a static and non-volatile configuration. Port pins connected to PLD outputs can no longer be driven by the 8032 using MCU I/O output mode. – Latched MCU Address Output: Port A or Port B can output de-multiplexed 8032 address signals A0 - A7 on a pin-by-pin basis as specified in csiop registers at run-time. In addition, Port B can also be configured to output de-multiplexed A8-A15 in PSDsoft Express. – Data Bus Repeater: Port A can bidirectionally buffer the 8032 data bus (demultiplexed) for a specified address range in PSDsoft Express. This is referred to as Peripheral I/O Mode in this document. – Open Drain Outputs: Some port pins can function as open-drain as specified in csiop registers at run-time. – Pins on Port D can be used for external chipselect outputs originating from the DPLD, without consuming OMC resources within the GPLD. JTAG Port. In-System Programming (ISP) can be performed through the JTAG signals on Port C. This serial interface allows programming of the entire PSD Module device or subsections of the PSD Module (for example, only Flash memory but not the PLDs) without the participation of the 8032. A blank uPSD33xx device soldered to a circuit board can be completely programmed in 10 to 25 seconds. The four basic JTAG signals on Port C; TMS, TCK, TDI, and TDO form the IEEE-1149.1 interface. The PSD Module does not implement the IEEE-1149.1 Boundary Scan functions, but uses the JTAG interface for ISP an 8032 debug. The PSD Module can reside in a standard JTAG chain with other JTAG devices and it will remain in BYPASS mode when other devices perform JTAG functions. ISP programming time can be reduced as much as 30% by using two optional JTAG signals on Port C, TSTAT and TERR, in addition to TMS, TCK, TDI and TDO, and this is referred to as “6-pin JTAG”. The FlashLINK JTAG programming cable is available from STMicroelectronics and PSDsoft Express software is available at no charge from www.st.com/psm. More JTAG ISP information maybe found in the section titled “JTAG ISP and Debug” on page 137. The MCU module is also included in the JTAG chain within the uPSD33xx device for 8032 debugging and emulation. While debugging, the PSD Module is in BYPASS mode. Conversely, during ISP, the MCU Module is in BYPASS mode. Power Management. The PSD Module has bits in csiop registers that are configured at run-time by the 8032 to reduce power consumption of the GPLD. The Turbo Bit in the PMMR0 Register can be set to logic ’1’ and both PLDs will go to NonTurbo mode, meaning it will latch its outputs and go to sleep until the next transition on its inputs. There is a slight penalty in PLD performance (longer propagation delay), but significant power savings are realized. Going to Non-Turbo mode may require an additional wait state in the 8032 SFR, BUSCON, because memory decode signals are also delayed. The default state of the Turbo Bit is logic '0,' meaning by default, the GPLD is in fast Turbo mode until the Turbo mode is turned off. Additionally, bits in csiop registers PMMR0 and PMMR2 can be set by the 8032 to selectively block signals from entering both PLDs which further reduces power consumption. There is also an Automatic Power Down counter that detects lack of 8032 activity and reduces power consumption on the PSD Module to its lowest level (see Power Management, page 137).uPSD33xx 138/231 Security and NVM Sector Protection. A programmable security bit in the PSD Module protects its contents from unauthorized viewing and copying. The security bit is specified in PSDsoft Express and programmed into the uPSD33xx with JTAG. Once set, the security bit will block access of JTAG programming equipment to the PSD Module Flash memory and PLD configuration, and also blocks JTAG debugging access to the MCU Module. The only way to defeat the security bit is to erase the entire PSD Module using JTAG (the erase command is the only JTAG command allowed after the security bit has been set), after which the device is blank and may be used again. Additionally and independently, the contents of each individual Flash memory sector can be write protected (sector protection) by configuration with PSDsoft Express. This is typically used to protect 8032 boot code from being corrupted by inadvertent WRITEs to Flash memory from the 8032. Status of sector protection bits may be read (but not written) using two registers in csiop space. Memory Mapping There many different ways to place (or map) the address range of PSD Module memory and I/O depending on system requirements. The DPLD provides complete mapping flexibility. Figure 53 shows one possible system memory map. In this example, 128K bytes of Main Flash memory for a uPSD3333 device is in 8032 program address space, and 32K bytes of Secondary Flash memory, the SRAM, and csiop registers are all in 8032 XDATA space. In Figure 53, the nomenclature fs0..fs7 are designators for the individual sectors of Main Flash memory, 16K bytes each. CSBOOT0..CSBOOT3 are designators for the individual Secondary Flash memory segments, 8K bytes each. rs0 is the designator for SRAM, and csiop designates the PSD Module control register set. The designer may easily specify memory mapping in a point-and-click software environment using PSDsoft Express, creating a non-volatile configuration when the DPLD is programmed using JTAG. 8032 Program Address Space. In the example of Figure 53, six sectors of Main Flash memory (fs2.. fs7) are paged across three memory pages in the upper half of program address space, and the remaining two sectors of Main Flash memory (fs0, fs1) reside in the lower half of program address space, and these two sectors are independent of paging (they reside in “common” program address space). This paged memory example is quite common and supported by many 8051 software compilers. 8032 Data Address Space (XDATA). Four sectors of Secondary Flash memory reside in the upper half of 8032 XDATA space in the example of Figure 53. SRAM and csiop registers are in the lower half of XDATA space. The 8032 SFR registers and local SRAM inside the 8032 MCU Module do not reside in XDATA space, so it is OK to place PSD Module SRAM or csiop registers at an address that overlaps the address of internal 8032 MCU Module SRAM and registers. Figure 53. Typical System Memory Map 0000h 8000h A000h C000h E000h FFFFh 8032 XDATA SPACE (RD and WR) 8032 PROGRAM SPACE (PSEN) csboot0 8KB csboot1 8KB csboot2 8KB csboot3 8KB Page X fs0, 16KB Common Memory to All Pages fs7 16KB fs5 16KB fs3 16KB rs0, 8KB Page 0 Page 2 Page 1 2000h 0000h 8000h FFFFh System I/O fs6 16KB fs4 16KB fs2 16KB fs1, 16KB Common Memory to All Pages C000h 4000h csiop 256B AI09173139/231 uPSD33xx Specifying the Memory Map with PSDsoft Express. The memory map example shown in FieuPSD33xx 140/231 EEPROM Emulation. EEPROM emulation is needed if it is desired to repeatedly change only a small number of bytes of data in Flash memory. In this case EEPROM emulation is needed because although Flash memory can be written byte-bybyte, it must be erased sector-by-sector, it is not erasable byte-by-byte (unlike EEPROM which is written AND erased byte-by-byte). So changing one or two bytes in Flash memory typically requires erasing an entire sector each time only one byte is changed within that sector. However, two of the 8K byte sectors of Secondary Flash memory may be used to emulate EEPROM by using a linked-list software technique to create a small data set that is maintained by alternating between the two flash sectors. For example, a data set of 128 bytes is written and maintained by software in a distributed fashion across one 8K byte sector of Secondary Flash memory until it becomes full. Then the writing continues on the other 8K byte sector while erasing the first 8K byte sector. This process repeats continuously, bouncing back and forth between the two 8K byte sectors. This creates a wear-leveling effect, which increases the effective number of erase cycles for a data set of 128 bytes to many times more than the base 100K erase cycles of the Flash memory. EEPROM emulation in Flash memory is typically faster than writing to actual EEPROM memory, and more reliable because the last known value in a data set is maintained even if a WRITE cycle is corrupted by a power outage. The EEPROM emulation function can be called by the firmware, making it appear that the user is writing a single byte, or data record, thus hiding all of the data management that occurs within the two 8K byte flash sectors. EEPROM emulation firmware for the uPSD33xx is available from www.st.com/psm. Alternative Mapping Schemes. Here are more possible memory maps for the uPSD3333. Note: Mapping examples would be slightly different for uPSD3312, uPSD3334, and uPSD3354 because of the different sizes of individual Flash memory sectors and SRAM as defined in Table 82., page 155. – Figure 55. Place the larger Main Flash Memory into program space, but split the Secondary Flash in half, placing two of it’s sectors into XDATA space and remaining two sectors into program space. This method allows the designer to put IAP code (or boot code) into two sectors of Secondary Flash in program space, and use the other two Secondary Flash sectors for data storage, such as EEPROM emulation in XDATA space. – Figure 56. Place both the Main and Secondary Flash memories into program space for maximum code storage, with no Flash memory in XDATA space. Figure 55. Mapping: Split Second Flash in Half Figure 56. Mapping: All Flash in Code Space 0000h 8000h 4000h 6000h FFFFh 8032 XDATA SPACE (RD and WR) 8032 PROGRAM SPACE (PSEN) csboot1, 8KB Common Memory to All Pages csboot0, 8KB Common Memory to All Pages csboot2 8KB csboot3 8KB Page X rs0, 8KB csiop, 256B fs7 16KB fs3 16KB fs1 16KB Page 0 Page 1 Page 2 Page 3 2000h 0000h 8000h FFFFh Nothing Mapped fs6 16KB fs5 16KB fs4 16KB fs2 16KB fs0 16KB System I/O System I/O C000h 2100h 4000h 2000h AI09174 0000h 8000h 4000h 6000h FFFFh 8032 XDATA SPACE (RD and WR) 8032 PROGRAM SPACE (PSEN) csboot1, 8KB Common Memory to All Pages csboot0, 8KB Common Memory to All Pages csboot2, 8KB Common Memory to All Pages csboot3, 8KB Common Memory to All Pages Page X rs0, 8KB csiop, 256B fs7 16KB fs3 16KB fs1 16KB Page 0 Page 1 Page 2 Page 3 2000h 0000h FFFFh fs6 16KB fs5 16KB fs4 16KB fs2 16KB fs0 16KB System I/O C000h 2100h 2000h AI09175141/231 uPSD33xx – Figure 57. Place the larger Main Flash Memory into XDATA space and the smaller Secondary Flash into program space for systems that need a large amount of Flash for data recording or large look-up tables, and not so much Flash for 8032 firmware. Figure 57. Mapping: Small Code / Big Data It is also possible to “reclassify” the Flash memories during runtime, moving the memories between XDATA memory space and program memory space on-the-fly. This essentially means that the user can override the initial setting during run-time by writing to a csiop register (the VM Register). This is useful for IAP, because standard 8051 architecture does not allow writing to program space. For example, if the user wants to update firmware in Main Flash memory that is residing in program space, the user can temporarily “reclassify” the Main Flash memory into XDATA space to erase and rewrite it while executing IAP code from the Secondary Flash memory in program space. After the writing is complete, the Main Flash can be “reclassified” back to program space, then execution can continue from the new code in Main Flash memory. The mapping example of Figure 57 will accommodate this operation. Memory Sector Select Rules. When defining sector select signals (FSx, CSBOOTx, RS0, CSIOP, PSELx) in PSDsoft Express, keep these rules in mind: – Main Flash and Secondary Flash memory sector select signals may not be larger than their physical sector size as defined in Table 75., page 135. – Any Main Flash memory sector select may not be mapped in the same address range as another Main Flash sector select (cannot overlap segments of Main Flash on top of each other). – Any Secondary Flash memory sector select may not be mapped in the same address range as another Secondary Flash sector select (cannot overlap segments of Secondary Flash on top of each other). – A Secondary Flash memory sector may overlap a Main Flash memory sector. In the case of overlap, priority is given to the Secondary Flash memory sector. – SRAM, CSIOP, or PSELx may overlap any Flash memory sector. In the case of overlap, priority is given to SRAM, CSIOP, or PSELx. Note: PSELx is for optional Peripheral I/O Mode on Port A. – The address range for sector selects for SRAM, PSELx, and CSIOP must not overlap each other as they have the same priority, causing contention if overlapped. 0000h 8000h 4000h 6000h FFFFh 8032 XDATA SPACE (RD and WR) 8032 PROGRAM SPACE (PSEN) csboot0 8KB csboot1 8KB csboot2 8KB csboot3 8KB Page X rs0, 8KB Common Memory to All Pages csiop, 256 bytes, Common to All Pages fs7 16KB fs3 16KB fs1 16KB Page 0 Page 1 Page 2 Page 3 2000h 0000h 8000h FFFFh Nothing Mapped fs6 16KB fs5 16KB fs4 16KB fs2 16KB fs0 16KB System I/O C000h 2100h 2000h AI09176uPSD33xx 142/231 Figure 58 illustrates the priority scheme of the memory elements of the PSD Module. Priority refers to which memory will ultimately produce a byte of data or code to the 8032 MCU for a given bus cycle. Any memory on a higher level can overlap and has priority over any memory on a lower level. Memories on the same level must not overlap. Example: FS0 is valid when the 8032 produces an address in the range of 8000h to BFFFh. CSBOOT0 is valid from 8000h to 9FFFh. RS0 is valid from 8000h to 87FFh. Any address from the 8032 in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses Secondary Flash memory. Any address greater than 9FFFh accesses Main Flash memory. One-half of the Main Flash memory segment, and one-fourth of the Secondary Flash memory segment cannot be accessed by the 8032 in this example. Figure 58. PSD Module Memory Priority The VM Register. One of the csiop registers (the VM Register) controls whether or not the 8032 bus control signals RD, WR, and PSEN are routed to the Main Flash memory, the Secondary Flash memory, or the SRAM. Routing of these signals to these PSM Module memories determines if memories reside in 8032 program address space, 8032 XDATA space, or both. The initial setting of the VM Register is determined by a choice in PSDsoft Express and programmed into the uPSD33xx in a non-volatile fashion using JTAG. This initial setting is loaded into the VM Register upon power-up and also loaded upon any reset event. However, the 8032 may override the initial VM Register setting at run-time by writing to the VM Register, which is useful for IAP. Table 78., page 143 defines bit functions within the VM Register. Note: Bit 7, PIO_EN, is not related to the memory manipulation functions of Bits 0, 1, 2, 3, and 4. Also note that SRAM must at least always be in 8032 XDATA space (default condition). Bit 0 allows the user to optionally place SRAM into 8032 program space in addition to XDATA space. CSIOP registers are always in XDATA space and cannot reside in program space. Figure 59., page 144 illustrates how the VM Register affects the routing of RD, WR, and PSEN to the memories on the PSD Module. As an example, if we apply the value 0Ch to the VM Register to implement the memory map example shown in Figure 53., page 138, then the routing of RD, WR, and PSEN would look like that shown in Figure 60., page 145. In this example, the configuration is specified in PSDsoft Express and programmed into the uPSD33xx using JTAG. Upon power-on or any reset condition, the non-volatile value 0Ch is loaded into the VM Register. At runtime, the value 0Ch in the VM Register may be changed (overridden) by the 8032 if desired to implement IAP or other functions. Level 1 SRAM, CSIOP, and Peripheral I/O Mode Highest Priority Level 2 Secondary Flash Memory Level 3 Main Flash Memory Lowest Priority AI02867E143/231 uPSD33xx Table 78. VM Register (address = csiop + offset E2h) Note: 1. Default value of Bits 0, 1, 2, 3, and 4 is loaded from Non-Volatile setting as specified from PSDsoft Express upon any reset or powerup condition. The default value of these bits can be overridden by 8032 at run-time. 2. Default value of Bit 7 is zero upon any reset condition. Bit 7 PIO_EN Bit 6 Bit 5 Bit 4 Main Flash XDATA Space Bit 3 Secondary Flash XDATA Space Bit 2 Main Flash Program Space Bit 1 Secondary Flash Program Space Bit 0 SRAM Program Space 0 = disable Peripheral I/O Mode on Port A not used not used 0 = RD or WR cannot access Main Flash 0 = RD or WR cannot access Secondary Flash 0 = PSEN cannot access Main Flash 0 = PSEN cannot access Secondary Flash 0 = PSEN cannot access SRAM 1 = enable Peripheral I/O Mode on Port A not used not used 1 = RD or WR can access Main Flash 1 = RD or WR can access Secondary Flash 1 = PSEN can access Main Flash 1 = PSEN can access Secondary Flash 1 = PSEN can access SRAMuPSD33xx 144/231 Figure 59. VM Register Control of Memories DPLD Main Flash Memory Secondary Flash Memory SRAM CS CS CS FS0 - FS7 CSBOOT0 - CSBOOT3 RS0 WR VM REG BIT 4 VM REG BIT 3145/231 uPSD33xx Figure 60. VM Register Example Corresponding to Memory Map Example of Figure 33 Runtime Control Register Definitions (csiop) The 39 csiop registers are defined in Table 79. The 8032 can access each register by the address offset (specified in Table 79) added to the csiop base address that was specified in PSDsoft Express. Do not write to unused locations within the csiop block of 256 registers, they should remain logic zero. Table 79. CSIOP Registers and their Offsets (in hexadecimal) DPLD Main Flash Memory Secondary Flash Memory SRAM CS CS CS FS0 - FS7 CSBOOT0 - CSBOOT3 RS0 WR OE WR OE WR OE 8032 Address 53 Other PLD Inputs WR PSEN RD VM Register = 0Ch AI02869D Register Name Port A (80-pin) Port B Port C Port D Other Description Link Data In 00h 01h 10h 11h MCU I/O input mode. Read to obtain current logic level of pins on Ports A, B, C, or D. No WRITEs. Table 95., page 172 Control 02h 03h Selects MCUI/O or Latched Address Out mode. Logic 0 = MCU I/O, 1 = 8032 Addr Out. Write to select mode. Read for status. Table 107., page 177 Data Out 04h 05h 12h 13h MCU I/O output mode. Write to set logic level on pins of Ports A, B, C, or D. Read to check status. This register has no effect if a port pin is driven by an OMC output from PLD. Table 99., page 172 Direction 06h 07h 14h 15h MCU I/O mode. Configures port pin as input or output. Write to set direction of port pins. Logic 1 = out, Logic 0 = in. Read to check status. Table 103., page 173 Drive Select 08h 09h 16h 17h Write to configure port pins as either CMOS push-pull or Open Drain on some pins, while selecting high slew rate on other pins. Read to check status. Default output type is CMOS push-pull. Table 109., page 179uPSD33xx 146/231 Input Macrocells 0Ah 0Bh 18h Read to obtain logic state of IMCs. No WRITEs. Table 90., page 167 Enable Out OCh 0Dh 1Ah 1Bh Read state of output enable logic on each I/O port driver. 1 = driver output is enabled, 0 = driver is off, and it is in high impedance state. No WRITEs. Table 113., page 180 Output Macrocells AB (MCELLAB) 20h Read logic state of MCELLAB outputs (bank of eight OMCs). Write to load MCELLAB flip-flops. Table 86., page 165 Output Macrocells BC (MCELLBC) 21h Read logic state of MCELLBC outputs (bank of eight OMCs). Write to load MCELLBC flip-flops. Table 87., page 165 Mask Macrocells AB 22h Write to set mask for MCELLAB. Logic '1' blocks READs/WRITEs of OMC. Logic '0' will pass OMC value. Read to check status. Table 88., page 166 Mask Macrocells BC 23h Write to set mask for MCELLBC. Logic '1' blocks READs/WRITEs of OMC. Logic '0' will pass OMC value. Read to check status. Table 89., page 166 Main Flash Sector Protection C0h Read to determine Main Flash Sector Protection Setting (non-volatile) that was specified in PSDsoft Express. No WRITEs. Table 82., page 155 Security Bit and Secondary Flash Sector Protection C2h Read to determine if PSD Module device Security Bit is active (nonvolatile) Logic 1 = device secured. Also read to determine Secondary Flash Protection Setting (non-volatile) that was specified in PSDsoft. No WRITEs. Table 83., page 155 PMMR0 B0h Power Management Register 0. WRITE and READ. Table 117., page 188 PMMR2 B4h Power Management Register 2. WRITE and READ. Table 118., page 188 PMMR3 C7h Power Management Register 3. WRITE and READ. However, Bit 1 can be cleared only by a reset condition. Table 119., page 188 Page E0h Memory Page Register. WRITE and READ. Figure 52., page 135 VM (Virtual Memory) E2h Places PSD Module memories into 8032 Program Address Space and/or 8032 XDATA Address Space. (VM overrides initial non-volatile setting that was specified in PSDsoft Express. Reset restores initial setting) Table 78., page 143 Register Name Port A (80-pin) Port B Port C Port D Other Description Link147/231 uPSD33xx PSD Module Detailed Operation Specific details are given here for the following key functional areas on the PSD Module: ■ Flash Memories ■ PLDs (DPLD and GPLD) ■ I/O Ports ■ Power Management ■ JTAG ISP and Debug Interface Flash Memory Operation. The Flash memories are accessed through the 8032 Address, Data, and Control Bus interfaces. Flash memories (and SRAM) cannot be accessed by any other bus master other than the 8032 MCU (these are not dual-port memories). The 8032 cannot write to Flash memory as it would an SRAM (supply address, supply data, supply WR strobe, assume the data was correctly written to memory). Flash memory must first be “unlocked” with a special instruction sequence of byte WRITE operations to invoke an internal algorithm inside either Flash memory array, then a single data byte is written (programmed) to the Flash memory array, then programming status is checked by a byte READ operation or by checking the Ready/Busy pin (PC3). Table 80., page 148 lists all of the special instruction sequences to program a byte to either of the Flash memory arrays, erase the arrays, and check for different types of status from the arrays. This unlocking sequence is typical for many Flash memories to prevent accidental WRITEs by errant code. However, it is possible to bypass this unlocking sequence to save time while intentionally programming Flash memory. IMPORTANT: The 8032 may not read and execute code from the same Flash memory array for which it is directing an instruction sequence. Or more simply stated, the 8032 may not read code from the same Flash array that is writing or erasing. Instead, the 8032 must execute code from an alternate memory (like SRAM or a different Flash array) while sending instruction sequences to a given Flash array. Since the two Flash memory arrays inside the PSD Module device are completely independent, the 8032 may read code from one array while sending instructions to the other. It is possible, however, to suspend a sector erase operation in one particular Flash array in order to access a different sector within that same Flash array, then resume the erase later. After a Flash memory array is programmed or erased it will go to “Read Array” mode, then the 8032 can read from Flash memory just as it would read from any 8-bit ROM or SRAM device. Flash Memory Instruction Sequences. An instruction sequence consists of a sequence of specific byte WRITE and byte READ operations. Each byte written to either Flash memory array on the PSD Module is received by a state machine inside the Flash array and sequentially decoded to execute an embedded algorithm. The algorithm is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out period of 80µs. Some instruction sequences are structured to include READ operations after the initial WRITE operations. An instruction sequence must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory resets the PSD Module Flash logic into Read Array mode (where Flash memory is read like a ROM device). The Flash memories support instruction sequences summarized in Table 80., page 148. ■ Program a Byte ■ Unlock Sequence Bypass ■ Erase memory by array or by sector ■ Suspend or resume a sector erase ■ Reset to Read Array mode The first two bytes of an instruction sequence are 8032 bus WRITE operations to “unlock” the Flash array, followed by writing a command byte. The bus operations consist of writing the data AAh to address X555h during the first bus cycle and data 55h to address XAAAh during the second bus cycle. 8032 address signals A12-A15 are “Don’t care” during the instruction sequence during WRITE cycles. However, the appropriate sector select signal (FSx or CSBOOTx) from the DPLD must be active during the entire instruction sequence to complete the entire 8032 address (this includes the page number when memory paging is used). Ignoring A12-A15 means the user has more flexibility in memory mapping. For example, in many traditional Flash memories, instruction sequences must be written to addresses AAAAh and 5555h, not XAAAh and X555h like supported on the PSD Module. When AAAAh and 5555h must be written to, the memory mapping options are limited. The Main Flash and Secondary Flash memories each have the same instruction set shown in Table 80., page 148, but the sector select signals determine which memory array will receive and execute the instructions.uPSD33xx 148/231 Table 80. Flash Memory Instruction Sequences(1,2) Instr. Sequence Bus Cycle 1 Bus Cycle 2 Bus Cycle 3 Bus Cycle 4 Bus Cycle 5 Bus Cycle 6 Bus Cycle 7 Link Read Memory Contents (Read Array mode) Read byte from any valid Flash memory addr Read Memory Contents., p age 149 Program (write) a Byte to Flash Memory Write AAh to X555h (unlock) Write 55h to XAAAh (unlock) Write A0h to X555h (command ) Write data byte to address Programmin g Flash Memory., pa ge 150 Bypass Unlock Write AAh to X555h (unlock) Write 55h to XAAAh (unlock) Write 20h to X555h (command ) Bypassed Unlock Sequence, p age 153 Program a Byte to Flash Memory with Bypassed Unlock Write A0h to XXXXh (command) Write data byte to address Bypassed Unlock Sequence, p age 153 Reset Bypass Unlock Write 90h to XXXXh (command) Write 00h to XXXXh (command ) Bypassed Unlock Sequence, p age 153 Flash Bulk Erase(3) Write AAh to X555h (unlock) Write 55h to XAAAh (unlock) Write 80h to X555h (command ) Write AAh to X555h (unlock) Write 55h to XAAAh (unlock) Write 10h to X555h (command) Flash Bulk Erase., page 153 Flash Sector Erase Write AAh to X555h (unlock) Write 55h to XAAAh (unlock) Write 80h to X555h (command ) Write AAh to X555h (unlock) Write 55h to XAAAh (unlock) Write 30h to desired Sector (command) Write 30h to another Sector (command) Flash Sector Erase., page 154 Suspend Sector Erase Write B0h to address that activates FSx or CSBOOTx where erase is in progress (command) Suspend Sector Erase., page 154 Resume Sector Erase Write 30h to address that activates FSx or CSBOOTx where desired to resume erase (command) Resume Sector Erase., page 154149/231 uPSD33xx Note: 1. All values are in hexadecimal, X = Don’t care 2. 8032 addresses A12 through A15 are “Don’t care” during the instruction sequence decoding. Only address bits A0-A11 are used during decoding of Flash memory instruction sequences. The individual sector select signal (FS0 - FS7 or CSBOOT0-CSBOOT3) which is active during the instruction sequence determines the complete address. 3. Directing this command to any individual sector within a Flash memory array will invoke the bulk erase of all Flash memory sectors within that array. Reading Flash Memory. Under typical conditions, the 8032 may read the Flash memory using READ operations (READ bus cycles) just as it would a ROM or RAM device. Alternately, the 8032 may use READ operations to obtain status information about a Program or Erase operation that is currently in progress. The following sections describe the kinds of READ operations. Read Memory Contents. Flash memory is placed in the Read Array mode after Power-up, after a PSD Module reset event, or after receiving a Reset Flash memory instruction sequence from the 8032. The 8032 can read Flash memory contents using standard READ bus cycles anytime the Flash array is in Read Array mode. Flash memories will always be in Read Array mode when the array is not actively engaged in a program or erase operation. Reading the Erase/Program Status Bits. The Flash arrays provide several status bits to be used by the 8032 to confirm the completion of an erase or program operation on Flash memory, shown in Table 81., page 150. The status bits can be read as many times as needed until an operation is complete. The 8032 performs a READ operation to obtain these status bits while an erase or program operation is being executed by the state machine inside each Flash memory array. Data Polling Flag (DQ7). While programming either Flash memory, the 8032 may read the Data Polling Flag Bit (DQ7), which outputs the com1.24Is0.6(2(i)8.4(3(n)]TJl)8.1(e21.5(n)-23.8(0.9(m3.5o)-23.8(f.9(m3.5)-7.23659 16.9(p)D72(g)-0)]TJ 8as)-77.236 of77.236 0.9(m3.h)-23.8(e16.9(6.5(-77.236e21.5([(at).8(r)2-23.8(g21.5([i)-16.2(l)8)17.4(o)-36e21.5(d)24.4(o)]TJ -1-9.097623.8(r)21.5(-77.236o21.5([-1.08TD 0.00)-23.56-6.8(h )236e21.5(8(h )236o21.5(r.9(6.5(..9(m3.5Onc9(6.5(e21.5([)-7.23659 i)-16.2(l)8)17 as)-6.5(e))-23.8(ro9(o)0.1p)-24.3(o)-24.2(f)14.9(08)]TJ 0 b)-8op)-23.6( on )2p.3(as3(eded124.4(F)t)9.5(ee)-23.6(m)9.5(e)D1(i)c)177(o)0.8(0.8(m)- equaat)-8. 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Error Flag (DQ5). During a normal program or erase operation, the Error Flag Bit (DQ5) is to ’0’. This bit is set to ’1’ when there is a failure during Flash memory byte program, sector erase, or bulk erase operations. In the case of Flash memory programming, DQ5 Bit indicates an attempt to program a Flash memory bit from the programmed state of 0, to the erased state of 1, which is not valid. DQ5 may also indicate a particular Flash cell is damaged and cannot be programmed. In case of an error in a Flash memory sector erase or byte program operation, the Flash memory sector in which the error occurred or to which the programmed byte belongs must no longer be used. Other Flash memory sectors may still be used. DQ5 is reset after a Reset Flash instruction sequence. Erase Time-out Flag (DQ3). The Erase Timeout Flag Bit (DQ3) reflects the time-out period allowed between two consecutive sector erase instruction sequence bytes. If multiple sector erase commands are desired, the additional sector erase commands (30h) must be sent by the 8032 within 80us after the previous sector erase command. DQ3 is 0 before this time period has expired, indicating it is OK to issue additional sector erase commands. DQ3 will go to logic ’1’ if the time has been longer than 80µs since the previous sector erase command (time has expired), indication that is not OK to send another sector erase command. In this case, the 8032 must start a new sector erase instruction sequence (unlock and command) beginning again after the current sector erase operation has completed. Programming Flash Memory. When a byte of Flash memory is programmed, individual bits are programmed to logic '0.' The user cannot program a bit in Flash memory to a logic ’1’ once it has been programmed to a logic '0.' A bit must be erased to logic ’1’, and programmed to logic '0.' That means Flash memory must be erased prior to being programmed. A byte of Flash memory is erased to all 1s (FFh). The 8032 may erase the entire Flash memory array all at once, or erase individual sector-by-sector, but not erase byte-by-byte. However, even though the Flash memories cannot be erased byte-by-byte, the 8032 may program Flash memory byte-by-byte. This means the 8032 does not need to program group of bytes (64, 128, etc.) at one time, like some Flash memories. Each Flash memory requires the 8032 to send an instruction sequence to program a byte or to erase sectors (see Table 80., page 148). If the byte to be programmed is in a protected Flash memory sector, the instruction sequence is ignored. IMPORTANT: It is mandatory that a chip-select signal is active for the Flash sector where a programming instruction sequence is targeted. Make sure that the correct chip-select equation, FSx, or CSBOOTx specified in PSDsoft Express matches the address range that the 8032 firmware is accessing, otherwise the instruction sequence will not be recognized by the Flash array. If memory paging is used, be sure that the 8032 firmware sets the page register to the correct page number before issuing an instruction sequence to the Flash memory segment on a particular memory page, otherwise the correct sector select signal will not become active. Once the 8032 issues a Flash memory program or erase instruction sequence, it must check the status bits for completion. The embedded algorithms that are invoked inside a Flash memory array provide several ways to give status to the 8032. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (pin PC3). Table 81. Flash Memory Status Bit Definition Note: 1. X = Not guaranteed value, can be read either '1' or '0.' 2. DQ7-DQ0 represent the 8032 Data Bus Bits, D7-D0. Functional Block FSx, or CSBOOTx DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Flash Memory Active (the desired segment is selected) Data Polling Toggle Flag Error Flag X Erase Timeout XXX151/231 uPSD33xx Data Polling. Polling on the Data Polling Flag Bit (DQ7) is a method of checking whether a program or erase operation is in progress or has completed. Figure 61 shows the Data Polling algorithm. When the 8032 issues a program instruction sequence, the embedded algorithm within the Flash memory array begins. The 8032 then reads the location of the byte to be programmed in Flash memory to check status. The Data Polling Flag Bit (DQ7) of this location becomes the compliment of Bit D7 of the original data byte to be programmed. The 8032 continues to poll this location, comparing the Data Polling Flag Bit (DQ7) and monitoring the Error Flag Bit (DQ5). When the Data Polling Flag Bit (DQ7) matches Bit D7 of the original data, then the embedded algorithm is complete. If the Error Flag Bit (DQ5) is '1,' the 8032 should test the Data Polling Flag Bit (DQ7) again since the Data Polling Flag Bit (DQ7) may have changed simultaneously with the Error Flag Bit (DQ5) (see Figure 61). The Error Flag Bit (DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte (indicating a bad Flash cell) or if the 8032 attempted to program bit to logic ’1’ when that bit was already programmed to logic ’0’ (must erase to achieve logic ’1’). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to the Flash memory with the byte that was intended to be written. When using the Data Polling method during an erase operation, Figure 61 still applies. However, the Data Polling Flag Bit (DQ7) is '0' until the erase operation is complete. A ’1’ on the Error Flag Bit (DQ5) indicates a time-out condition on the Erase cycle, a ’0’ indicates no error. The 8032 can read any location within the sector being erased to get the Data Polling Flag Bit (DQ7) and the Error Flag Bit (DQ5). PSDsoft Express generates ANSI C code functions for implementation of these Data Polling algorithms. Figure 61. Data Polling Flowchart READ DQ5 & DQ7 at VALID ADDRESS START READ DQ7 FAIL PASS AI01369B DQ7 = DATA YES NO YES NO DQ5 = 1 DQ7 = DATA YES NOuPSD33xx 152/231 Data Toggle. Checking the Toggle Flag Bit (DQ6) is another method of determining whether a program or erase operation is in progress or has completed. Figure 62 shows the Data Toggle algorithm. When the 8032 issues a program instruction sequence, the embedded algorithm within the Flash memory array begins. The 8032 then reads the location of the byte to be programmed in Flash memory to check status. The Toggle Flag Bit (DQ6) of this location toggles each time the 8032 reads this location until the embedded algorithm is complete. The 8032 continues to read this location, checking the Toggle Flag Bit (DQ6) and monitoring the Error Flag Bit (DQ5). When the Toggle Flag Bit (DQ6) stops toggling (two consecutive reads yield the same value), then the embedded algorithm is complete. If the Error Flag Bit (DQ5) is '1,' the 8032 should test the Toggle Flag Bit (DQ6) again, since the Toggle Flag Bit (DQ6) may have changed simultaneously with the Error Flag Bit (DQ5) (see Figure 62). The Error Flag Bit (DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte, or if the 8032 attempted to program bit to logic ’1’ when that bit was already programmed to logic ’0’ (must erase to achieve logic ’1’). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to Flash memory with the byte that was intended to be written. When using the Data Toggle method during an erase operation, Figure 62 still applies. the Toggle Flag Bit (DQ6) toggles until the erase operation is complete. A ’1’ on the Error Flag Bit (DQ5) indicates a time-out condition on the Erase cycle, a ’0’ indicates no error. The 8032 can read any location within the sector being erased to get the Toggle Flag Bit (DQ6) and the Error Flag Bit (DQ5). PSDsoft Express generates ANSI C code functions for implementation of these Data Toggling algorithms. Figure 62. Data Toggle Flowchart READ DQ5 & DQ6 START READ DQ6 FAIL PASS AI01370B DQ6 = TOGGLE NO NO YES YES DQ5 = 1 NO YES DQ6 = TOGGLE153/231 uPSD33xx Ready/Busy (PC3). This signal can be used to output the Ready/Busy status of a program or erase operation on either Flash memory. The output on the Ready/Busy pin is a ’0’ (Busy) when either Flash memory array is being written, or when either Flash memory array is being erased. The output is a ’1’ (Ready) when no program or erase operation is in progress. To activate this function on this pin, the user must select the “Ready/Busy” selection in PSDsoft Express when configuring pin PC3. This pin may be polled by the 8032 or used as a 8032 interrupt to indicate when an erase or program operation is complete (requires routing the signal on PC board from PC3 back into a pin on the MCU Module). This signal is also available internally on the PSD Module as an input to both PLDs (without routing a signal externally on PC board) and it’s signal name is “rd_bsy”. The Ready/Busy output can be probed during lab development to check the timing of Flash memory programming in the system at run-time. Bypassed Unlock Sequence. The Bypass Unlock mode allows the 8032 to program bytes in the Flash memories faster than using the standard Flash program instruction sequences because the typical AAh, 55h unlock bus cycles are bypassed for each byte that is programmed. Bypassing the unlock sequence is typically used when the 8032 is intentionally programming a large number of bytes (such as during IAP). After intentional programming is complete, typically the Bypass mode would be disabled, and full protection is back in place to prevent unwanted WRITEs to Flash memory. The Bypass Unlock mode is entered by first initiating two Unlock bus cycles. This is followed by a third WRITE operation containing the Bypass Unlock command, 20h (as shown in Table 80., page 148). The Flash memory array that received that sequence then enters the Bypass Unlock mode. After this, a two bus cycle program operation is all that is required to program a byte in this mode. The first bus cycle in this shortened program instruction sequence contains the Bypassed Unlocked Program command, A0h, to any valid address within the unlocked Flash array. The second bus cycle contains the address and data of the byte to be programmed. Programming status is checked using toggle, polling, or Ready/Busy just as before. Additional data bytes are programmed the same way until this Bypass Unlock mode is exited. To exit Bypass Unlock mode, the system must issue the Reset Bypass Unlock instruction sequence. The first bus cycle of this instruction must write 90h to any valid address within the unlocked Flash Array; the second bus cycle must write 00h to any valid address within the unlocked Flash Array. After this sequence the Flash returns to Read Array mode. During Bypass Unlock Mode, only the Bypassed Unlock Program instruction, or the Reset Bypass Unlock instruction is valid, other instruction will be ignored. Erasing Flash Memory. Flash memory may be erased sector-by-sector, or an entire Flash memory array may be erased with one command (bulk). Flash Bulk Erase. The Flash Bulk Erase instruction sequence uses six WRITE operations followed by a READ operation of the status register, as described in Table 80., page 148. If any byte of the Bulk Erase instruction sequence is wrong, the Bulk Erase instruction sequence aborts and the device is reset to the Read Array mode. The address provided by the 8032 during the Flash Bulk Erase command sequence may select any one of the eight Flash memory sector select signals FSx or one of the four signals CSBOOTx. An erase of the entire Flash memory array will occur in a particular array even though a command was sent to just one of the individual Flash memory sectors within that array. During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7). The Error Flag Bit (DQ5) returns a ’1’ if there has been an erase failure. Details of acquiring the status of the Bulk Erase operation are detailed in the section entitled “Programming Flash Memory., page 150. During a Bulk Erase operation, the Flash memory does not accept any other Flash instruction sequences.uPSD33xx 154/231 Flash Sector Erase. The Sector Erase instruction sequence uses six WRITE operations, as described in Table 80., page 148. Additional Flash Sector Erase commands to other sectors within the same Flash array may be issued by the 8032 if the additional commands are sent within a limited amount of time. The Erase Time-out Flag Bit (DQ3) reflects the time-out period allowed between two consecutive sector erase instruction sequence bytes. If multiple sector erase commands are desired, the additional sector erase commands (30h) must be sent by the 8032 to another sector within 80µs after the previous sector erase command. DQ3 is 0 before this time period has expired, indicating it is OK to issue additional sector erase commands. DQ3 will go to logic ’1’ if the time has been longer than 80µs since the previous sector erase command (time has expired), indicating that is not OK to send another sector erase command. In this case, the 8032 must start a new sector erase instruction sequence (unlock and command), beginning again after the current sector erase operation has completed. During a Sector Erase operation, the memory status may be checked by reading the Error Flag Bit (DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7), as detailed in Reading the Erase/Program Status Bits, page 149. During a Sector Erase operation, a Flash memory accepts only Reset Flash and Suspend Sector Erase instruction sequences. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed. The address provided with the initial Flash Sector Erase command sequence (Table 80., page 148) must select the first desired sector (FSx or CSBOOTx) to erase. Subsequent sector erase commands that are appended within the time-out period must be addressed to other desired segments within the same Flash memory array. Suspend Sector Erase. When a Sector Erase operation is in progress, the Suspend Sector Erase instruction sequence can be used to suspend the operation by writing B0h to any valid address within the Flash array that currently is undergoing an erase operation. This allows reading of data from a different Flash memory sector within the same array after the Erase operation has been suspended. Suspend Sector Erase is accepted only during an Erase operation. There is up to 15µs delay after the Suspend Sector Erase command is accepted and the array goes to Read Array mode. The 8032 will monitor the Toggle Flag Bit (DQ6) to determine when the erase operation has halted and Read Array mode is active. If a Suspend Sector Erase instruction sequence was executed, the following rules apply: – Attempting to read from a Flash memory sector that was being erased outputs invalid data. – Reading from a Flash memory sector that was not being erased is valid. – The Flash memory cannot be programmed, and only responds to Resume Sector Erase and Reset Flash instruction sequences. – If a Reset Flash instruction sequence is received, data in the Flash memory sector that was being erased is invalid. Resume Sector Erase. If a Suspend Sector Erase instruction sequence was previously executed, the erase cycle may be resumed with this instruction sequence. The Resume Sector Erase instruction sequence consists of writing the command 30h to any valid address within the Flash array that was suspended as shown in Table 80., page 148. Reset Flash. The Reset Flash instruction sequence resets the embedded algorithm running on the state machine in the targeted Flash memory (Main or Secondary) and the memory goes into Read Array mode. The Reset Flash instruction consists of one bus WRITE cycle as shown in Table 80., page 148, and it must be executed after any error condition that has occurred during a Flash memory Program or Erase operation. It may take the Flash memory up to 25µs to complete the Reset cycle. The Reset Flash instruction sequence is ignored when it is issued during a Program or Bulk Erase operation. The Reset Flash instruction sequence aborts any on-going Sector Erase operation and returns the Flash memory to Read Array mode within 25µs. Reset Signal Applied to Flash Memory. Whenever the PSD Module receives a reset signal from the MCU Module, any operation that is occurring in either Flash memory array will be aborted and the array(s) will go to Read Array mode. It may take up to 25µs to abort an operation and achieve Read Array mode. A reset from the MCU Module will result from any of these events: an active signal on the uPSD33xx RESET_IN input pin, a watchdog timer time-out, detection of low VCC, or a JTAG debug channel reset event.155/231 uPSD33xx Flash Memory Sector Protection. Each Flash memory sector can be separately protected against program and erase operations. This mode can be activated (or deactivated) by selecting this feature in PSDsoft Express and then programming through the JTAG Port. Sector protection can be selected for individual sectors, and the 8032 cannot override the protection during run-time. The 8032 can read, but not change, sector protection. Any attempt to program or erase a protected Flash memory sector is ignored. The 8032 may read the contents of a Flash sector even when a sector is protected. Sector protection status is not read using Flash memory instruction sequences, but instead this status is read by the 8032 reading two registers within csiop address space shown in Table 82 and Table 83. Flash Memory Protection During Power-Up. Flash memory WRITE operations are automatically prevented while VDD is ramping up until it rises above VLKO voltage threshold at which time Flash memory WRITE operations are allowed. PSD Module Security Bit. A programmable security bit in the PSD Module protects its contents from unauthorized viewing and copying. The security bit is set using PSDsoft Express and programmed into the PSD Module with JTAG. When set, the security bit will block access of JTAG programming equipment from reading or modifying the PSD Module Flash memory and PLD configuration. The security bit also blocks JTAG access to the MCU Module for debugging. The only way to defeat the security bit is to erase the entire PSD Module using JTAG (erase is the only JTAG operation allowed while security bit is set), after which the device is blank and may be used again. The 8032 MCU will always have access to Flash mem-uPSD33xx 156/231 PLDs. The PSD Module contains two PLDs: the Decode PLD (DPLD), and the General PLD (GPLD), as shown in Figure 63., page 157. Both PLDs are fed by a common PLD input signal bus, and additionally, the GPLD is connected to the 8032 data bus. PLD logic is specified using PSDsoft Express and programmed into the PSD Module using the JTAG ISP channel. PLD logic is non-volatile and available at power-up. PLDs may not be programmed by the 8032. The PLDs have selectable levels of performance and power consumption. The DPLD performs address decoding, and generates select signals for internal and external components, such as memory, registers, and I/O ports. The DPLD can generate External Chip-Select (ECS1-ECS2) signals on Port D. The GPLD can be used for logic functions, such as loadable counters and shift registers, state machines, encoding and decoding logic. These logic functions can be constructed from a combination of 16 Output Macrocells (OMC), 20 Input Macrocells (IMC), and the AND-OR Array. Routing of the 16 OMCs outputs can be divided between pins on three Ports A, B, or C by the OMC Allocator as shown in Figure 67., page 163. Eight of the 16 OMCs that can be routed to pins on Port A or Port B and are named MCELLAB0- MCELLAB7. The other eight OMCs to be routed to pins on Port B or Port C and are named MCELLBC0-MCELLBC7. This routing depends on the pin number assignments that are specified in PSDsoft Express for “PLD Outputs” in the Pin Definition section. OMC outputs can also be routed internally (not to pins) used as buried nodes to create shifters, counters, etc. The AND-OR Array is used to form product terms. These product terms are configured from the logic definitions entered in PSDsoft Express. A PLD Input Bus consisting of 69 signals is connected to both PLDs. Input signals are shown in Table 84, both the true and compliment versions of each of these signals are available at inputs to each PLD. Note: The 8032 data bus, D0 - D7, does not route directly to PLD inputs. Instead, the 8032 data bus has indirect access to the GPLD (not the DPLD) when the 8032 reads and writes the OMC and IMC registers within csiop address space. Turbo Bit and PLDs. The PLDs can minimize power consumption by going to standby after ALL the PLD inputs remain unchanged for an extended time (about 70ns). When the Turbo Bit is set to logic one (Bit 3 of the csiop PMMR0 Register), Turbo mode is turned off and then this automatic standby mode is achieved. Turning off Turbo mode increases propagation delays while reducing power consumption. The default state of the Turbo Bit is logic zero, meaning Turbo mode is on. Additionally, four bits are available in the csiop PMMR0 and PMMR2 Registers to block the 8032 bus control signals (RD, WR, PSEN, ALE) from entering the PLDs. This reduces power consumption and can be used only when these 8032 control signals are not used in PLD logic equations. See Power Management, page 187. Table 84. DPLD and GPLD Inputs Input Source Input Name Number of Signals 8032 Address Bus A0-A15 16 8032 Bus Control Signals PSEN, RD, WR, ALE 4 Reset from MCU Module RESET 1 Power-Down from AutoPower Down Counter PDN 1 PortA Input Macrocells (80-pin devices only) PA0-PA7 8 PortB Input Macrocells PB0-PB7 8 PortC Input Macrocells PC2, PC3, PC4, PC7 4 Port D Inputs (52-pin devices have only PD1) PD1, PD2 2 Page Register PGR0-PGR7 8 Macrocell OMC bank AB Feedback MCELLAB FB0-7 8 Macrocell OMC bank BC Feedback MCELLBC FB0-7 8 Flash memory Status Bit Ready/Busy 1157/231 uPSD33xx Figure 63. DPLD and GPLD GPLD 20 INPUT MACROCELLS PLD INPUT BUS PIN FEEDBACK, PORTS A, B, C NODE FEEDBACK DPLD Main Flash Memory Selects (FSx) AAAAAAAA BBBBBBBB C C C C 69 INPUTS OMC ALLOCATOR 4 or 8 2 or 4 Secondary Flash Memory Selects (CSBOOTx) 1 SRAM Select (RS0) 1 I/O PORT Select (CSIOP) 2 Periperal I/O Mode Range Selects (PSELx) 1 or 2 External Device Chip-Selects (ECSx) 8 8 4 8 8 4 AND-OR ARRAY AND-OR ARRAY 8032 ADDRESS 8032 BUS CONTROL PAGE REGISTER OTHER SIGNALS 16 OUTPUT MACROCELLS PORT A (80-pin only) PORT C PORT B 8032 DATA BUS PIN FEEDBACK, PORT D PORT D 8032 DATA BUS 8 PLD OUT A B A B A B A B A B A B A B A B B C B C B C B C B C B C B C B C 8 PLD OUT 69 INPUTS AI06600AuPSD33xx 158/231 Decode PLD (DPLD). The DPLD (Figure 64., page 159) generates the following memory decode signals: ■ Eight Main Flash memory sector select signals (FS0-FS7) with three product terms each ■ Four Secondary Flash memory sector select signals (CSBOOT0-CSBOOT3) with three product terms each ■ One SRAM select signal (RS0) with two product terms ■ One select signal for the base address of 256 PSD Module device control and status registers (CSIOP) with one product term ■ Two external chip-select output signals for Port D pins, each with one product term (52- pin devices only have one pin on Port D) ■ Two chip-select signals (PSEL0, PSEL1) used to enable the 8032 data bus repeater function (Peripheral I/O mode) for Port A on 80-pin devices. Each has one product term. A product term indicates the logical OR of two or more inputs. For example, three product terms in a DPLD output means the final output signal is capable of representing the logical OR of three different input signals, each input signal representing the logical AND of a combination of the 69 PLD inputs. Using the signal FS0 for example, the user may create a 3-product term chip select signal that is logic true when any one of three different address ranges are true... FS0 = address range 1 OR address range 2 OR address range 3. The phrase “one product term” is a bit misleading, but commonly used in this context. One product term is the logical AND of two or more inputs, with no OR logic involved at all, such as the CSIOP signal in Figure 64., page 159.159/231 uPSD33xx Figure 64. DPLD Logic Array FS0 FS1 FS7 FS6 FS5 FS4 FS3 FS2 MAIN FLASH MEMORY SECTOR SELECTS CSBOOT0 CSBOOT3 CSBOOT2 CSBOOT1 SECONDARY FLASH MEMORY SECTOR SELECTS RS0 SRAM SELECT CSIOP I/O & CONTROL REGISTERS SELECT ECS0 ECS1 EXTERNAL CHIPSELECTS (PORT D) PSEL0 PSEL1 PERIPHERAL I/O MODE RANGE SELECTS 8032 ADDRESS (A0 - A15) 16 4 1 POWER-DOWN INDICATOR (PDN) 1 PIN INPUT PORTS A, B, C (IMCs) 20 PIN INPUT PORT D 2 OMC FEEDBACK (MCELLAB.FB0-7) 8 PAGE REGISTER (PGR0 - PGR7) 8 8 1 OMC FEEDBACK (MCELLBC.FB0-7) PLD INPUT BUS 3 3 3 3 3 3 3 3 3 3 3 3 2 1 1 1 1 1 NUMBER OF PRODUCT TERMS AI06601A PSM MODULE RESET (RST) FLASH MEM PROG STATUS (RDYBSY) 8032 CNTL (RD, WR, PSEN, ALE)uPSD33xx 160/231 General PLD (GPLD). The GPLD is used to create general system logic. Figure 63., page 157 shows the architecture of the entire GPLD, and Figure 65., page 161 shows the relationship between one OMC, one IMC, and one I/O port pin, which is representative of pins on Ports A, B, and C. It is important to understand how these elements work together. A more detailed description will follow for the three major blocks (OMC, IMC, I/ O Port) shown in Figure 65. Figure 65 also shows which csiop registers to access for various PLD and I/O functions. The GPLD contains: ■ 16 Output Macrocells (OMC) ■ 20 Input Macrocells (IMC) ■ OMC Allocator ■ Product Term Allocator inside each OMC ■ AND-OR Array capable of generating up to 137 product terms ■ Three I/O Ports, A, B, and C161/231 uPSD33xx Figure 65. GPLD: One OMC, One IMC, and One I/O Port (typical pin, Port A, B, or C) OUTPUT MACROCELL (OMC) INPUT MACROCELL (IMC) FLIP-FLOP CLOCK GLOBAL CLOCK FLIP-FLOP CLEAR NODE FEEDBACK NATIVE PRODUCT TERMS PRODUCT TERM ALLOCATOR PRODUCT TERMS FROM OTHER OMCs I/O PORT LOGIC PERIPHERAL I/O MODE BIT OUTPUT ENABLE LATCHED 8032 ADDR BIT PSD MODULE PORT PIN 8032 DATA BIT 8032 DATA BIT OUTPUT ENABLE PIN FEEDBACK CLOCK or GATE SIGNAL PLD INPUT BUS OMC OUT ALE TO OTHER I/O PORT LOGIC OMC ALLOCATOR RESET PSD MODULE RESET FROM OTHER MACROCELL ALLOCATOR GLOBAL CLOCK AND-OR ARRAY CLOCK or GATE RESET FLIP-FLOP AND OTHER LOGIC BORROWED PRODUCT TERMS PIN INPUT LATCH OR PASS INPUT SIGNAL 8032 DATA BITS 8032 DATA BITS CSIOP REGISTERS (DATA OUT, DIRECTION CONTROL, DRIVE) M U X OMC OUTPUT FEED BACK DIRECTION CONTROL DATA OUT CSIOP REGISTERS (DATA IN, DATA OUT, DIRECTION, CONTROL, DRIVE, ENABLE) CSIOP REGISTERS (MCELLAB, MCELLBC) READ OMC LOAD OMC CSIOP REGISTERS (IMCA, IMCB, IMCC) READ IMC FLIP-FLOP PRESET PIN INPUT DATA IN 69 INPUTS 8032 RD 8032 RD 8032 RD 8032 WR 8032 WR 8032 ADDRESS, DATA, CONTROL BUS AI06602AuPSD33xx 162/231 Output Macrocell. The GPLD has 16 OMCs. Architecture of one individual OMC is shown in Figure 66. OMCs can be used for internal node feedback (buried registers to build shift registers, etc.), or their outputs may be routed to external port pins. The user can choose any mixture of OMCs used for buried functions and OMCs used to drive port pins. Referring to Figure 66, for each OMC there are native product terms available from the AND-OR Array to form logic, and also borrowed product terms are available (if unused) from other OMCs. The polarity of the final product term output is controlled by the XOR gate. Each OMC can implement sequential logic using the flip-flop element, or combinatorial logic when bypassing the flip-flop as selected by the output multiplexer. An OMC output can drive a port pin through the OMC Allocator, it can also drive the 8032 data bus, and also it can drive a feedback path to the AND-OR Array inputs, all at the same time. The flip-flop in each OMC can be synthesized as a D, T, JK, or SR type in PSDsoft Express. OMC flipflops are specified using PSDsoft Express in the “User Defined Nodes” section of the Design Assistant. Each flip-flop’s clock, preset, and clear inputs may be driven individually from a product term of the AND-OR Array, defined by equations in PSDsoft Express for signals *. c, *.pr, and *.re respectively. The preset and clear inputs on the flip-flops are level activated, active-high logic signals. The clock inputs on the flip-flops are rising-edge logic signals. Optionally, the signal CLKIN (pin PD1) can be used for a common clock source to all OMC flipflops. Each flip-flop is clocked on the rising edge. A common clock is specified in PSDsoft Express by assigning the function “Common Clock Input” for pin PD1 in the Pin Definition section, and then choosing the signal CLKIN when specifying the clock input (*.c) for individual flip-flops in the “User Defined Nodes” section. Figure 66. Detail of a Single OMC D CLR PRE Q MUX MUX M U X M U X PSDsoft PSDsoft OUTPUT MACROCELL (OMC) PT PRESET (.PR) FROM AND-OR ARRAY BORROWED PTs PT CLEAR (.RE) NODE FEEDBACK (.FB) POLARITY SELECT, PSDsoft PT ALLOCATOR, DRAWS FROM LOCAL AND GLOBAL UNUSED PRODUCT TERMS. PSDsoft DICTATES. LENDED PTs DATA BIT FROM 8032 DATA BIT TO 8032 INDICATES MCU WRITE TO PARTICULAR CSIO OMC REGISTER MCU OVERRIDES PT PRESET AND CLR DURING MCU WRITE MCU READ OF PARTICULAR CSIOP OMC REGISTER OMC OUTPUT FROM AND-OR ARRAY TO PLD INPUT BUS FROM AND-OR ARRAY NATIVE PTs ALLOCATED PTs PT CLOCK (.C) FROM AND-OR ARRAY GLOBAL CLOCK (CLKIN) FROM PLD INPUT BUS 8032 ADDRESS, DATA, CONTROL BUS OMC ALLOCATOR O U T PRODUCT TERMS FROM OTHER OMCs AI06617A163/231 uPSD33xx OMC Allocator. Outputs of the 16 OMCs can be routed to a combination of pins on Port A (80-pin devices only), Port B, or Port C as shown in Figure 67. OMCs are routed to port pins automatically after specifying pin numbers in PSDsoft Express. Routing can occur on a bit-by-bit basis, spitting OMC assignment between the ports. However, one OMC can be routed to one only port pin, not both ports. Product Term Allocator. Each OMC has a Product Term Allocator as shown in Figure 66., page 162. PSDsoft Express uses PT Allocators to give and take product terms to and from other OMCs to fit a logic design into the available silicon resources. This happens automatically in PSDsoft Express, but understanding how PT allocation works will help the user if the logic design does not “fit,” in which case the user may try selecting a different pin or different OMC for the logic where more product terms may be available. The following list summarizes how product terms are allocated to each OMC, as shown in Table 85., page 164. – MCELLAB0-MCELLAB7 each have three native product terms and may borrow up to six more – MCELLBC0-MCELLBC3 each have four native product terms and may borrow up to five more – MCELLBC4-MCELLBC7 each have four native product terms and may borrow up to six more. Native product terms come from the AND-OR Array. Each OMC may borrow product terms only from certain other OMCs, if they are not in use. Product term allocation does not add any propagation delay to the logic. The fitter report generated by PSDsoft Express will show any PT allocation that has occurred. If an equation requires more product terms than are available to it through PT allocation, then “external” product terms are required, which consumes other OMCs. This is called product term expansion and also happens automatically in PSDsoft Express as needed. PT expansion causes additional propagation delay because an additional OMC is consumed by the expansion process and it’s output is rerouted (or fed back) into the AND-OR array. The user can examine the fitter report generated by PSDsoft Express to see resulting PT allocation and PT expansion (expansion will have signal names, such as ‘*.fb_0’ or ‘*.fb_1’). PSDsoft Express will always try to fit the logic design first by using PT allocation, and if that is not sufficient then PSDsoft Express will use PT expansion. Product term expansion may occur in the DPLD for complex chip select equations for Flash memory sectors and for SRAM, but this is a rare occurence. If PSDsoft Express does use PT expansion in the DPLD, it results in an approximate 15ns additional propagation delay for that chip select signal, which gives 15ns less time for the memory to respond. Be aware of this and consider adding a wait state to the 8032 bus access (using the SFR named, BUSCON), or lower the 8032 clock frequency to avoid problems with memory access time. Figure 67. OMC Allocator PORT B PINS PORT C PINS PORT A PINS (80-pin pkg only) OMC Bank AB (MCELLAB0-7) OMC Bank BC (MCELLBC0-7) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 4 3 2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ** ** * = Used for JTAG, Pin Not Available to GPLD AI09177uPSD33xx 164/231 Table 85. OMC Port and Data Bit Assignments Note: 1. MCELLAB0-MCELLAB7 can be output to Port A pins only on 80-pin devices. Port A is not available on 52-pin devices 2. Port pins PC0, PC1, PC5, and PC6 are dedicated JTAG pins and are not available as outputs for MCELLBC 0, 1, 5, or 6 OMC Port Assignment(1,2) Native Product Terms from AND-OR Array Maximum Borrowed Product Terms Data Bit on 8032 Data Bus for Loading or Reading OMC MCELLAB0 Port A0 or B0 3 6 D0 MCELLAB1 Port A1 or B1 3 6 D1 MCELLAB2 Port A2 or B2 3 6 D2 MCELLAB3 Port A3 or B3 3 6 D3 MCELLAB4 Port A4 or B4 3 6 D4 MCELLAB5 Port A5 or B5 3 6 D5 MCELLAB6 Port A6 or B6 3 6 D6 MCELLAB7 Port A7 or B7 3 6 D7 MCELLBC0 Port B0 4 5 D0 MCELLBC1 Port B1 4 5 D1 MCELLBC2 Port B or C2 4 5 D2 MCELLBC3 Port B3 or C3 4 5 D3 MCELLBC4 Port B4 or C4 4 6 D4 MCELLBC5 Port B5 4 6 D5 MCELLBC6 Port B6 4 6 D6 MCELLBC7 Port B7 orC7 4 6 D7165/231 uPSD33xx Loading and Reading OMCs. Each of the two OMC groups (eight OMCs each) occupies a byte in csiop space, named MCELLAB and MCELLBC (see Table 86 and Table 87). When the 8032 writes or reads these two OMC registers in csiop it is accessing each of the OMCs through it’s 8-bit data bus, with the bit assignment shown in Table 85., page 164. Sometimes it is important to know the bit assignment when the user builds GPLD logic that is accessed by the 8032. For example, the user may create a 4-bit counter that must be loaded and read by the 8032, so the user must know which nibble in the corresponding csiop OMC register the firmware must access. The fitter report generated by PSDsoft Express will indicate how it assigned the OMCs and data bus bits to the logic. The user can optionally force PSDsoft Express to assign logic to specific OMCs and data bus bits if desired by using the ‘PROPERTY’ statement in PSDsoft Express. Please see the PSDsoft Express User’s Manual for more information on OMC assignments. Loading the OMC flip-flops with data from the 8032 takes priority over the PLD logic functions. As such, the preset, clear, and clock inputs to the flip-flop can be asynchronously overridden when the 8032 writes to the csiop registers to load the individual OMCs. Table 86. Output Macrocell MCELLAB (address = csiop + offset 20h) Note: All bits clear to logic ’0’ at power-on reset, but do not clear after warm reset conditions (non-power-on reset) Table 87. Output Macrocell MCELLBC (address = csiop + offset 21h) Note: All bits clear to logic ’0’ at power-on reset, but do not clear after warm reset conditions (non-power-on reset) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCELLAB7 MCELLAB6 MCELLAB5 MCELLAB4 MCELLAB3 MCELLAB2 MCELLAB1 MCELLAB0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCELLBC7 MCELLBC6 MCELLBC5 MCELLBC4 MCELLBC3 MCELLBC2 MCELLBC1 MCELLBC0uPSD33xx 166/231 OMC Mask Registers. There is one OMC Mask Register for each of the two groups of eight OMCs shown in Table 88 and Table 89. The OMC mask registers are used to block loading of data to individual OMCs. The default value for the mask registers is 00h, which allows loading of all OMCs. When a given bit in a mask register is set to a '1,' the 8032 is blocked from writing to the associated OMC flip-flop. For example, suppose that only four of eight OMCs (MCELLAB0-3) are being used for a state machine. The user may not want the 8032 write to all the OMCs in MCELLAB because it would overwrite the state machine registers. Therefore, the user would want to load the mask register for MCELLAB with the value 0Fh before writing OMCs. Table 88. Output Macrocell MCELLAB Mask Register (address = csiop + offset 22h) Note: 1. Default is 00h after any reset condition 2. 1 = block writing to individual macrocell, 0 = allow writing to individual macrocell Table 89. Output Macrocell MCELLBC Mask Register (address = csiop + offset 23h) Note: 1. Default is 00h after any reset condition 2. 1 = block writing to individual macrocell, 0 = allow writing to individual macrocell Input Macrocells. The GPLD has 20 IMCs, one for each pin on Port A (80-pin device only), one for each pin on Port B, and for the four pins on Port C that are not JTAG pins. The architecture of one individual IMC is shown in Figure 68., page 167. IMCs are individually configurable, and they can strobe a signal coming in from a port pin as a latch (gated), or as a register (clocked), or the IMC can pass the signal without strobing, all prior to driving the signal onto the PLD input bus. Strobing is useful for sampling and debouncing inputs (keypad inputs, etc.) before entering the PLD AND-OR arrays. The outputs of IMCs can be read by the 8032 asynchronously when the 8032 reads the csiop registers shown in Table 90, Table 91, and Table 92., page 167. It is possible to read a PSD Module port pin using one of two different methods, one method is by reading IMCs as described here, the other method is using MCU I/O mode described in a later section. The optional IMC clocking or gating signal used to strobe pin inputs is driven by a product term from the AND-OR array. There is one clocking or gating product term available for each group of four IMCs. Port inputs 0-3 are controlled by one product term and 4-7 by another. To specify in PSDsoft Express the method in which a signal will be strobed as it enters an IMC for a given input pin on Port A, B, or C, just specify “PT Clocked Register” to use a rising edge to clock the incoming signal, or specify “PT Clock Latch” to use an active high gate signal to latch the incoming signal. Then define an equation for the IMC clock (.ld) or the IMC gate (.le) signal in the “I/O Equations” section. If the user would like to latch an incoming signal using the gate signal ALE from the 8032, then in PSDsoft Express, for a given input pin on Port A, B, or C, specify “Latched Address” as the pin function. If it is desired to pass an incoming signal through an IMC directly to the AND-OR array inputs without clocking or gating (this is most common), in PSDsoft Express simply specify “Logic or Address” for the input pin function on Port A, B, or C. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mask MCELLAB7 Mask MCELLAB6 Mask MCELLAB5 Mask MCELLAB4 Mask MCELLAB3 Mask MCELLAB2 Mask MCELLAB1 Mask MCELLAB0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mask MCELLBC7 Mask MCELLBC6 Mask MCELLBC5 Mask MCELLBC4 Mask MCELLBC3 Mask MCELLBC2 Mask MCELLBC1 Mask MCELLBC0167/231 uPSD33xx Figure 68. Detail of a Single IMC Table 90. Input Macrocell Port A(1) (address = csiop + offset 0Ah) Note: 1. Port A not available on 52-pin uPSD33xx devices 2. 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’ Table 91. Input Macrocell Port B (address = csiop + offset 0Bh) Note: 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’ Table 92. Input Macrocell Port C (address = csiop + offset 18h) Note: 1. X = Not guaranteed value, can be read either '1' or '0.' These are JTAG pins. 2. 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’ Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IMC PA7 IMC PA6 IMC PA5 IMC PA4 IMC PA3 IMC PA2 IMC PA1 IMC PA0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IMC PB7 IMC PB6 IMC PB5 IMC PB4 IMC PB3 IMC PB2 IMC PB1 IMC PB0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IMC PC7 X X IMC PC4 IMC PC3 IMC PC2 X X INPUT MACROCELL (IMC) Q D G Q D M U X M U X PSDsoft 8032 DATA BIT 8032 READ OF PARTICULAR CSIOP IMC REGISTER PT CLOCK OR GATE (.LD OR .LE) PIN INPUT LATCHED INPUT GATED INPUT (.LD) (.LE) ALE PSDsoft ALE 8032 ADDR, DATA, CNTL BUS FROM I/O PORT LOGIC INPUT SIGNAL FROM PIN ON PORT A, B, or C FROM AND-OR ARRAY TO PLD INPUT BUS THIS SIGAL IS GANGED TO 3 OTHER IMCs, GROUPING IMC 0 - 3 or IMC 4 - 7. AI06603AuPSD33xx 168/231 I/O Ports. There are four programmable I/O ports on the PSD Module: Port A (80-pin device only), Port B, Port C, and Port D. Ports A and B are eight bits each, Port C is four bits, and Port D is two bits for 80-pin devices or 1-bit for 52-pin devices. Each port pin is individually configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Express then programming with JTAG, and also by the 8032 writing to csiop registers at run-time. Topics discussed in this section are: ■ General Port architecture ■ Port Operating Modes ■ Individual Port Structure General Port Architecture. The general architecture for a single I/O Port pin is shown in Figure 69., page 169. Port structures for Ports A, B, C, and D differ slightly and are shown in Figure 74., page 181 though Figure 77., page 186. Figure 69., page 169 shows four csiop registers whose outputs are determined by the value that the 8032 writes to csiop Direction, Drive, Control, and Data Out. The I/O Port logic contains an output mux whose mux select signal is determined by PSDsoft Express and the csiop Control register bits at run-time. Inputs to this output mux include the following: 1. Data from the csiop Data Out register for MCU I/O output mode (All ports) 2. Latched de-multiplexed 8032 Address for Address Output mode (Ports A and B only) 3. Peripheral I/O mode data bit (Port A only) 4. GPLD OMC output (Ports A, B, and C). The Port Data Buffer (PDB) provides feedback to the 8032 and allows only one source at a time to be read when the 8032 reads various csiop registers. There is one PDB for each port pin enabling the 8032 to read the following on a pin-by-pin basis: 1. MCU I/O signal direction setting (csiop Direction reg) 2. Pin drive type setting (csiop Drive Select reg) 3. Latched Addr Out mode setting (csiop Control reg) 4. MCU I/O pin output setting (csiop Data Out reg) 5. Output Enable of pin driver (csiop Enable Out reg) 6. MCU I/O pin input (csiop Data In reg) A port pin’s output enable signal is controlled by a two input OR gate whose inputs come from: a product term of the AND-OR array; the output of the csiop Direction Register. If an output enable from the AND-OR Array is not defined, and the port pin is not defined as an OMC output, and if Peripheral I/O mode is not used, then the csiop Direction Register has sole control of the OE signal. As shown in Figure 69., page 169, a physical port pin is connected to the I/O Port logic and is also separately routed to an IMC, allowing the 8032 to read a port pin by two different methods (MCU I/O input mode or read the IMC). Port Operating Modes. I/O Port logic has several modes of operation. Table 88., page 166 summarizes which modes are available on each port. Each of the port operating modes are described in following sections. Some operating modes can be defined using PSDsoft Express, and some by the 8032 writing to the csiop registers at run-time, and some require both. For example, PLD I/O, Latched Address Out, and Peripheral I/O modes must be defined in PSDsoft Express and programmed into the device using JTAG, but an additional step must happen at run-time to activate Latched Address Out mode and Peripheral I/O mode, but not needed for PLD I/O. In another example, MCU I/O mode is controlled completely by the 8032 at runtime and only a simple pin name declaration is needed in PSDsoft Express for documentation. Table 89., page 166 summarizes what actions are needed in PSDsoft Express and what actions are required by the 8032 at run-time to achieve the various port functions.169/231 uPSD33xx Figure 69. Detail of a Single I/O Port (typical of Ports A, B, C) I/O PORT LOGIC O U T P U T M U X P D B M U X DIRECTION DRIVE SELECT CONTROL DATA OUT (MCUI/O) ENABLE OUT DATA IN (MCUI/O) D BIT, PERIPH I/O MODE, Port A PT OUTPUT ENABLE (.OE) LATCHED ADDR BIT, PORT A or B OE MUX 8032 DATA BIT OUTPUT DRIVER TYPICAL PIN PORT A, B, C PSD MODULE RESET ONE of 6 CSIOP REGISTERS OUTPUT SELECT PERIPHERAL I/O MODE SETS DIRECTION (PORT A ONLY) 8032 ADDRESS, DATA, CONTROL BUS 1 2 3 1 4 2 3 4 5 6 FROM OMC OUTPUT TO IMC FROM PLD INPUT BUS FROM AND-OR ARRAY FROM OMC ALLOCATOR D CLR DIRECTION DRIVE CONTROL (MCUI/O) DATA OUT RESET PSDsoft PSELx PERIPH I/O DATA BIT CSIOP REGISTERS Q Q Q Q 8032 DRIVE TYPE DATA BITS INPUT BUFFER OUTPUT ENABLE WR RD PIO EN 8032 WR 8032 RD AI07873AuPSD33xx 170/231 Table 93. Port Operating Modes Note: 1. MCELLBC outputs available only on pins PC2, PC3, PC4, and PC7. 2. JTAG pins (PC0/TMS, PC1/TCK, PC5/TDI, PC6/TDO) are dedicated to JTAG pin functions (cannot be used for general I/O). Port Operating Mode Port A (80-pin only) Port B Port C Port D Find it MCU I/O Yes Yes Yes Yes MCU I/O Mode., p age 172 PLD I/O OMC MCELLAB Outputs OMC MCELLBC Outputs External Chip-Select Outputs PLD Inputs Yes No No Yes Yes Yes No Yes No Yes(1) No Yes No No Yes Yes PLD I/O Mode., p age 174 Latched Address Output Yes Yes No No Latched Address Output Mode, pa ge 177 Peripheral I/O Mode Yes No No No Peripher al I/O Mode, pa ge 178 JTAG ISP No No Yes(2) No JTAG ISP Mode., p age 179171/231 uPSD33xx Table 94. Port Configuration Setting Requirements Port Operating Mode Required Action in PSDsoft Express to Configure each Pin Value that 8032 writes to csiop Control Register at run-time Value that 8032 writes to csiop Direction Register at run-time Value that 8032 writes to Bit 7 (PIO_EN) of csiop VM Register at run-time MCU I/O Choose the MCU I/O function and declare the pin name Logic '0' (default) Logic 1 = Out of uPSD Logic 0 = Into uPSD N/A PLD I/O Choose the PLD function type, declare pin name, and specify logic equation(s) N/A Direction register has no effect on a pin if pin is driven from OMC output N/A Latched Address Output Choose Latched Address Out function, declare pin name Logic '1' Logic '1' Only N/A Peripheral I/O Choose Peripheral I/O mode function and specify address range in DPLD for PSELx N/A N/A PIO_EN Bit = Logic 1 (default is '0') 4-PIN JTAG ISP No action required in PSDsoft to get 4-pin JTAG. By default TDO, TDI, TCK, TMS are dedicated JTAG functions. N/A N/A N/A 6-PIN JTAG ISP (faster programming) Choose JTAG TSTAT function for pin PC3 and JTAG TERR function for pin PC4. N/A N/A N/AuPSD33xx 172/231 MCU I/O Mode. In MCU I/O mode, the 8032 on the MCU Module expands its own I/O by using the I/O Ports on the PSD Module. The 8032 can read PSD Module I/O pins, set the direction of the I/O pins, and change the output state of I/O pins by accessing the Data In, Direction, and Data Out csiop registers respectively at run-time. To implement MCU I/O mode, each desired pin is specified in PSDsoft Express as MCU I/O function and given a pin name. Then 8032 firmware is written to set the Direction bit for each corresponding pin during initialization routines (0 = In, 1 = Out of the chip), then the 8032 firmware simply reads the corresponding Data In register to determine the state of an I/O pin, or writes to a Data Out register to set the state of a pin. The Direction of each pin may be changed dynamically by the 8032 if desired. A mixture of input and output pins within a single port is allowed. Figure 69., page 169 shows the Data In, Data Out, and Direction signal paths. The Data In registers are defined in Table 95 to Table 98. The Data Out registers are defined in Table 99 to Table 102., page 173. The Direction registers are defined in Table 103 to Table 106., page 173. Table 95. MCU I/O Mode Port A Data In Register(1) (address = csiop + offset 00h) Note: 1. Port A not available on 52-pin uPSD33xx devices 2. For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’ Table 96. MCU I/O Mode Port B Data In Register (address = csiop + offset 01h) Note: For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’ Table 97. MCU I/O Mode Port C Data In Register (address = csiop + offset 10h) Note: 1. X = Not guaranteed value, can be read either '1' or '0.' 2. For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’ Table 98. MCU I/O Mode Port D Data In Register (address = csiop + offset 11h) Note: 1. X = Not guaranteed value, can be read either '1' or '0.' 2. For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’ 3. Not available on 52-pin uPSD33xx devices Table 99. MCU I/O Mode Port A Data Out Register(1) (address = csiop + offset 04h) Note: 1. Port A not available on 52-pin uPSD33xx devices 2. For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’ 3. Default state of register is 00h after reset or power-up Table 100. MCU I/O Mode Port B Data Out Register (address = csiop + offset 05h) Note: 1. For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’ 2. Default state of register is 00h after reset or power-up Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC7 X X PC4 PC3 PC2 X X Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XXXXX PD2(3) PD1 X Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0173/231 uPSD33xx Table 101. MCU I/O Mode Port C Data Out Register (address = csiop + offset 12h) Note: 1. For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’ 2. Default state of register is 00h after reset or power-up Table 102. MCU I/O Mode Port D Data Out Register (address = csiop + offset 13h) Note: 1. For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’ 2. Default state for register is 00h after reset or power-up 3. Not available on 52-pin uPSD33xx devices Table 103. MCU I/O Mode Port A Direction Register(1) (address = csiop + offset 06h) Note: 1. Port A not available on 52-pin uPSD33xx devices 2. For each bit, 1 = out from uPSD33xx port pin1, 0 = in to PSD33xx port pin 3. Default state for register is 00h after reset or power-up Table 104. MCU I/O Mode Port B Direction In Register (address = csiop + offset 07h) Note: 1. For each bit, 1 = out from uPSD33xx port pin1, 0 = in to PSD33xx port pin 2. Default state for register is 00h after reset or power-up Table 105. MCU I/O Mode Port C Direction Register (address = csiop + offset 14h) Note: 1. For each bit, 1 = out from uPSD33xx port pin1, 0 = in to PSD33xx port pin 2. Default state for register is 00h after reset or power-up Table 106. MCU I/O Mode Port D Direction Register (address = csiop + offset 15h) Note: 1. For each bit, 1 = out from uPSD33xx port pin1, 0 = in to PSD33xx port pin 2. Default state for register is 00h after reset or power-up 3. Not available on 52-pin uPSD33xx devices Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC7 N/A N/A PC4 PC3 PC2 N/A N/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N/A N/A N/A N/A N/A PD2(3) PD1 N/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC7 N/A N/A PC4 PC3 PC2 N/A N/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N/A N/A N/A N/A N/A PD2(3) PD1 N/AuPSD33xx 174/231 PLD I/O Mode. Pins on Ports A, B, C, and D can serve as inputs to either the DPLD or the GPLD. Inputs to these PLDs from Ports A, B, and C are routed through IMCs before reaching the PLD input bus. Inputs to the PLDs from Port D do not pass through IMCs, but route directly to the PLD input bus. Pins on Ports A, B, and C can serve as outputs from GPLD OMCs, and Port D pins can be outputs from the DPLD (external chip-selects) which do not consume OMCs. Whenever a pin is specified to be a PLD output, it cannot be used for MCU I/O mode, or other pin modes. If a pin is specified to be a PLD input, it is still possible to read the pin using MCU I/O input mode with the csiop register Data In. Also, the csiop Direction register can still affect a pin which is used for a PLD input. The csiop Data Out register has no effect on a PLD output pin. Each pin on Ports A, B, C, and D have a tri-state buffer at the final output stage. The Output Enable signal for this buffer is driven by the logical OR of two signals. One signal is an Output Enable signal generated by the AND-OR array (from an .oe equation specified in PSDsoft), and the other signal is the output of the csiop Direction register. This logic is shown in Figure 69., page 169. At power-on, all port pins default to high-impedance input (Direction registers default to 00h). However, if an equation is written for the Output Enable that is active at power-on, then the pin will behave as an output. PLD I/O equations are specified in PSDsoft Express and programmed into the uPSD using JTAG. Figure 70 shows a very simple combinatorial logic example which is implemented on pins of Port B. To give a general idea how PLD logic is implemented using PSDsoft Express, Figure 71., page 175 illustrates the pin declaration window of PSDsoft Express, showing the PLD output at pin PB0 declared as “Combinatorial” in the “PLD Output” section, and a signal name, “pld_out”, is specified. The other three signals on pins PB1, PB2, and PB3 would be declared as “Logic or Address” in the “PLD Input” section, and given signal names. In the “Design Assistant” window of PSDsoft Express shown in Figure 72., page 176, simply enter the logic equation for the signal “pld_out” as shown. Either type in the logic statements or enter them using a point-and-click method, selecting various signal names and logic operators available in the window. After PSDsoft Express has accepted and realized the logic from the equations, it synthesizes the logic statement: pld_out = ( pld_in_1 # pld_in_2 ) & !pld_in_3; to be programmed into the GPLD. See the PSDsoft User’s Manual for all the steps. Note: If a particular OMC output is specified as an internal node and not specified as a port pin output in PSDsoft Express, then the port pin that is associated with that OMC can be used for other I/O functions. Figure 70. Simple PLD Logic Example PLDIN 1 PLDIN 2 PLDIN 3 PLD OUT PB0 PB3 PB2 PB1 AI09178175/231 uPSD33xx Figure 71. Pin Declarations in PSDsoft Express for Simple PLD ExampleuPSD33xx 176/231 Figure 72. Using the Design Assistant in PSDsoft Express for Simple PLD Example177/231 uPSD33xx Latched Address Output Mode. In the MCU Module, the data bus Bits D0-D15 are multiplexed with the low address Bits A0-A15, and the ALE signal is used to separate them with respect to time. Sometimes it is necessary to send de-multiplexed address signals to external peripherals or memory devices. Latched Address Output mode will drive individual demuxed address signals on pins of Ports A or B. Port pins can be designated for this function on a pin-by-pin basis, meaning that an entire port will not be sacrificed if only a few address signals are needed. To activate this mode, the desired pins on Port A or Port B are designated as “Latched Address Out” in PSDsoft. Then in the 8032 initialization firmware, a logic ’1’ is written to the csiop Control register for Port A or Port B in each bit position that corresponds to the pin of the port driving an address signal. Table 107 and Table 108 define the csiop Control register locations and bit assignments. The latched low address byte A4-A7 is available on both Port A and Port B. The high address byte A8-A15 is available on Port B only. Selection of high or low address byte is specified in PSDsoft Express. Table 107. Latched Address Output, Port A Control Register(1) (address = csiop + offset 02h) Note: 1. Port A not available on 52-pin uPSD33xx devices 2. For each bit, 1 = drive demuxed 8032 address signal on pin, 0 = pin is default mode, MCU I/O 3. Default state for register is 00h after reset or power-up Table 108. Latched Address Output, Port B Control Register (address = csiop + offset 03h) Note: 1. For each bit, 1 = drive demuxed 8032 address signal on pin, 0 = pin is default mode, MCU I/O 2. Default state for register is 00h after reset or power-up Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA7 (addr A7) PA6 (addr A6) PA5 (addr A5) PA4 (addr A4) PA3 (addr A3) PA2 (Addr A2) PA1 (addr A1) PA0 (addr A0) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PB7 (addr A7 or A15) PB6 (addr A6 or A14) PB5 (addr A5 or A13) PB4 (addr A4 or A12) PB3 (addr A3 or A11) PB2 (Addr A2 or A10) PB1 (addr A1 or A9) PB0 (addr A0 or A8)uPSD33xx 178/231 Peripheral I/O Mode. This mode will provide a data bus repeater function for the 8032 to interface with external parallel peripherals. The mode is only available on Port A (80-pin devices only) and the data bus signals, D0 - D7, are de-multiplexed (no address A0-A7). When active, this mode behaves like a bidirectional buffer, with the direction automatically controlled by the 8032 RD and WR signals for a specified address range. The DPLD signals PSEL0 and PSEL1 determine this address range. Figure 69., page 169 shows the action of Peripheral I/O mode on the Output Enable logic of the tri-state output driver for a single port pin. Figure 73., page 178 illustrates data repeater the operation. To activate this mode, choose the pin function “Peripheral I/O Mode” in PSDsoft Express on any Port A pin (all eight pins of Port A will automatically change to this mode). Next in PSDsoft, specify an address range for the PSELx signals in the “Chip-Select” section of the “Design Assistant.” Specify an address range for either PSEL0 or PSEL1. Always qualify the PSELx equation with “PSEN is logic '1'” to ensure Peripheral I/O mode is only active during 8032 data cycles, not code cycles. Only one equation is needed since PSELx signals are OR’ed together (Figure 73). Then in the 8032 initialization firmware, a logic ’1’ is written to the csiop VM register, Bit 7 (PIO_EN) as shown in Table 73., page 132. After this, Port A will automatically perform this repeater function whenever the 8032 presents an address (and memory page number, if paging is used) that is within the range specified by PSELx. Once Port A is designated as Peripheral I/O mode in PSDsoft Express, it cannot be used for other functions. Note: The user can alternatively connect an external parallel peripheral to the standard 8032 AD0- AD7 pins on an 80-pin uPSD device (not Port A), but these pins have multiplexed address and data signals, with a weaker fanout drive capability. Figure 73. Peripheral I/O Mode PSEL1 PORT A pins PA0 - PA7 PSEL0 VM REGISTER BIT 7 (PIO EN) 8032 RD 8032 WR 8032 DATA BUS D0-D7 (DE-MUXED) 8 8 AI02886A179/231 uPSD33xx JTAG ISP Mode. Four of the pins on Port C are based on the IEEE 1149.1 JTAG specification and are used for In-System Programming (ISP) of the PSD Module and debugging of the 8032 MCU Module. These pins (TDI, TDO, TMS, TCK) are dedicated to JTAG and cannot be used for any other I/O function. There are two optional pins on Port C (TSTAT and TERR) that can be used to reduce programming time during ISP. See JTAG ISP and JTAG Debug, page 195. Other Port Capabilities. It is possible to change the type of output drive on the ports at run-time. It is also possible to read the state of the output enable signal of the output driver at run-time. The following sections provide the details. Port Pin Drive Options. The csiop Drive Select registers allow reconfiguration of the output drive type for certain pins on Ports A, B, C, and D. The 8032 can change the default drive type setting at run-time. The is no action needed in PSDsoft Express to change or define these pin output drive types. Figure 69., page 169 shows the csiop Drive Select register output controlling the pin output driver. The default setting for drive type for all pins on Ports A, B, C, and D is a standard CMOS pushpull output driver. Note: When a pin on Port A, B, C, D is not used as an output and has no external device driving it as an input (floating pin), excess power consumption can be avoided by placing a weak pull-up resistor (100KΩ) to VDD which keeps the CMOS input pin from floating. Drive Select Registers. The csiop Drive Select Registers will configure a pin output driver as Open Drain or CMOS push/pull for some port pins, and controls the slew rate for other port pins. An external pull-up resistor should be used for pins configured as Open Drain, and the resistor should be sized not to exceed the current sink capability of the pin (see DC specifications). Open Drain outputs are diode clamped, thus the maximum voltage on an pin configured as Open Drain is VDD + 0.7V. A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to logic '1.' Note: The slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive Register is set to '1.' The default rate is standard slew rate (see AC specifications). Table 109 through Table 112., page 180 show the csiop Drive Registers for Ports A, B, C, and D. The tables summarize which pins can be configured as Open Drain outputs and which pins the slew rate can be changed. The default output type is CMOS push/pull output with normal slew rate. Enable Out Registers. The state of the output enable signal for the output driver at each pin on Ports A, B, C, and D can be read at any time by the 8032 when it reads the csiop Enable Output registers. Logic '1' means the driver is in output mode, logic ’0’ means the output driver is in high-impedance mode, making the pin suitable for input mode (read by the input buffer shown in Figure 69., page 169). Figure 69 shows the three sources that can control the pin output enable signal: a product term from AND-OR array; the csiop Direction register; or the Peripheral I/O Mode logic (Port A only). The csiop Enable Out registers represent the state of the final output enable signal for each port pin driver, and are defined in Table 113., page 180 through Table 116., page 180. Table 109. Port A Pin Drive Select Register(1) (address = csiop + offset 08h) Note: 1. Port A not available on 52-pin uPSD33xx devices 2. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull 3. Default state for register is 00h after reset or power-up Table 110. Port B Pin Drive Select Register (address = csiop + offset 09h) Note: 1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull 2. Default state for register is 00h after reset or power-up Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA7 Open Drain PA6 Open Drain PA5 Open Drain PA4 Open Drain PA3 Slew Rate PA2 Slew Rate PA1 Slew Rate PA0 Slew Rate Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PB7 Open Drain PB6 Open Drain PB5 Open Drain PB4 Open Drain PB3 Slew Rate PB2 Slew Rate PB1 Slew Rate PB0 Slew RateuPSD33xx 180/231 Table 111. Port C Pin Drive Select Register (address = csiop + offset 16h) Note: 1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull 2. Default state for register is 00h after reset or power-up Table 112. Port D Pin Drive Select Register (address = csiop + offset 17h) Note: 1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull 2. Default state for register is 00h after reset or power-up 3. Pin is not available on 52-pin uPSD33xx devices Table 113. Port A Enable Out Register(1) (address = csiop + offset 0Ch) Note: 1. Port A not available on 52-pin uPSD33xx devices 2. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input) Table 114. Port B Enable Out Register (address = csiop + offset 0Dh) Note: For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input) Table 115. Port C Enable Out Register (address = csiop + offset 1Ah) Note: 1. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input) Table 116. Port D Enable Out Register (address = csiop + offset 1Bh) Note: 1. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input) 2. Pin is not available on 52-pin uPSD33xx devices Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC7 Open Drain N/A (JTAG) N/A (JTAG) PC4 Open Drain PC3 Open Drain PC2 Open Drain N/A (JTAG) N/A (JTAG) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N/A N/A N/A N/A N/A PD2(3) Slew Rate PD1 Slew Rate N/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA7 OE PA6 OE PA5 OE PA4 OE PA3 OE PA2 OE PA1 OE PA0 OE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PB7 OE PB6 OE PB5 OE PB4 OE PB3 OE PB2 OE PB1 OE PB0 OE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC7 OE N/A (JTAG) N/A (JTAG) PC4 OE PC3 OE PC2 OE N/A (JTAG) N/A (JTAG) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N/A N/A N/A N/A N/A PD2 OE(2) PD1 OE N/A181/231 uPSD33xx Individual Port Structures. Ports A, B, C, and D have some differences. The structure of each individual port is described in the next sections. Port A Structure. Port A supports the following operating modes: ■ MCU I/O Mode ■ GPLD Output Mode from Output Macrocells MCELLABx ■ GPLD Input Mode to Input Macrocells IMCAx ■ Latched Address Output Mode ■ Peripheral I/O Mode Port A also supports Open Drain/Slew Rate output drive type options using csiop Drive Select registers. Pins PA0-PA3 can be configured to fast slew rate, pins PA4-PA7 can be configured to Open Drain Mode. See Figure 74 for details. Figure 74. Port A Structure Note: 1. Port pins PA0-PA3 are capable of Fast Slew Rate output drive option. Port pins PA4-PA7 are capable of Open Drain output option. I/O PORT A LOGIC O U T P U T M U P X D B M U X DIRECTION DRIVE SELECT CONTROL DATA OUT (MCUI/O) ENABLE OUT DATA IN (MCUI/O) D BIT, PERIPH I/O MODE PT OUTPUT ENABLE (.OE) LATCHED ADDR BIT OE MUX OUTPUT ENABLE TYPICAL PIN, PORT A PSD MODULE RESET ONE of 6 CSIOP REGISTERS OUTPUT SELECT PERIPHERAL I/O MODE SETS DIRECTION 8032 ADDRESS, DATA, CONTROL BUS 1 2 3 1 4 2 3 4 5 6 FROM OMC OUTPUT (MCELLABx) FROM PLD INPUT BUS FROM ANDOR ARRAY FROM OMC ALLOCATOR D CLR DIRECTION DRIVE CONTROL (MCUI/O) DATA OUT 8032 WR RESET PSDsoft 8032 RD WR RD PSELx PERIPH I/O DATA BIT TO IMCs PIO EN CSIOP REGISTERS Q Q Q Q DRIVE TYPE SELECT(1) 8032 DATA BITS 8032 DATA BIT PIN INPUT CMOS BUFFER NO HYSTERESIS VDD VDD PIN OUTPUT 1 = OPEN DRAIN, PA4 - PA7 1 = FAST SLEW RATE, PA0 - PA3 IMCA0 - IMCA7 AI09179uPSD33xx 182/231 Port B Structure. Port B supports the following operating modes: ■ MCU I/O Mode ■ GPLD Output Mode from Output Macrocells MCELLABx, or MCELLBCx (OMC allocator routes these signals) ■ GPLD Input Mode to Input Macrocells IMCBx ■ Latched Address Output Mode Port B also supports Open Drain/Slew Rate output drive type options using the csiop Drive Select registers. Pins PB0-PB3 can be configured to fast slew rate, pins PB4-PB7 can be configured to Open Drain Mode. See Figure 75 for detail. Figure 75. Port B Structure Note: 1. Port pins PB0-PB3 are capable of Fast Slew Rate output drive option. Port pins PB4-PB7 are capable of Open Drain output option. I/O PORT B LOGIC O U T P U T M U P X D B M U X DIRECTION DRIVE SELECT CONTROL DATA OUT (MCUI/O) ENABLE OUT DATA IN (MCUI/O) PT OUTPUT ENABLE (.OE) LATCHED ADDR BIT OUTPUT ENABLE OUTPUT ENABLE TYPICAL PIN, PORT B PSD MODULE RESET ONE of 6 CSIOP REGISTERS OUTPUT SELECT 8032 ADDRESS, DATA, CONTROL BUS 1 2 3 1 2 3 4 5 6 FROM OMC OUTPUT (MCELLABx or MCELLBCx) FROM PLD INPUT BUS FROM ANDOR ARRAY FROM OMC ALLOCATOR D CLR DIRECTION DRIVE CONTROL (MCUI/O) DATA OUT 8032 WR RESET PSDsoft 8032 RD TO IMCs CSIOP REGISTERS Q Q Q Q DRIVE TYPE SELECT(1) 8032 DATA BITS 8032 DATA BIT PIN INPUT CMOS BUFFER NO HYSTERESIS VDD VDD PIN OUTPUT 1 = OPEN DRAIN, PB4 - PB7 1 = FAST SLEW RATE, PB0 - PB3 IMCB0 - IMCB7 AI09180183/231 uPSD33xx Port C Structure. Port C supports the following operating modes on pins PC2, PC3, PC4, PC7: ■ MCU I/O Mode ■ GPLD Output Mode from Output Macrocells MCELLBC2, MCELLBC3, MCELLBC4, MCELLBC7 ■ GPLD Input Mode to Input Macrocells IMCC2, IMCC3, IMCC4, IMCC7 See Figure 76., page 184 for detail. Port C pins can also be configured in PSDsoft for other dedicated functions: – Pins PC3 and PC4 support TSTAT and TERR status indicators, to reduce the amount of time required for JTAG ISP programming. These two pins must be used together for this function, adding to the four standard JTAG signals. When TSTAT and TERR are used, it is referred to as “6-pin JTAG”. PC3 and PC4 cannot be used for other functions if they are used for 6-pin JTAG. See JTAG ISP and JTAG Debug, page 195 for details. – PC2 can be used as a voltage input (from battery or other DC source) to backup the contents of SRAM when VDD is lost. This function is specified in PSDsoft Express as SRAM Standby Mode (battery backup), page 193. – PC3 can be used as an output to indicate when a Flash memory program or erase operation has completed. This is specified in PSDsoft Express as Ready/Busy (PC3), page 153. – PC4 can be used as an output to indicate when the SRAM has switched to backup voltage (when VDD is less than the battery input voltage on PC2). This is specified in PSDsoft Express as “Standby-On Indicator” (see SRAM Standby Mode (battery backup), page 193). The remaining four pins (TDI, TDO, TCK, TMS) on Port C are dedicated to the JTAG function and cannot be used for any other function. See JTAG ISP and JTAG Debug, page 195. Port C also supports the Open Drain output drive type options on pins PC2, PC3, PC4, and PC7 using the csiop Drive Select registers.uPSD33xx 184/231 Figure 76. Port C Structure Note: 1. Pull-up switches to VBAT when SRAM goes to battery back-up mode. 2. Optional function on a specific Port C pin. I/O PORT C LOGIC O U T P U T M U P X D B M U X DIRECTION DRIVE SELECT DATA OUT (MCUI/O) ENABLE OUT DATA IN (MCUI/O) PT OUTPUT ENABLE, .OE (JTAG STATE MACHINE AUTOMATICALLY CONTROLS OE FOR JTAG SIGNALS) OUTPUT ENABLE TYPICAL PIN, PORT C PSD MODULE RESET ONE of 6 CSIOP REGISTERS 8032 ADDRESS, DATA, CONTROL BUS 1 2 3 4 5 1 2 3 4 5 FROM OMC OUTPUT (MCELLBCx) STANDBY ON(2) FROM SRAM BACK-UP CIRCUIT FROM FLASH MEMORIES TO/FROM JTAG STATE MACHINE FROM PLD INPUT BUS FROM ANDOR ARRAY FROM OMC ALLOCATOR D CLR DIRECTION DRIVE (MCUI/O) DATA OUT 8032 WR RESET PSDsoft 8032 RD TO IMCs CSIOP REGISTERS Q Q Q DRIVE TYPE SELECT(2) 8032 DATA BITS 8032 DATA BIT PIN CMOS INPUT BUFFER NO HYSTERESIS VDD VDD/VBAT (1) VDD/VBAT (1) PIN OUTPUT 50k PULL-UP ONLY ON JTAG TDI, TMS, TCK SIGNALS TO SRAM BATTERY BACK-UP CIRCUIT(2) IMCC2, IMCC3, IMCC4, IMCC7 RDY/BSY(2) TDO, TSTAT(2), TERR(2) TDI, TMS, TCK AI09181185/231 uPSD33xx Port D Structure. Port D has two I/O pins (PD1, PD2) on 80-pin uPSD33xx devices, and just one pin (PD1) on 52-pin devices, supporting the following operating modes: ■ MCU I/O Mode ■ DPLD Output Mode for External Chip Selects, ECS1, ECS2. This does not consume OMCs in the GPLD. ■ PLD Input Mode – direct input to the PLD Input Bus available to DPLD and GPLD. Does not use IMCs See Figure 77., page 186 for detail. Port D pins can also be configured in PSDsoft as pins for other dedicated functions: – PD1 can be used as a common clock input to all 16 OMC Flip-flops (see OMCs, page 136) and also the Automatic Power-Down (APD), page 189. – PD2 can be used as a common chip select signal (CSI) for the Flash and SRAM memories on the PSD Module (see Chip Select Input (CSI), page 191). If driven to logic ’1’ by an external source, CSI will force all memories into standby mode regardless of what other internal memory select signals are doing on the PSD Module. This is specified in PSDsoft as “PSD Chip Select Input, CSI”. Port D also supports the Fast Slew Rate output drive type option using the csiop Drive Select registers.uPSD33xx 186/231 Figure 77. Port D Structure Note: 1. Optional function on a specific Port D pin. I/O PORT D LOGIC O U T P U T M U P X D B M U X DIRECTION DRIVE SELECT DATA OUT (MCUI/O) ENABLE OUT DATA IN (MCUI/O) PT OUTPUT ENABLE (.OE) OUTPUT ENABLE OUTPUT ENABLE TYPICAL PIN, PORT D PSD MODULE RESET ONE of 5 CSIOP REGISTERS 8032 ADDRESS, DATA, CONTROL BUS 1 2 1 2 3 4 5 FROM DPLD EXTERNAL CHIP (ECSx) FROM PLD INPUT BUS FROM ANDOR ARRAY FROM DPLD D CLR DIRECTION DRIVE (MCUI/O) DATA OUT 8032 WR RESET PSDsoft 8032 RD TO POWER MANAGEMENT AND PLD INPUT BUS CSIOP REGISTERS Q Q Q 8032 DRIVE TYPE SELECT DATA BITS 8032 DATA BIT PIN INPUT CMOS BUFFER NO HYSTERESIS VDD VDD PIN OUTPUT 1 = FAST SLEW RATE PD1. PIN, PD2.PIN DIRECTLY TO PLD INPUT BUS, NO IMC CSI(1) TO POWER MANAGEMENT CLKIN(1) AI09182187/231 uPSD33xx Power Management. The PSD Module offers configurable power saving options, and also a way to manage power to the SRAM (battery backup). These options may be used individually or in combinations. A top level description for these functions is given here, then more detailed descriptions will follow. – Zero-Power Memory: All memory arrays (Flash and SRAM) in the PSD Module are built with zero-power technology, which puts the memories into standby mode (~ zero DC current) when 8032 address signals are not changing. As soon as a transition occurs on any address input, the affected memory “wakes up”, changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve this memory standby mode when no inputs are changing—it happens automatically. Thus, the slower the 8032 clock, the lower the current consumption. Both PLDs (DPLD and GPLD) are also zeropower, but this is not the default condition. The 8032 must set a bit in one of the csiop PMMR registers at run-time to achieve zero-power. – Automatic Power-Down (APD): The APD feature allows the PSD Module to reach it’s lowest current consumption levels. If enabled, the APD counter will time-out when there is a lack of 8032 bus activity for an extended amount of time (8032 asleep). After time-out occurs, all 8032 address and data buffers on the PSD Module are shut down, preventing the PSD Module memories and potentially the PLDs from waking up from standby, even if address inputs are changing state because of noise or any external components driving the address lines. Since the actual address and data buffers are turned off, current consumption is even further reduced. Note: Non-address signals are still available to PLD inputs and will wake up the PLDs if these signals are changing state, but will not wake up the memories. The APD counter requires a relatively slow external clock input on pin PD1 that does stop when the 8032 goes to sleep mode. – Forced Power-Down (FPD): The MCU can put the PSD Module into Power-Down mode with the same results as using APD described above, but FPD does not rely on the APD counter. Instead, FPD will force the PSD Module into Power-Down mode when the MCU firmware sets a bit in one of the csiop PMMR registers. This is a good alternative to APD because no external clock is needed for the APD counter. – PSD Module Chip Select Input (CSI): This input on pin PD2 (80-pin devices only) can be used to disable the internal memories, placing them in standby mode even if address inputs are changing. This feature does not block any internal signals (the address and data buffers are still on but signals are ignored) and CSI does not disable the PLDs. This is a good alternative to using the APD counter, which requires an external clock on pin PD1. – Non-Turbo Mode: The PLDs can operate in Turbo or non-Turbo modes. Turbo mode has the shortest signal propagation delay, but consumes more current than non-Turbo mode. A csiop register can be written by the 8032 to select modes, the default mode is with Turbo mode enabled. In non-Turbo mode, the PLDs can achieve very low standby current (~ zero DC current) while no PLD inputs are changing, and the PLDs will even use less AC current when inputs do change compared to Turbo mode. When the Turbo mode is enabled, there is a significant DC current component AND the AC current component is higher than non-Turbo mode, as shown in Figure 85., page 202 (5V) and Figure 86., page 202 (3.3V). – Blocking Bits: Significant power savings can be achieved by blocking 8032 bus control signals (RD, WR, PSEN, ALE) from reaching PLD inputs, if these signals are not used in any PLD equations. Blocking is achieved by the 8032 writing to the “blocking bits” in csiop PMMR registers. Current consumption of the PLDs is directly related to the composite frequency of all transitions on PLD inputs, so blocking certain PLD inputs can significantly lower PLD operating frequency and power consumption (resulting in a lower frequency on the graphs of Figure 85., page 202 and Figure 86., page 202). – SRAM Backup Voltage: Pin PC2 can be configured in PSDsoft to accept an alternate DC voltage source (battery) to automatically retain the contents of SRAM when VDD drops below this alternate voltage. Note: It is recommended to prevent unused inputs from floating on Ports A, B, C, and D by pulling them up to VDD with a weak external resistor (100KΩ), or by setting the csiop Direction register to “output” at run-time for all unused inputs. This will prevent the CMOS input buffers of unused input pins from drawing excessive current. The csiop PMMR register definitions are shown in 117 through Table 119., page 188.uPSD33xx 188/231 Table 117. Power Management Mode Register PMMR0 (address = csiop + offset B0h) Note: All the bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the registers. 1. Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation. Table 118. Power Management Mode Register PMMR2 (address = csiop + offset B4h) Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the registers. 1. Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation. Table 119. Power Management Mode Register PMMR3 (address = csiop + offset C7h) Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the registers. Bit 0 X 0 Not used, and should be set to zero. Bit 1 APD Enable 0 Automatic Power Down (APD) counter is disabled. 1 APD counter is enabled Bit 2 X 0 Not used, and should be set to zero. Bit 3 PLD Turbo Disable 0 = on PLD Turbo mode is on 1 = off PLD Turbo mode is off, saving power. Bit 4 Blocking Bit, CLKIN to PLDs(1) 0 = on CLKIN (pin PD1) to the PLD Input Bus is not blocked. Every transition of CLKIN powers-up the PLDs. 1 = off CLKIN input to PLD Input Bus is blocked, saving power. But CLKIN still goes to APD counter. Bit 5 Blocking Bit, CLKIN to OMCs Only(1) 0 = on CLKIN input is not blocked from reaching all OMC’s common clock inputs. 1 = off CLKIN input to common clock of all OMCs is blocked, saving power. But CLKIN still goes to APD counter and all PLD logic besides the common clock input on OMCs. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero. Bit 0 X 0 Not used, and should be set to zero. Bit 1 X 0 Not used, and should be set to zero. Bit 2 Blocking Bit, WR to PLDs(1) 0 = on 8032 WR input to the PLD Input Bus is not blocked. 1 = off 8032 WR input to PLD Input Bus is blocked, saving power. Bit 3 Blocking Bit, RD to PLDs(1) 0 = on 8032 RD input to the PLD Input Bus is not blocked. 1 = off 8032 RD input to PLD Input Bus is blocked, saving power. Bit 4 Blocking Bit, PSEN to PLDs(1) 0 = on 8032 PSEN input to the PLD Input Bus is not blocked. 1 = off 8032 PSEN input to PLD Input Bus is blocked, saving power. Bit 5 Blocking Bit, ALE to PLDs(1) 0 = on 8032 ALE input to the PLD Input Bus is not blocked. 1 = off 8032 ALE input to PLD Input Bus is blocked, saving power. Bit 5 Blocking Bit, PC7 to PLDs(1) 0 = on Pin PC7 input to the PLD Input Bus is not blocked. 1 = off Pin PC7 input to PLD Input Bus is blocked, saving power. Bit 7 X 0 Not used, and should be set to zero. Bit 0 X 0 Not used, and should be set to zero. Bit 1 FORCE_PD 0 = off APD counter will cause Power-Down Mode if APD is enabled. 1 = on Power-Down mode will be entered immediately regardless of APD activity. Bit 3-7 X 0 Not used, and should be set to zero.189/231 uPSD33xx Automatic Power-Down (APD). The APD unit shown in Figure 63., page 157 puts the PSD Module into power-down mode by monitoring the activity of the 8032 Address Latch Enable (ALE) signal. If the APD unit is enabled by writing a logic ’1’ to Bit 1 of the csiop PMMR0 register, and if ALE signal activity has stopped (8032 in sleep mode), then the four-bit APD counter starts counting up. If the ALE signal remains inactive for 15 clock periods of the CLKIN signal (pin PD1), then the APD counter will reach maximum count and the power down indicator signal (PDN) goes to logic ’1’ forcing the PSD Module into power-down mode. During this time, all buffers on the PSD Module for 8032 address and data signals are disabled in silicon, preventing the PSD Module memories from waking up from stand-by mode, even if noise or other devices are driving the address lines. The PLDs will also stay in standby mode if the PLDs are in non-Turbo mode and if all other PLD inputs (non-address signals) are static. However, if the ALE signal has a transition before the APD counter reaches max count, the APD counter is cleared to zero and the PDN signal will not go active, preventing power-down mode. To prevent unwanted APD time-outs during normal 8032 operation (not sleeping), it is important to choose a clock frequency for CLKIN that will NOT produce 15 or more pulses within the longest period between ALE transitions. A 32768 Hz clock signal is quite often an ideal frequency for CLKIN and APD, and this frequency is often available on external supervisor or real-time clock devices. The “PDN” power-down indicator signal is available to the PLD input bus to use in any PLD equations if desired. The user may want to send this signal as a PLD output to an external device to indicate the PSD Module is in power-down mode. PSDsoft Express automatically includes the “PDN” signal in the DPLD chip select equations for FSx, CSBOOTx, RS0, and CSIOP. The following should be kept in mind when the PSD Module is in power-down mode: – 8032 address and data bus signals are blocked from all memories and both PLDs. – The PSD Module comes out of power-down mode when: ALE starts pulsing again, or the CSI input on pin PD2 transitions from logic ’1’ to logic '0,' or the PSD Module reset signal, RST, transitions from logic ’0’ to logic '1.' – Various signals can be blocked (prior to power-down mode) from entering the PLDs by using “blocking bits” in csiop PMMR registers. – All memories enter standby mode, and the state of the PLDs and I/O Ports are unchanged (if no PLD inputs change). Table 121., page 194 shows the effects of powerdown mode on I/O pins while in various operating modes. – The 8032 Ports 1,3, and 4 on the MCU Module are not affected at all by power-down mode in the PSD Module. – Power-down standby current given in the AC specifications for PSD Module assume there are no transitions on any unblocked PLD input, and there are no output pins driving any loads. The APD counter will count whenever Bit 1 of csiop PMMR0 register is set to logic '1,' and when the ALE signal is steady at either logic ’1’ or logic ’0’ (not transitioning). Figure 79., page 191 shows the flow leading up to power-down mode. The only action required in PSDsoft Express to enable APD mode is to select the pin function “Common Clock Input, CLKIN” before programming with JTAG.uPSD33xx 190/231 Forced Power Down (FDP). An alternative to APD is FPD. The resulting power-savings is the same, but the PDN signal in Figure 78., page 191 is set and Power-Down mode is entered immediately when firmware sets the FORCE_PD Bit to logic '1' in the csiop Register PMMR3 (Bit 1). FPD will override APD counter activity when FORCE_PD is set. No external clock source for the APD counter is needed. The FORCE_PD Bit is cleared only by a reset condition. Caution must be used when implementing FPD because code memory goes off-line as soon as PSD Module Power-Down mode is entered, leaving the MCU with no instruction stream to execute. The MCU Module must put itself into Power-Down mode after it puts the PSD Module into PowerDown Mode. How can it do this if code memory goes off-line? The answer is the Pre-Fetch Queue (PFQ) in the MCU Module. By using the instruction scheme shown in the 8051 assembly code example in Table 120, the PFQ will be loaded with the final instructions to command the MCU Module to Power Down mode after the PDS Module goes to Power-Down mode. In this case, even though the code memory goes off-line in the PSD Module, the last few MCU instruction are sourced from the PFQ. Table 120. Forced Power-Down Example PDOWN: ANL A8h, #7Fh ; disable all interrupts ORL 9Dh, #C0h ; ensure PFQ and BC are enabled MOV DPTR, #xxC7 ; load XDATA pointer to select PMMR3 register (xx = base ; address of csiop registers) CLR A ; clear A JMP LOOP ; first loop - fill PFQ/BQ with Power Down instructions NOP ; second loop - fetch code from PFQ/BC and set Power- ; Down bits for PSD Module and then MCU Module LOOP: MOVX @DPTR, A ; set FORCE_PD Bit in PMMR3 in PSD Module in second ; loop MOV 87h, A ; set PD Bit in PCON Register in MCU Module in second ; loop MOV A, #02h ; set power-down bit in the A Register, but not in PMMR3 or ; PCON yet in first loop JMP LOOP ; uPSD enters into Power-Down mode in second loop191/231 uPSD33xx Figure 78. Automatic Power Down (APD) Unit Figure 79. Power-Down Mode Flow Chart Chip Select Input (CSI). Pin PD2 of Port D can optionally be configured in PSDsoft Express as the PSD Module Chip Select Input, CSI, which is an active-low logic input. By default, pin PD2 does not have the CSI function. When the CSI function is specified in PSDsoft Express, the CSI signal is automatically included in DPLD chip select equations for FSx, CSBOOTx, RS0, and CSIOP. When the CSI pin is driven to logic ’0’ from an external device, all of these memories will be available for READ and WRITE operations. When CSI is driven to logic '1,' none of these memories are available for selection, regardless of the address activity from the 8032, reducing power consumption. The state of the PLD and port I/O pins are not changed when CSI goes to logic ’1’ (disabled). PMMR0, BIT 1 (APD EN) 8032 ALE PSD MODULE RST_ CSI (pin PD2) CLKIN (pin PD1) PDN OMC OUTPUTS FSx CSBOOTx RS0 CSIOP 8032 DATA FROM MCU MODULE 8032 ADDR FROM MCU MODULE PDN PDN CSI PMMR3, BIT 1 (FORCE_PD) ENABLE 1 = FOUND TRANSITION 1 = FOUND EDGE CLEAR FULL COUNT DPLD CHIP SELECT EQUATIONS GPLD TRANSITION DETECTION EDGE DETECTION 4-BIT APD UP-COUNTER ENABLE CLK 1 = POWER DOWN MODE ENABLE PSD MODULE LINE BUFFERS 8032 DATA 8032 ADDR WHEN CSI FUNCTION IS SPECIFIED IN PSDSOFT EXPRESS, CSI IS PART OF EQUATIONS FOR FSx, CSBOOTx, RS0, and CSIOP AI06608B Enable APD. Set PMMR0, Bit 1 = 1 RESET OPTIONAL. Disable desired inputs to PLDs by setting PMMR0 bits 4 and 5, and PMMR2 bits 2 through 6 ALE idle for 15 CLKIN clocks? PDN = 1, PSD Module in PowerDown Mode YES NO AI09183uPSD33xx 192/231 PLD Non-Turbo Mode. The power consumption and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in the csiop PMMR0 register. By setting this bit to logic '1,' the Turbo mode is turned off and both PLDs consume only stand-by current when ALL PLD inputs have no transitions for an extended time (65ns for 5V devices, 100ns for 3.3 V devices), significantly reducing current consumption. The PLDs will latch their outputs and go to standby, drawing very little current. When Turbo mode is off, PLD propagation delay time is increased as shown in the AC specifications for the PSD Module. Since this additional propagation delay also effects the DPLD, the response time of the memories on the PSD Module is also lengthened by that same amount of time. If Turbo mode is off, the user should add an additional wait state to the 8032 BUSCON SFR register if the 8032 clock frequency is higher that a particular value. Please refer to Table 36., page 64 in the MCU Module section. The default state of the Turbo Bit is logic '0,' meaning Turbo mode is on by default (after power-up and reset conditions) until it is turned off by the 8032 writing to PMMR0. PLD Current Consumption. Figure 85., page 202 and Figure 86., page 202 (5V and 3.3V devices respectively) show the relationship between PLD current consumption and the composite frequency of all the transitions on PLD inputs, indicating that a higher input frequency results in higher current consumption. Current consumption of the PLDs have a DC component and an AC component. Both need to be considered when calculating current consumption for a specific PLD design. When Turbo mode is on, there is a linear relationship between current and frequency, and there is a substantial DC current component consumed by the PSD Module when there are no transitions on PLD inputs (composite frequency is zero). The magnitude of this DC current component is directly proportional to how many product terms are used in the equations of both PLDs. PSDsoft Express generates a “fitter” report that specifies how many product terms were used in a design out of a total of 186 available product terms. Figure 85., page 202 and Figure 86., page 202 both give two examples, one with 100% of the 186 product terms used, and another with 25% of the 186 product terms used. Turbo Mode Current Consumption. To determine the AC current component of the specific PLD design with Turbo mode on, the user will have to interpolate from the graph, given the number of product terms specified in the fitter report, and the estimated composite frequency of PLD input signal transitions. For the DC component (y-axis crossing), the user can calculate the number by multiplying the number of product terms used (from fitter report) times the DC current per product term specified in the DC specifications for the PSD Module. The total PLD current usage is the sum of its AC and DC components. Non-Turbo Mode Current Consumption. Notice in Figure 85., page 202 and Figure 86., page 202 that when Turbo mode is off, the DC current consumption is “zero” (just standby current) when the composite frequency of PLD input transitions is zero (no input transitions). Now moving up the frequency axis to consider the AC current component, current consumption remains considerably less than Turbo mode until PLD input transitions happen so rapidly that the PLDs do not have time to latch their outputs and go to standby between the transitions anymore. This is where the lines converge on the graphs, and current consumption becomes the same for PLD input transitions at this frequency and higher regardless if Turbo mode is on or off. To determine the current consumption of the PLDs with Turbo mode off, extrapolate the AC component from the graph based on number of product terms and input frequency. The only DC component in non-Turbo mode is the PSD Module standby current. The key to reducing PLD current consumption is to reduce the composite frequency of transitions on the PLD input bus, moving down the frequency scale on the graphs. One way to do this is to carefully select which signals are entering PLD inputs, not selecting high frequency signals if they are not used in PLD equations. Another way is to use PLD “Blocking Bits” to block certain signals from entering the PLD input bus.193/231 uPSD33xx PLD Blocking Bits. Blocking specific signals from entering the PLDs using bits of the csiop PMMR registers can further reduce PLD AC current consumption by lowering the effective composite frequency of inputs to the PLDs. Blocking 8032 Bus Control Signals. When the 8032 is active on the MCU Module, four bus control signals (RD, WR, PSEN, and ALE) are constantly transitioning to manage 8032 bus traffic. Each time one of these signals has a transition from logic ’1’ to '0,' or 0 to '1,' it will wake up the PLDs if operating in non-Turbo mode, or when in Turbo mode it will cause the affected PLD gates to draw current. If equations in the DPLD or GPLD do not use the signals RD, WR, PSEN, or ALE then these signals can be blocked which will reduce the AC current component substantially. These bus control signals are rarely used in DPLD equations because they are routed in silicon directly to the memory arrays of the PSD Module, bypassing the PLDs. For example, it is NOT necessary to qualify a memory chip select signal with an MCU write strobe, such as “fs0 = address range & !WR_”. Only “fs0 = address range” is needed. Each of the 8032 bus control signals may be blocked individually by writing to Bits 2, 3, 4, and 5 of the PMMR2 register shown in Table 118., page 188. Blocking any of these four bus control signals only prevents them from reaching the PLDs, but they will always go to the memories directly. However, sometimes it is necessary to use these 8032 bus control signals in the GPLD when creating interface signals to external I/O peripherals. But it is still possible to save power by dynamically unblocking the bus signals before reading/writing the external device, then blocking the signals after the communication is complete. The user can also block an input signal coming from pin PC7 to the PLD input bus if desired by writing to Bit 6 of PMMR2. Blocking Common Clock, CLKIN. The input CLKIN (from pin PD1) can be blocked to reduce current consumption. CLKIN is used as a common clock input to all OMC flip-flips, it is a general input to the PLD input bus, and it is used to clock the APD counter. In PSDsoft Express, the function of pin PD1 must be specified as “Common Clock Input, CLKIN” before programming the device with JTAG to get the CLKIN function. Bit 4 of PMMR0 can be set to logic ’1’ to block CLKIN from reaching the PLD input bus, but CLKIN will still reach the APD counter. Bit 5 of PMMR0 can be set to logic ’1’ to block CLKIN from reaching the OMC flip-flops only, but CLKIN is still available to the PLD input bus and the APD counter. See Table 117., page 188 for details. SRAM Standby Mode (battery backup). The SRAM on the PSD Module may optionally be backed up by an external battery (or other DC source) to make its contents non-volatile. This is achieved by connecting a battery to pin PC2 on Port C and selecting the “SRAM Standby” function for pin PC2 within PSDsoft Express. Automatic voltage supply cross-over circuitry is built into the PSD Module to switch SRAM supply to battery as soon as VDD drops below the voltage level of the battery. SRAM contents are protected while battery voltage is greater than 2.0V. Pin PC4 on Port C can be used as an output to indicate that a battery switch-over has occurred. This is configured in PSDsoft Express by selecting the “Standby On Indicator” option for pin PC4. PSD Module Reset Conditions The PSD Module receives a reset signal from the MCU Module. This reset signal is referred to as the “RST” input in PSD Module documentation, and it is active-low when asserted. The character of the RST signal generated from the MCU Module is described in SUPERVISORY FUNCTIONS, page 65. Upon power-up, and while RST is asserted, the PSD Module immediately loads its configuration from non-volatile bits to configure the PLDs and other items. PLD logic is operational and ready for use well before RST is de-asserted. The state of PLD outputs are determined by equations specified in PSDsoft Express. The Flash memories are reset to Read Array mode after any assertion of RST (even if a program or erase operation is occurring). Flash memory WRITE operations are automatically prevented while VDD is ramping up until it rises above the VLKO voltage threshold at which time Flash memory WRITE operations are allowed. Once the uPSD33xx is up and running, any subsequent reset operation is referred to as a warm reset, until power is turned off again. Some PSD Module functions are reset in different ways depending if the reset condition was caused from a power-up reset or a warm reset. Table 121., page 194 summarizes how PSD Module functions are affected by power-up and warm resets, as well as the affect of PSD Module powerdown mode (from APD). The I/O pins of PSD Module Ports A, B, C, and D do not have weak internal pull-ups.uPSD33xx 194/231 In MCU I/O mode, Latched Address Out mode, and Peripheral I/O mode, the pins of Ports A, B, C, and D become standard CMOS inputs during a reset condition. If no external devices are driving these pins during reset, then these inputs may float and draw excessive current. If low power consumption is critical during reset, then these floating inputs should be pulled up externally to VDD with a weak (100KΩ minimum) resistor. In PLD I/O mode, pins of Ports A, B, C, and D may also float during reset if no external device is driving them, and if there is no equation specified for the DPLD or GPLD to make them an output. In this case, a weak external pull-up resistor (100KΩ minimum) should be used on floating pins to avoid excessive current draw. The pins on Ports 1, 3, and 4 of the 8032 MCU module do have weak internal pull-ups and the inputs will not float, so no external pull-ups are needed. Table 121. Function Status During Power-Up Reset, Warm Reset, Power-down Mode Note: 1. VM register Bit 7 (PIO_EN) and Bit 0 (SRAM in 8032 program space) are cleared to zero at power-up and warm reset conditions. Port Configuration Power-Up Reset Warm Reset APD Power-down Mode MCU I/O Pins are in input mode Pins are in input mode Pin logic state is unchanged PLD I/O Pin logic is valid after internal PSD Module configuration bits are loaded. Happens long before RST is de-asserted Pin logic is valid and is determined by PLD logic equations Pin logic depends on inputs to PLD (8032 addresses are blocked from reaching PLD inputs during powerdown mode) Latched Address Out Mode Pins are High Impedance Pins are High Impedance Pins logic state not defined since 8032 address signals are blocked Peripheral I/O Mode Pins are High Impedance Pins are High Impedance Pins are High Impedance JTAG ISP and Debug JTAG channel is active and available JTAG channel is active and available JTAG channel is active and available Register Power-Up Reset Warm Reset APD Power-down Mode PMMR0 and PMMR2 Cleared to 00h Unchanged Unchanged Output of OMC Flip-flops Cleared to ’0’ Depends on .re and .pr equations Depends on .re and .pr equations VM Register(1) Initialized with value that was specified in PSDsoft Initialized with value that was specified in PSDsoft Unchanged All other csiop registers Cleared to 00h Cleared to 00h Unchanged195/231 uPSD33xx JTAG ISP and JTAG Debug. An IEEE 1149.1 serial JTAG interface is used on uPSD33xx devices for ISP (In-System Programming) of the PSD module, and also for debugging firmware on the MCU Module. IEEE 1149.1 Boundary Scan operations are not supported in the uPSD33xx. The main advantage of JTAG ISP is that a blank uPSD33xx device may be soldered to a circuit board and programmed with no involvement of the 8032, meaning that no 8032 firmware needs to be present for ISP. This is good for manufacturing, for field updates, and for easy code development in the lab. JTAG-based programmers and debuggers for uPSD33xx are available from STMicroelectronics and 3rd party vendors. ISP is different than IAP (In-Application Programming). IAP involves the 8032 to program Flash memory over any interface supported by the 8032 (e.g., UART, SPI, I2C), which is good for remote updates over a communication channel. uPSD33xx devices support both ISP and IAP. The entire PSD Module (Flash memory and PLD) may be programmed with JTAG ISP, but only the Flash memories may be programmed using IAP. JTAG Chaining Inside the Package. JTAG protocol allows serial “chaining” of more than one device in a JTAG chain. The uPSD33xx is assembled with a stacked die process combining the PSD Module (one die) and the MCU Module (the other die). These two die are chained together within the uPSD33xx package. The standard JTAG interface has four basic signals: ■ TDI - Serial data into device ■ TDO - Serial data out of device ■ TCK - Common clock ■ TMS - Mode Selection Every device that supports IEEE 1149.1 JTAG communication contains a Test Access Port (TAP) controller, which is a small state machine to manage JTAG protocol and serial streams of commands and data. Both the PSD Module and the MCU Module each contain a TAP controller. Figure 80 illustrates how these die are chained within a package. JTAG programming/test equipment will connect externally to the four IEEE 1149.1 JTAG pins on Port C. The TDI pin on the uPSD33xx package goes directly to the PSD Module first, then exits the PSD Module through TDO. TDO of the PSD Module is connected to TDI of the MCU Module. The serial path is completed when TDO of the MCU Module exits the uPSD33xx package through the TDO pin on Port C. The JTAG signals TCK and TMS are common to both modules as specified in IEEE 1149.1. When JTAG devices are chained, typically one devices is in BYPASS mode while another device is executing a JTAG operation. For the uPSD33xx, the PSD Module is in BYPASS mode while debugging the MCU Module, and the MCU Module is in BYPASS mode while performing ISP on the PSD Module. The RESET_IN input pin on the uPSD33xx package goes to the MCU Module, and this module will generate the RST reset signal for the PSD Module. These reset signals are totally independent of the JTAG TAP controllers, meaning that the JTAG channel is operational when the modules are held in reset. It is required to assert RESET_IN during ISP. STMicroelectronics and 3rd party JTAG ISP tools will automatically assert a reset signal during ISP. However, this reset signal must be connected to RESET_IN as shown in examples in Figure Figure 81., page 196 and Figure 82., page 198. Figure 80. JTAG Chain in uPSD33xx Package JTAG TDI JTAG TMS JTAG TCK JTAG TDO TDI TMS TCK TDO TDO TMS TCK TDI PC3 / TSTAT PC4 / TERR TSTAT TERR OPTIONAL JTAG TAP CONTROLLER JTAG TAP CONTROLLER RESET_IN OPTIONAL DEBUG RESET RST 8032 MCU MCU MODULE PSD MODULE MAIN FLASH MEMORY 2ND FLASH MEMORY PLD uPSD33XX IEEE 1149.1 AI09184uPSD33xx 196/231 In-System Programming. The ISP function can use two different configurations of the JTAG interface: ■ 4-pin JTAG: TDI, TDO, TCK, TMS ■ 6-pin JTAG: Signals above plus TSTAT, TERR At power-up, the four basic JTAG signals are all inputs, waiting for a command to appear on the JTAG bus from programming or test equipment. When the enabling command is received, TDO becomes an output and the JTAG channel is fully functional. The same command that enables the JTAG channel may optionally enable the two additional signals, TSTAT and TERR. 4-pin JTAG ISP (default). The four basic JTAG pins on Port C are enabled for JTAG operation at all times. These pins may not be used for other I/ O functions. There is no action needed in PSDsoft Express to configure a device to use 4-pin JTAG, as this is the default condition. No 8032 firmware is needed to use 4-pin ISP because all ISP functions are controlled from the external JTAG program/test equipment. Figure 81 shows recommended connections on a circuit board to a JTAG program/test tool using 4-pin JTAG. It is required to connect the RST output signal from the JTAG program/test equipment to the RESET_IN input on the uPSD33xx. The RST signal is driven by the equipment with an Open Drain driver, allowing other sources (like a push button) to drive RESET_IN without conflict. Note: The recommended pull-up resistors and decoupling capacitor are illustrated in Figure 81. Figure 81. Recommended 4-pin JTAG Connections Note: 1. For 5V uPSD33xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 5V system VDD. 2. For 3.3V uPSD33xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 3.3V system VCC. 3. This signal is driven by an Open-Drain output in the JTAG equipment, allowing more than one source to activate RESETIN. TMS - PC0 TCK - PC1 SRAM STBY or I/O - PC2 GENERAL I/O - PC3 GENERAL I/O - PC4 TDI - PC5 TDO - PC6 GENERAL I/O - PC7 JTAG CONN. 100k typical TMS TCK TDI TDO GENERAL I/O SIGNALS GND VCC (1,2) RST(3) uPSD33XX 0.01 µF CIRCUIT BOARD JTAG Programming or Test Equipment Connects Here 10k PUSH BUTTON or ANY OTHER RESET SOURCE DEBUG OPTIONAL TEST POINT 100k RESETIN AI09185197/231 uPSD33xx 6-pin JTAG ISP (optional). The optional signals TSTAT and TERR are programming status flags that can reduce programming time by as much as 30% compared to 4-pin JTAG because this status information does not have to be scanned out of the device serially. TSTAT and TERR must be used as a pair for 6-pin JTAG operation. – TSTAT (pin PC3) indicates when programming of a single Flash location is complete. Logic 1 = Ready, Logic 0 = busy. – TERR (pin PC4) indicates if there was a Flash programming error. Logic 1 = no error, Logic 0 = error. The pin functions for PC3 and PC4 must be selected as “Dedicated JTAG - TSTAT” and “Dedicated JTAG - TERR” in PSDsoft Express to enable 6-pin JTAG ISP. No 8032 firmware is needed to use 6-pin ISP because all ISP functions are controlled from the external JTAG program/test equipment. TSTAT and TERR are functional only when JTAG ISP operations are occurring, which means they are non-functional during JTAG debugging of the 8032 on the MCU Module. Programming times vary depending on the number of locations to be programmed and the JTAG programming equipment, but typical JTAG ISP programming times are 10 to 25 seconds using 6- pin JTAG. The signals TSTAT and TERR are not included in the IEEE 1149.1 specification. Figure 82., page 198 shows recommended connections on a circuit board to a JTAG program/test tool using 6-pin JTAG. It is required to connect the RST output signal from the JTAG program/test equipment to the RESET_IN input on the uPSD33xx. The RST signal is driven by the equipment with an Open Drain driver, allowing other sources (like a push button) to drive RESET_IN without conflict. Note: The recommended pull-up resistors and decoupling capacitor are illustrated in Figure 82.uPSD33xx 198/231 Figure 82. Recommended 6-pin JTAG Connections Note: 1. For 5V uPSD33xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 5V system VDD. 2. For 3.3V uPSD33xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 3.3V system VCC. 3. This signal is driven by an Open-Drain output in the JTAG equipment, allowing more than one source to activate RESET_IN. TMS - PC0 TCK - PC1 SRAM STBY or I/O - PC2 TSTAT - PC3 TERR - PC4 TDI - PC5 TDO - PC6 GENERAL I/O - PC7 JTAG CONN. 100k typical TMS TCK TDI TERR TSTAT TDO GENERAL I/O SIGNALS GND VCC (1,2) RST(3) uPSD33XX 0.01 µF CIRCUIT BOARD JTAG Programming or Test Equipment Connects Here 10k PUSH BUTTON or ANY OTHER RESET SOURCE DEBUG OPTIONAL TEST POINT 100k RESETIN AI09186199/231 uPSD33xx Recommended JTAG Connector. There is no industry standard JTAG connector. STMicroelectronics recommends a specific JTAG connector and pinout for uPSD3xxx so programming and debug equipment will easily connect to the circuit board. The user does not have to use this connector if there is a different connection scheme. The recommended connector scheme can accept a standard 14-pin ribbon cable connector (2 rows of 7 pins on 0.1” centers, 0.025” square posts, standard keying) as shown in Figure 83. See the STMicroelectronics “FlashLINK, FL-101 User Manual” for more information. Figure 83. Recommended JTAG Connector Chaining uPSD33xx Devices. It is possible to chain a uPSD33xx device with other uPSD33xx devices on a circuit board, and also chain with IEEE 1149.1 compliant devices from other manufacturers. Figure 84., page 200 shows a chaining example. The TDO of one device connects to the TDI of the next device, and so on. Only one device is performing JTAG operations at any given time while the other two devices are in BYPASS mode. Configuration for JTAG chaining can be made in PSDsoft Express by choosing “More than one device” when prompted about chaining devices. Notice in Figure 84., page 200 that the uPSD33xx devices are chained externally, but also be aware that the two die within each uPSD33xx device are chained internally. This internal chaining of die is transparent to the user and is taken care of by PSDsoft Express and 3rd party JTAG tool software. The example in Figure 84., page 200 also shows how to use 6-pin JTAG when chaining devices. The signals TSTAT and TERR are configured as open-drain type signals from PSDsoft Express. This facilitates a wired-OR connection of TSTAT signals from multiple uPSD33xx devices and also a wired-OR connection of TERR signals from those same multiple devices. PSDsoft Express puts TSTAT and TERR signals into open-drain mode by default, requiring external pull-up resistors. Click on 'Properties' in the JTAG-ISP window of PSDsoft Express to change to standard CMOS push-pull outputs if desired, but wired-OR logic is not possible in CMOS output mode. TDO TCK TMS VCC TDI GND JEN TERR GND GND RST TSTAT CNTL TRST 14 12 10 13 11 9 8 7 6 5 4 3 2 1 KEY WAY VIEW: Looking into face of shrouded male connector, with 0.025" posts on 0.1" centers. Connector reference: Molex 70247-1401 This connector accepts a 14-pin ribbon cable such as: • Samtec: HCSD-07-D-06.00-01-S-N • Digikey: M3CCK-14065-ND AI09187uPSD33xx 200/231 Figure 84. Example of Chaining uPSD33xx Devices Device 1 µPSD33XX uPSD33XX TMS TCK TDI TDO IEEE 1149.1 Compliant Device Device 2 Device N System Reset Circuitry TMS TCK TDI TDO TSTAT TERR CIRCUIT BOARD JTAG CONN. VCC TMS TCK TDI TSTAT TERR TDO RST GND 100K 100K 100K 100K 100K 10K 100K JTAG Programming or Test Equipment Connects Here Optional Optional TMS TCK TDI TDO TSTAT TERR AI09188201/231 uPSD33xx Debugging the 8032 MCU Module. The 8032 on the MCU module may be debugged in-circuit using the same four basic JTAG signals as used for JTAG ISP (TDI, TDO, TCK, TMS). The signals TSTAT and TERR are not needed for debugging, and they will not create a problem if they exist on the circuit board while debugging. The same connector specified in Figure 83., page 199 can be used for ISP or for 8032 debugging. There are 3rd party suppliers of uPSD33xx JTAG debugging equipment (check www.st.com/psm). These are small pods which connect to a PC (or notebook computer) using a USB interface, and they are driven by an 8032 Integrated Development Environment (IDE) running on the PC. Standard debugging features are provided through this JTAG interface such as single-step, breakpoints, trace, memory dump and fill, and others. There is also a dedicated Debug pin (shown in Figure 80., page 195) which can be configured as an output to trigger external devices upon a programmable internal event (e.g., breakpoint match), or the pin can be configured as an input so an external device can initiate an internal debug event (e.g., break execution). The Debug pin function is configured by the 8032 IDE debug software tool. See DEBUG UNIT, page 39 for more details. The Debug signal should always be pulled up externally with a weak pull-up (100K minimum) to VCC even if nothing is connected to it, as shown in Figure 81., page 196 and Figure 82., page 198. JTAG Security Setting. A programmable security bit in the PSD Module protects its contents from unauthorized viewing and copying. The security bit is set by clicking on the “Additional PSD Settings” box in the main flow diagram of PSDsoft Express, then choosing to set the security bit. Once a file with this setting is programmed into a uPSD33xx using JTAG ISP, any further attempts to communicate with the uPSD33xx using JTAG will be limited. Once secured, the only JTAG operation allowed is a full-chip erase. No reading or modifying Flash memory or PLD logic is allowed. Debugging operations to the MCU Module are also not allowed. The only way to defeat the security bit is to perform a JTAG ISP full-chip erase operation, after which the device is blank and may be used again. The 8032 on the MCU Module will always have access to PSM Module memory contents through the 8-bit 8032 data bus connecting the two die, even while the security bit is set. Initial Delivery State. When delivered from STMicroelectronics, uPSD33xx devices are erased, meaning all Flash memory and PLD configuration bits are logic '1.' Firmware and PLD logic configuration must be programmed at least the first time using JTAG ISP. Subsequent programming of Flash memory may be performed using JTAG ISP, JTAG debugging, or the 8032 may run firmware to program Flash memory (IAP).uPSD33xx 202/231 AC/DC PARAMETERS These tables describe the AD and DC parameters of the uPSD33xx Devices: ■ DC Electrical Specification ■ AC Timing Specification ■ PLD Timing – Combinatorial Timing – Synchronous Clock Mode – Asynchronous Clock Mode – Input Macrocell Timing ■ MCU Module Timing – READ Timing – WRITE Timing – Power-down and RESET Timing The following are issues concerning the parameters presented: – In the DC specification the supply current is given for different modes of operation. – The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figure 85 and Figure 86 show the PLD mA/MHz as a function of the number of Product Terms (PT) used. – In the PLD timing parameters, add the required delay when Turbo Bit is '0.' Figure 85. PLD ICC /Frequency Consumption (5V range) Figure 86. PLD ICC /Frequency Consumption (3V range) 0 10 20 30 40 60 70 80 90 100 110 VCC = 5V 50 0 10 15 5 20 25 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) ICC – (mA) TURBO ON (100%) TURBO ON (25%) TURBO OFF TURBO OFF PT 100% PT 25% AI02894 0 10 20 30 40 50 60 VCC = 3V 0 10 15 5 20 25 ICC – (mA) TURBO ON (100%) TURBO ON (25%) TURBO OFF TURBO OFF HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) PT 100% PT 25% AI03100203/231 uPSD33xx Table 122. PSD Module Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off) Conditions MCU Clock Frequency = 12MHz Highest Composite PLD input frequency (Freq PLD) = 8MHz MCU ALE frequency (Freq ALE) = 2MHz % Flash memory Access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational Modes % Normal = 40% % Power-down Mode = 60% Number of product terms used (from fitter report) = 45 PT % of total product terms = 45/182 = 24.7% Turbo Mode = Off Calculation (using typical values) ICC total = ICC(MCUactive) x %MCUactive + ICC(PSDactive) x %PSDactive + IPD(pwrdown) x %pwrdown ICC(MCUactive) = 20mA IPD(pwrdown) = 250uA ICC(PSDactive) = ICC(ac) + ICC(dc) = %flash x 2.5mA/MHz x Freq ALE + %SRAM x 1.5mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD) = 0.8 x 2.5mA/MHz x 2MHz + 0.15 x 1.5mA/MHz x 2MHz + 24mA = (4 + 0.45 + 24) mA = 28.45mA ICC total = 20mA x 40% + 28.45mA x 40% + 250uA x 60% = 8mA + 11.38mA + 150uA = 19.53mA This is the operating power with no Flash memory Erase or Program cycles in progress. Calculation is based on all I/O pins being disconnected and IOUT = 0mA.uPSD33xx 204/231 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 123. Absolute Maximum Ratings Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω) DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 124. Operating Conditions (5V Devices) Table 125. Operating Conditions (3.3V Devices) Symbol Parameter Min. Max. Unit TSTG Storage Temperature –65 125 °C TLEAD Lead Temperature during Soldering (20 seconds max.)(1) 235 °C VIO Input and Output Voltage (Q = VOH or Hi-Z) –0.5 6.5 V VCC Supply Voltage –0.5 6.5 V VPP Device Programmer Supply Voltage –0.5 14.0 V VESD Electrostatic Discharge Voltage (Human Body Model)(2) –2000 2000 V Symbol Parameter Min. Max. Unit VCC Supply Voltage 4.5 5.5 V TA Ambient Operating Temperature (industrial) –40 85 °C Ambient Operating Temperature (commercial) 0 70 °C Symbol Parameter Min. Max. Unit VCC Supply Voltage 3.0 3.6 V TA Ambient Operating Temperature (industrial) –40 85 °C Ambient Operating Temperature (commercial) 0 70 °C205/231 uPSD33xx Table 126. AC Signal Letters for Timing Note: Example: tAVLX = Time from Address Valid to ALE Invalid. Table 127. AC Signal Behavior Symbols for Timing Note: Example: tAVLX = Time from Address Valid to ALE Invalid. Figure 87. Switching Waveforms – Key A Address C Clock D Input Data I Instruction L ALE N RESET Input or Output P PSEN signal Q Output Data R RD signal W WR signal B VSTBY Output M Output Macrocell t Time L Logic Level Low or ALE H Logic Level High V Valid X No Longer a Valid Logic Level Z Float PW Pulse Width WAVEFORMS INPUTS OUTPUTS STEADY INPUT MAY CHANGE FROM HI TO LO MAY CHANGE FROM LO TO HI DON'T CARE OUTPUTS ONLY STEADY OUTPUT WILL BE CHANGING FROM HI TO LO WILL BE CHANGING LO TO HI CHANGING, STATE UNKNOWN CENTER LINE IS TRI-STATE AI03102uPSD33xx 206/231 Table 128. Major Parameters Parameter Test Conditions/Comments 5.0V Value 3.3V Value Unit Operating Voltage – 4.5 to 5.5 (PSD); 3.0 to 3.6 (MCU) 3.0 to 3.6 (PSD and MCU) V Operating Temperature – –40 to 85 –40 to 85 °C MCU Frequency 8MHz (min) for I2C 1 Min, 40 Max 1 Min, 40 Max MHz Active Current, Typical (20% of PLD used; 25°C operation) 40MHz Crystal, Turbo 50 40 mA 40MHz Crystal, Non-Turbo 48 38 mA 8MHz Crystal, Turbo 21 18 mA 8MHz Crystal, Non-Turbo 10 8 mA Idle Current, Typical (20% of PLD used; 25°C operation) 40MHz Crystal divided by 2048 internally. All interfaces are disabled. 16 11 mA Standby Current, Typical Power-down Mode needs reset to exit. 140 120 µA SRAM Backup Current, Typical If external battery is attached. 0.5 0.5 µA I/O Sink/Source Current, Ports A, B, C, and D VOL = 0.45V (max); VOH = 2.4V (min) IOL = 8 (max); IOH = –2 (min) IOL = 4 (max); IOH = –1 (min) mA I/O Sink/Source Current, Port 4 VOL = 0.6V (max); VOH = 2.4V (min) IOL = 10 (max); IOH = –10 (min) IOL = 10 (max); IOH = –10 (min) mA PLD Macrocells For registered or combinatorial logic 16 16 – PLD Inputs Inputs from pins, feedback, or MCU addresses 69 69 – PLD Outputs Output to pins or internal feedback 18 18 – PLD Propagation Delay, Typical, Turbo Mode PLD input to output 15 22 ns207/231 uPSD33xx Table 129. Preliminary MCU Module DC Characteristics Note: 1. Power supply (VCC) is always 3.0 to 3.6V for the MCU Module. VDD for the PSD Module may be 3V or 5V. 2. IPD (Power-down Mode) is measured with: XTAL1 = VSS; XTAL2 = NC; RESET = VCC; Port 0 = VCC; all other pins are disconnected. 3. ICC-CPU (Active Mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V, XTAL2 = NC; RESET = VSS; Port 0 = VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). 4. ICC-CPU (Idle Mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V, XTAL2 = NC; RESET = VCC; Port 0 = VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). All IP clocks are disabled. 5. I/O current = 0mA, all I/O pins are disconnected. Symbol Parameter Test Conditions Min. Typ. Max. Unit VCC Supply Voltage(1) 3.0 3.6 V VIH High Level Input Voltage (Ports 0, 1, 2, 3, 4, XTAL1, RESET) 5V Tolerant - max voltage 5.5V 3.0V < VCC < 3.6V 0.7VCC 5.5 V VIL Low Level Input Voltage (Ports 0, 1, 2, 3, 4, XTAL1, RESET) 3.0V < VCC < 3.6V VSS – 0.5 0.3VCC V VOL1 Output Low Voltage (Port 4) IOL = 10mA 0.6 V V VOL2 Output Low Voltage (Other Ports) IOL =5mA 0.6 V V VOH1 Output High Voltage (Ports 4 push-pull) IOH = –10mA 2.4 V V VOH2 Output High Voltage (Port 0 push-pull) IOH = –5mA 2.4 V V VOH3 Output High Voltage (Other Ports Bi-directional mode) IOH = –20µA 2.4 V V VOP XTAL Open Bias Voltage (XTAL1, XTAL2) IOL = 3.2mA 1.0 2.0 V IRST RESET Pin Pull-up Current (RESET) VIN = VSS –10 –55 uA IFR XTAL Feedback Resistor Current (XTAL1) XTAL1 = VCC; XTAL2 = VSS –20 50 uA IIHL1 Input High Leakage Current (Port 0) VSS < VIN < 5.5V –10 10 uA IIHL2 Input High Leakage Current (Port 1, 2, 3, 4) VIH = 2.3V –10 10 uA IILL Input Low Leakage Current (Port 1, 2, 3, 4) VIL < 0.5V –10 10 uA IPD (Note 2) Power-down Mode VCC = 3.6V 65 95 uA ICC-CPU (Note 3,4,5) Active - 12MHz VCC = 3.6V 14 20 mA Idle - 12MHz 10 12 mA Active - 24MHz VCC = 3.6V 19 30 mA Idle - 24MHz 13 17 mA Active - 40MHz VCC = 3.6V 26 40 mA Idle - 40MHz 17 22 mAuPSD33xx 208/231 Table 130. PSD Module DC Characteristics (with 5V VDD) Note: 1. Internal Power-down mode is active. 2. PLD is in non-Turbo mode, and none of the inputs are switching. 3. Please see Figure 85., page 202 for the PLD current calculation. 4. IOUT = 0mA Symbol Parameter Test Condition (in addition to those in Table 129., page 207) Min. Typ. Max. Unit VIH Input High Voltage 4.5V < VDD < 5.5V 2 VDD +0.5 V VIL Input Low Voltage 4.5V < VDD < 5.5V –0.5 0.8 V VLKO VDD (min) for Flash Erase and Program 2.5 4.2 V VOL Output Low Voltage IOL = 20uA, VDD = 4.5V 0.01 0.1 V IOL = 8mA, VDD = 4.5V 0.25 0.45 V VOH Output High Voltage Except VSTBY On IOH = –20uA, VDD = 4.5V 4.4 4.49 V IOH = –2mA, VDD = 4.5V 2.4 3.9 V VOH1 Output High Voltage VSTBY On IOH1 = 1uA VSTBY – 0.8 V VSTBY SRAM Stand-by Voltage 2.0 VDD V ISTBY SRAM Stand-by Current VDD = 0V 0.5 1 uA IIDLE Idle Current (VSTBY input) VDD > VSTBY –0.1 0.1 uA VDF SRAM Data Retention Voltage Only on VSTBY 2 VDD – 0.2 V ISB Stand-by Supply Current for Power-down Mode CSI > VDD – 0.3V (Notes 1,2) 120 250 uA ILI Input Leakage Current VSS < VIN < VDD –1 ±0.1 1 uA ILO Output Leakage Current 0.45 < VOUT < VDD –10 ±5 10 uA ICC (DC) (Note 4) Operating Supply Current PLD Only PLD_TURBO = Off, f = 0MHz (Note 4) 0 uA/PT PLD_TURBO = On, f = 0MHz 400 700 uA/PT Flash memory During Flash memory WRITE/Erase Only 15 30 mA Read only, f = 0MHz 0 0 mA SRAM f = 0MHz 0 0 mA ICC (AC) (Note 4) PLD AC Adder Note 3 Flash memory AC Adder 1.5 2.5 mA/ MHz SRAM AC Adder 1.5 3.0 mA/ MHz209/231 uPSD33xx Table 131. PSD Module DC Characteristics (with 3.3V VDD) Note: 1. Internal PD is active. 2. PLD is in non-Turbo mode, and none of the inputs are switching. 3. Please see Figure 86., page 202 for the PLD current calculation. 4. IOUT = 0mA Symbol Parameter Test Condition (in addition to those in Table 129., page 207) Min. Typ. Max. Unit VIH High Level Input Voltage 3.0V < VDD < 3.6V 0.7VDD VDD +0.5 V VIL Low Level Input Voltage 3.0V < VDD < 3.6V –0.5 0.8 V VLKO VDD (min) for Flash Erase and Program 1.5 2.2 V VOL Output Low Voltage IOL = 20uA, VDD = 3.0V 0.01 0.1 V IOL = 4mA, VDD = 3.0V 0.15 0.45 V VOH Output High Voltage Except VSTBY On IOH = –20uA, VDD = 3.0V 2.9 2.99 V IOH = –1mA, VDD = 3.0V 2.7 2.8 V VOH1 Output High Voltage VSTBY On IOH1 = 1uA VSTBY – 0.8 V VSTBY SRAM Stand-by Voltage 2.0 VDD V ISTBY SRAM Stand-by Current VDD = 0V 0.5 1 uA IIDLE Idle Current (VSTBY input) VDD > VSTBY –0.1 0.1 uA VDF SRAM Data Retention Voltage Only on VSTBY 2 VDD – 0.2 V ISB Stand-by Supply Current for Power-down Mode CSI > VDD – 0.3V (Notes 1,2) 50 100 uA ILI Input Leakage Current VSS < VIN < VDD –1 ±0.1 1 uA ILO Output Leakage Current 0.45 < VIN < VDD –10 ±5 10 uA ICC (DC) (Note 4) Operating Supply Current PLD Only PLD_TURBO = Off, f = 0MHz (Note 2) 0 uA/PT PLD_TURBO = On, f = 0MHz 200 400 uA/PT Flash memory During Flash memory WRITE/Erase Only 10 25 mA Read only, f = 0MHz 0 0 mA SRAM f = 0MHz 0 0 mA ICC (AC) (Note 4) PLD AC Adder Note 3 Flash memory AC Adder 1.0 1.5 mA/ MHz SRAM AC Adder 0.8 1.5 mA/ MHzuPSD33xx 210/231 Figure 88. External PSEN/READ Cycle (80-pin Device Only) Table 132. External PSEN or READ Cycle AC Characteristics (3V or 5V Device) Note: 1. BUSCON Register is configured for 4 PFQCLK. 2. Refer to Table 133 for “n” and “m” values. Table 133. n, m, and x, y Values Symbol Parameter 40MHz Oscillator(1) Variable Oscillator 1/tCLCL = 8 to 40MHz Unit Min Max Min Max tLHLL ALE pulse width 17 tCLCL – 8 ns tAVLL Address setup to ALE 13 tCLCL – 12 ns tLLAX Address hold after ALE 7.5 0.5tCLCL – 5 ns tLLPL ALE to PSEN or RD 7.5 0.5tCLCL – 5 ns tPLPH PSEN or RD pulse width(2) 40 ntCLCL – 10 ns tPXIX Input instruction/data hold after PSEN or RD 2 2 ns tPHIZ Input instruction/data float after PSEN or RD 10.5 0.5tCLCL – 2 ns tPXAV Address hold after PSEN or RD 7.5 0.5tCLCL – 5 ns tAVIV Address to valid instruction/data in(2) 70 mtCLCL – 5 ns tAZPL Address float to PSEN or RD –2 –2 ns # of PFQCLK in BUSCON Reg. PSEN (code) Cycle READ Cycle WRITE Cycle nmnmx y 3 12- - - - 4 232321 5 343432 6 454543 7 - - 5654 tAVLL tPLPH tPXIZ tAVIV211/231 uPSD33xx Figure 89. External WRITE Cycle (80-pin Device Only) Table 134. External WRITE Cycle AC Characteristics (3V or 5V Device) Note: 1. BUSCON Register is configured for 4 PFQCLK. 2. Refer to Table 135, page 151 for “n” and “m” values. Table 135. External Clock Drive Symbol Parameter 40MHz Oscillator(1) Variable Oscillator 1/tCLCL = 8 to 40MHz Unit Min Max Min Max tLHLL ALE pulse width 17 tCLCL – 8 ns tAVLL Address Setup to ALE 13 tCLCL – 12 ns tLLAX Address hold after ALE 7.5 0.5tCLCL – 5 ns tWLWH WR pulse width(2) 40 xtCLCL – 10 ns tLLWL ALE to WR 7.5 0.5tCLCL – 5 ns tAVWL Address valid to WR 27.5 1.5tCLCL – 10 ns tWHLH WR High to ALE High 6.5 14.5 0.5tCLCL – 6 0.5tCLCL + 2 ns tQVWH Data setup before WR(y) 20 ytCLCL – 5 ns tWHQX Data hold after WR 6.5 14.5 0.5tCLCL – 6 0.5tCLCL + 2 ns Symbol Parameter(1) 40MHz Oscillator Variable Oscillator 1/tCLCL = 8 to 40MHz Unit Min Max Min Max tCLCL Oscillator period 25 125 ns tCHCX High time 10 tCLCL – tCLCX ns tCLCX Low time 10 tCLCL – tCLCX ns tCLCH Rise time 10 ns tCHCL Fall time 10 ns MCU A8 - A11 MCU AD0 - AD7 ALE WR PSEN A8-A11 A8-A11 tLLWL tWLWH tAVLL tLHLL tQVWH A0-A7 DATA OUT A0-A7 INSTR IN tLLAX tAVWL tWHQX tWHLH AI07877uPSD33xx 212/231 Table 136. A/D Analog Specification Note: 1. fIN 2kHz, ACLK = 8MHz, AVREF = VCC = 3.3V 2. AVREF = VCC in 52-pin package. Symbol Parameter Test Conditions(1) Min. Typ. Max. Unit IDD Normal Input = AVREF 4.0 mA Power-down 40 uA AVIN Analog Input Voltage GND AVREF V AVREF(2) Analog Reference Voltage 3.6 V Accuracy Resolution 10 bits INL Integral Nonlinearity Input = 0 to AVREF (V) FOSC ≤ 32MHz ±2 LSB DNL Differential Nonlinearity Input = 0 to AVREF (V) FOSC ≤ 32MHz ±2 LSB SNR Signal to Noise Ratio fSAMPLE = 500ksps 50 54 dB SNDR Signal to Noise Distortion Ratio 48 52 dB ACLK ADC Clock 2 8 16 MHz tC Conversion Time 8MHz 1 4 8 µs tCAL Power-up Time Calibration Time 16 ms fIN Analog Input Frequency 60 kHz THD Total Harmonic Distortion 50 54 dB213/231 uPSD33xx Figure 90. Input to Output Disable / Enable Table 137. CPLD Combinatorial Timing (5V PSD Module) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only) Table 138. CPLD Combinatorial Timing (3V PSD Module) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only) Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew rate(1) Unit tPD(2) CPLD Input Pin/Feedback to CPLD Combinatorial Output 20 + 2 + 10 – 2 ns tEA CPLD Input to CPLD Output Enable 21 + 10 – 2 ns tER CPLD Input to CPLD Output Disable 21 + 10 – 2 ns tARP CPLD Register Clear or Preset Delay 21 + 10 – 2 ns tARPW CPLD Register Clear or Preset Pulse Width 10 + 10 ns tARD CPLD Array Delay Any macrocell 11 + 2 ns Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew rate(1) Unit tPD(2) CPLD Input Pin/Feedback to CPLD Combinatorial Output 35 + 4 + 20 – 6 ns tEA CPLD Input to CPLD Output Enable 38 + 20 – 6 ns tER CPLD Input to CPLD Output Disable 38 + 20 – 6 ns tARP CPLD Register Clear or Preset Delay 35 + 20 – 6 ns tARPW CPLD Register Clear or Preset Pulse Width 18 + 20 ns tARD CPLD Array Delay Any macrocell 20 + 4 ns tER tEA INPUT INPUT TO OUTPUT ENABLE/DISABLE AI02863uPSD33xx 214/231 Figure 91. Synchronous Clock Mode Timing – PLD Table 139. CPLD Macrocell Synchronous Clock Mode Timing (5V PSD Module) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL.105 3. Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew rate(1) Unit fMAX Maximum Frequency External Feedback 1/(tS+tCO) 40.0 MHz Maximum Frequency Internal Feedback (fCNT) 1/(tS+tCO–10) 66.6 MHz Maximum Frequency Pipelined Data 1/(tCH+tCL) 83.3 MHz tS Input Setup Time 12 + 2 + 10 ns tH Input Hold Time 0 ns tCH Clock High Time Clock Input 6 ns tCL Clock Low Time Clock Input 6 ns tCO Clock to Output Delay Clock Input 13 – 2 ns tARD CPLD Array Delay Any macrocell 11 + 2 ns tMIN Minimum Clock Period(2) tCH+tCL 12 ns tCH tCL tCO tS tH CLKIN INPUT REGISTERED OUTPUT AI02860215/231 uPSD33xx Table 140. CPLD Macrocell Synchronous Clock Mode Timing (3V PSD Module) Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL. Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew rate(1) Unit fMAX Maximum Frequency External Feedback 1/(tS+tCO) 23.2 MHz Maximum Frequency Internal Feedback (fCNT) 1/(tS+tCO–10) 30.3 MHz Maximum Frequency Pipelined Data 1/(tCH+tCL) 40.0 MHz tS Input Setup Time 20 + 4 + 15 ns tH Input Hold Time 0 ns tCH Clock High Time Clock Input 15 ns tCL Clock Low Time Clock Input 10 ns tCO Clock to Output Delay Clock Input 23 – 6 ns tARD CPLD Array Delay Any macrocell 20 + 4 ns tMIN Minimum Clock Period(2) tCH+tCL 25 nsuPSD33xx 216/231 Figure 92. Asynchronous RESET / Preset Figure 93. Asynchronous Clock Mode Timing (Product Term Clock) Table 141. CPLD Macrocell Asynchronous Clock Mode Timing (5V PSD Module) Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew Rate Unit fMAXA Maximum Frequency External Feedback 1/(tSA+tCOA) 38.4 MHz Maximum Frequency Internal Feedback (fCNTA) 1/(tSA+tCOA–10) 62.5 MHz Maximum Frequency Pipelined Data 1/(tCHA+tCLA) 71.4 MHz tSA Input Setup Time 7 + 2 + 10 ns tHA Input Hold Time 8 ns tCHA Clock Input High Time 9 + 10 ns tCLA Clock Input Low Time 9 + 10 ns tCOA Clock to Output Delay 21 + 10 – 2 ns tARDA CPLD Array Delay Any macrocell 11 + 2 ns tMINA Minimum Clock Period 1/fCNTA 16 ns tARP REGISTER OUTPUT tARPW RESET/PRESET INPUT AI02864 tCHA tCLA tCOA tSA tHA CLOCK INPUT REGISTERED OUTPUT AI02859217/231 uPSD33xx Table 142. CPLD Macrocell Asynchronous Clock Mode Timing (3V PSD Module) Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew Rate Unit fMAXA Maximum Frequency External Feedback 1/(tSA+tCOA) 21.7 MHz Maximum Frequency Internal Feedback (fCNTA) 1/(tSA+tCOA–10) 27.8 MHz Maximum Frequency Pipelined Data 1/(tCHA+tCLA) 33.3 MHz tSA Input Setup Time 10 + 4 + 15 ns tHA Input Hold Time 12 ns tCHA Clock High Time 17 + 15 ns tCLA Clock Low Time 13 + 15 ns tCOA Clock to Output Delay 31 + 15 – 6 ns tARD CPLD Array Delay Any macrocell 20 + 4 ns tMINA Minimum Clock Period 1/fCNTA 36 nsuPSD33xx 218/231 Figure 94. Input Macrocell Timing (Product Term Clock) Table 143. Input Macrocell Timing (5V PSD Module) Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX. Table 144. Input Macrocell Timing (3V PSD Module) Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX. Symbol Parameter Conditions Min Max PT Aloc Turbo Off Unit tIS Input Setup Time (Note 1) 0 ns tIH Input Hold Time (Note 1) 15 + 10 ns tINH NIB Input High Time (Note 1) 9 ns tINL NIB Input Low Time (Note 1) 9 ns tINO NIB Input to Combinatorial Delay (Note 1) 34 + 2 + 10 ns Symbol Parameter Conditions Min Max PT Aloc Turbo Off Unit tIS Input Setup Time (Note 1) 0 ns tIH Input Hold Time (Note 1) 25 + 15 ns tINH NIB Input High Time (Note 1) 12 ns tINL NIB Input Low Time (Note 1) 12 ns tINO NIB Input to Combinatorial Delay (Note 1) 43 + 4 + 15 ns tINH tINL tINO tIH tIS PT CLOCK INPUT OUTPUT AI03101219/231 uPSD33xx Table 145. Program, WRITE and Erase Times (5V, 3V PSD Modules) Note: 1. Programmed to all zero before erase. 2. Typical after 100K program/erase cycle is 5 seconds. 3. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. Symbol Parameter Min. Typ. Max. Unit Flash Program 8.5 s Flash Bulk Erase(1) (pre-programmed) 3(2) 10 s Flash Bulk Erase (not pre-programmed) 5 s tWHQV3 Sector Erase (pre-programmed) 1 10 s tWHQV2 Sector Erase (not pre-programmed) 2.2 s tWHQV1 Byte Program 14 150 µs Program/Erase Cycles (per Sector) 100,000 cycles PLD Program/Erase Cycles 1000 cycles tWHWLO Sector Erase Time-Out 100 µs tQ7VQV DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)(3) 30 nsuPSD33xx 220/231 Figure 95. Peripheral I/O READ Timing Table 146. Port A Peripheral Data Mode READ Timing (5V PSD Module) Note: 1. Any input used to select Port A Data Peripheral Mode. 2. Data is already stable on Port A. Table 147. Port A Peripheral Data Mode READ Timing (3V PSD Module) Note: 1. Any input used to select Port A Data Peripheral Mode. 2. Data is already stable on Port A. Symbol Parameter Conditions Min Max Turbo Off Unit tAVQV–PA Address Valid to Data Valid (Note 1) 37 + 10 ns tSLQV–PA CSI Valid to Data Valid 27 + 10 ns tRLQV–PA RD to Data Valid (Note 2) 32 ns tDVQV–PA Data In to Data Out Valid 22 ns tRHQZ–PA RD to Data High-Z 23 ns Symbol Parameter Conditions Min Max Turbo Off Unit tAVQV–PA Address Valid to Data Valid (Note 1) 50 + 20 ns tSLQV–PA CSI Valid to Data Valid 37 + 20 ns tRLQV–PA RD to Data Valid (Note 2) 45 ns tDVQV–PA Data In to Data Out Valid 38 ns tRHQZ–PA RD to Data High-Z 36 ns tRLQV (PA) tDVQV (PA) tRHQZ (PA) tSLQV (PA) tAVQV (PA) ADDRESS DATA VALID ALE A/D BUS RD DATA ON PORT A CSI AI06610221/231 uPSD33xx Figure 96. Peripheral I/O WRITE Timing Table 148. Port A Peripheral Data Mode WRITE Timing (5V PSD Module) Note: 1. Data stable on Port 0 pins to data on Port A. Table 149. Port A Peripheral Data Mode WRITE Timing (3V PSD Module) Note: 1. Data stable on Port 0 pins to data on Port A. Table 150. Supervisor Reset and LVD Note: 1. 25µs minimum to abort a Flash memory program or erase cycle in progress. 2. As FOSC decreases, tRST_ACTV increases. Example: tRST_ACTV = 50ms when FOSC = 8MHz. Symbol Parameter Conditions Min Max Unit tWLQV–PA WR to Data Propagation Delay 25 ns tDVQV–PA Data to Port A Data Propagation Delay (Note 1) 22 ns tWHQZ–PA WR Invalid to Port A Tri-state 20 ns Symbol Parameter Conditions Min Max Unit tWLQV–PA WR to Data Propagation Delay 42 ns tDVQV–PA Data to Port A Data Propagation Delay (Note 1) 38 ns tWHQZ–PA WR Invalid to Port A Tri-state 33 ns Symbol Parameter Conditions Min Typ Max Unit tRST_LO_IN Reset Input Duration 1(1) µs tRST_ACTV Generated Reset Duration fOSC = 40MHz 10(2) ms tRST_FIL Reset Input Spike Filter 1 µs VRST_HYS Reset Input Hysteresis VCC = 3.3V 0.1 V VRST_THRESH LVD Trip Threshold VCC = 3.3V 2.4 2.6 2.8 V tDVQV (PA) tWLQV (PA) tWHQZ (PA) A/D BUS ADDRESS DATA OUT WR PORT A DATA OUT ALE AI06611uPSD33xx 222/231 Table 151. VSTBYON Definitions Timing (5V, 3V PSD Modules) Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms. Figure 97. ISC Timing Table 152. ISC Timing (5V PSD Module) Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode. 2. For Program or Erase PLD only. Symbol Parameter Conditions Min Typ Max Unit tBVBH VSTBY Detection to VSTBYON Output High (Note 1) 20 µs tBXBL VSTBY Off Detection to VSTBYON Output Low (Note 1) 20 µs Symbol Parameter Conditions Min Max Unit tISCCF Clock (TCK, PC1) Frequency (except for PLD) (Note 1) 20 MHz tISCCH Clock (TCK, PC1) High Time (except for PLD) (Note 1) 23 ns tISCCL Clock (TCK, PC1) Low Time (except for PLD) (Note 1) 23 ns tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2) 5 MHz tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2) 90 ns tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2) 90 ns tISCPSU ISC Port Set Up Time 7 ns tISCPH ISC Port Hold Up Time 5 ns tISCPCO ISC Port Clock to Output 21 ns tISCPZV ISC Port High-Impedance to Valid Output 21 ns tISCPVZ ISC Port Valid Output to High-Impedance 21 ns ISCCH TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO t tISCCL tISCPSU tISCPH tISCPVZ t ISCPZV tISCPCO AI02865223/231 uPSD33xx Table 153. ISC Timing (3V PSD Module) Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode. 2. For Program or Erase PLD only. Figure 98. MCU Module AC Measurement I/O Waveform Note: AC inputs during testing are driven at VCC–0.5V for a logic '1,' and 0.45V for a logic '0.' Timing measurements are made at VIH(min) for a logic '1,' and VIL(max) for a logic '0' Figure 99. PSD Module AC Float I/O Waveform Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH or VOL level occurs IOL and IOH ≥ 20mA Symbol Parameter Conditions Min Max Unit tISCCF Clock (TCK, PC1) Frequency (except for PLD) (Note 1) 12 MHz tISCCH Clock (TCK, PC1) High Time (except for PLD) (Note 1) 40 ns tISCCL Clock (TCK, PC1) Low Time (except for PLD) (Note 1) 40 ns tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2) 5 MHz tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2) 90 ns tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2) 90 ns tISCPSU ISC Port Set Up Time 12 ns tISCPH ISC Port Hold Up Time 5 ns tISCPCO ISC Port Clock to Output 30 ns tISCPZV ISC Port High-Impedance to Valid Output 30 ns tISCPVZ ISC Port Valid Output to High-Impedance 30 ns AI06650 VCC – 0.5V 0.45V Test Points 0.2 VCC – 0.1V 0.2 VCC + 0.9V AI06651 Test Reference Points VOL + 0.1V VOH – 0.1V VLOAD – 0.1V VLOAD + 0.1V 0.2 VCC – 0.1VuPSD33xx 224/231 Figure 100. External Clock Cycle Figure 101. PSD Module AC Measurement I/O Waveform Figure 102. PSD Module AC Measurement Load Circuit Table 154. I/O Pin Capacitance Note: 1. Sampled only, not 100% tested. 2. Typical values are for TA = 25°C and nominal supply voltages. 3. Maximum for MCU Address and Data lines is 20pF each. 3.0V 0V Test Point 1.5V AI03103b Device Under Test 2.01 V 195 Ω CL = 30 pF (Including Scope and Jig Capacitance) AI03104b Symbol Parameter(1) Test Condition Typ.2 Max. Unit CIN Input Capacitance (for input pins) VIN = 0V 4 6 pF COUT Output Capacitance (for input/ output pins)(3) VOUT = 0V 8 12 pF225/231 uPSD33xx PACKAGE MECHANICAL INFORMATION Figure 103. TQFP52 – 52-lead Plastic Thin, Quad, Flat Package Outline Note: Drawing is not to scale. QFP-A Nd E1 CP b e A2 A N A1 α L D1 D 1 Ne E c D2 E2 L1uPSD33xx 226/231 Table 155. TQFP52 – 52-lead Plastic Thin, Quad, Flat Package Mechanical Data Symb mm inches Typ Min Max Typ Min Max A 1.50 – 1.70 0.059 – 0.067 A1 0.10 0.05 0.20 0.004 0.002 0.008 A2 1.40 1.30 1.50 0.055 0.039 0.059 b – 0.20 0.40 – 0.008 0.016 c – 0.07 0.20 – 0.003 0.008 D 12.00 11.80 12.20 0.472 0.465 0.480 D1 10.00 9.80 10.20 0.394 0.386 0.402 D2 7.80 7.67 7.93 0.307 0.302 0.312 E 12.00 11.80 12.20 0.472 0.465 0.480 E1 10.00 9.80 10.20 0.394 0.386 0.402 E2 7.80 7.67 7.93 0.307 0.302 0.312 e 0.65 – – 0.026 – – L – 0.45 0.75 – 0.018 0.030 L1 1.00 – – 0.039 – – α – 0° 7° – 0° 7° n 52 52 Nd 13 13 Ne 13 13 CP – – 0.10 – – 0.004227/231 uPSD33xx Figure 104. TQFP80 – 80-lead Plastic Thin, Quad, Flat Package Outline Note: Drawing is not to scale. QFP-A Nd E1 CP b e A2 A N A1 α L D1 D 1 Ne E c D2 E2 L1uPSD33xx 228/231 Table 156. TQFP80 – 80-lead Plastic Thin, Quad, Flat Package Mechanical Data Symb mm inches Typ Min Max Typ Min Max A 1.60 0.063 A1 0.05 0.15 0.002 0.006 A2 1.40 1.35 1.45 0.055 0.053 0.057 b 0.17 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 D 14.00 0.551 D1 12.00 0.472 D2 9.50 0.374 E 14.00 0.551 E1 12.00 0.472 E2 9.50 0.374 e 0.50 0.020 L 0.45 0.75 0.018 0.030 L1 1.00 0.039 α 0° 7° 0° 7° n 80 80 Nd 20 20 Ne 20 20 CP 0.08 0.003229/231 uPSD33xx PART NUMBERING Table 157. Ordering Information Scheme For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Example: uPSD 33 3 4 D V – 40 U 6 T Device Type uPSD = Microcontroller PSD Family 33 = Turbo core SRAM Size 1 = 2Kbyte 3 = 8Kbyte 5 = 32Kbyte Main Flash Memory Size 2 = 64Kbyte 3 = 128Kbyte 4 = 256Kbyte IP Mix D = IP Mix: I2C, SPI, UART (2), IrDA, ADC, Supervisor, PCA Operating Voltage blank = VCC = 4.5 to 5.5V V = VCC = 3.0 to 3.6V Speed –40 = 40MHz Package T = 52-pin TQFP U = 80-pin TQFP Temperature Range 6 = –40 to 85°C Shipping Option Tape & Reel Packing = TuPSD33xx 230/231 REVISION HISTORY Table 158. Document Revision History Date Version Revision Details July 1, 2003 1.0 First Issue 15-Jul-03 1.1 Update register information, electrical characteristics (Table 17, 46, 132, 133, 134, 135; Figure 68) 03-Sep-03 1.2 Update references for Product Catalog 05-Feb-04 2.0 Reformatted; corrected mechanical dimensions (Table 158) 07-May-04 3.0 Reformatted; update characteristics (Figure 3, 4, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84; Table 42, 64, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 121, 129, 130, 131, 136) 14-Sep-04 4.0 Reformatted; updated Feature Summary; added table (Table 128); updated graphics, mechanical dimensions (Figure 3, 4, 37, 40, 51, 76, 80; Table 2, 3, 6, 7, 8, 9, 10, 11, 37, 38, 40, 51, 77, 84, 119, 120, 121, 129, 155, 156) 29-Oct-04 5.0 Corrected TQFP80 mechanical dimensions (Table 156) 21-Jan-05 6.0 Updated characteristics, SPI section (Figure 3, 41, 42, 45; Table 59, 60, 61, 62, 128, 138, 140, 142, 144, 145, 152, 153)231/231 uPSD33xx Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No lii96ns0.71(i96 i)-12.1-s granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 1/29 Revision History : Revision 1.0 (Nov. 02, 2006) -Original Revision 1.1 (Mar. 02, 2007) - Delete BGA ball name of packing dimensions Revision 1.2 (May. 03, 2007) - Modify DC Characteristics Revision 1.3 (May. 14, 2007) - Modify tSS (1.5ns => 2.5ns) and tSH(1ns => 1.5ns) Revision 1.4 (Jul. 10, 2007) - Modify type error ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 2/29 SDRAM 512K x 32Bit x 2Banks Synchronous DRAM FEATURES z 1.8V power supply z LVCMOS compatible with multiplexed address z Dual banks operation z MRS cycle with address key programs - CAS Latency (1, 2 & 3 ) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) z EMRS cycle with address key programs. z All inputs are sampled at the positive going edge of the system clock z Burst Read Single-bit Write operation z Special Function Support. - PASR (Partial Array Self Refresh ) - TCSR (Temperature compensated Self Refresh) - DS (Driver Strength) z DQM for masking z Auto & self refresh z 64ms refresh period (4K cycle) GENERAL DESCRIPTION The M52D32321A is 33,554,432 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 32 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. MAX Freq. Package Comments M52D32321A -10BG 100MHz 90 Ball VFBGA Pb-free M52D32321A -7.5BG 133MHz 90 Ball VFBGA Pb-free PIN CONFIGURATION (TOP VIEW) 90 Ball FBGA 1 2 3 4 5 6 7 8 9 A DQ26 DQ24 VSS VDD DQ23 DQ21 B DQ28 VDDQ VSSQ VDDQ VSSQ DQ19 C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ E VDDQ DQ31 NC NC DQ16 VSSQ F VSS DQM3 A3 A2 DQM2 VDD G A4 A5 A6 A10 A0 A1 H A7 A8 NC NC NC NC J CLK CKE A9 BA CS RAS K DQM1 NC NC CAS WE DQM0 L VDDQ DQ8 VSS VDD DQ7 VSSQ M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 R DQ13 DQ15 VSS VDD DQ0 DQ2ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 3/29 FUNCTIONAL BLOCK DIAGRAM Bank Select Data Input Register Column Decoder Latency & Burst Length Programming Register 512K x 32 512K x 32 Timing Register CLK CKE CS RAS CAS WE L(U)DQM LDQM LWCBR DQi LDQM LWE LRAS LCBR LWE LCAS CLK ADD LCKE PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System Clock Active on the positive going edge to sample all inputs. CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A10 Address Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, column address : CA0 ~ CA7 BA Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write Enable Enables write operation and row precharge. Latches data in starting from CAS , WE active. L(U)DQM Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 4/29 DQ0 ~ 31 Data Input / Output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No Connection/ Reserved for Future Use This pin is recommended to be left No Connection on the device. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN,VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to VSS VDD,VDDQ -1.0 ~ 4.6 V Storage temperature TSTG -55 ~ + 150 °C Power dissipation PD 0.7 W Short circuit current IOS 50 MA Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA= 0 °C ~ 70 °C ) Parameter Symbol Min Typ Max Unit Note Supply voltage VDD,VDDQ 1.7 1.8 1.9 V Input logic high voltage VIH 0.8 x VDDQ 1.8 VDDQ+0.3 V 1 Input logic low voltage VIL -0.3 0 0.3 V 2 Output logic high voltage VOH VDDQ – 0.2 - - V IOH =-0.1mA Output logic low voltage VOL - - 0.2 V IOL = 0.1mA Input leakage current IIL -10 - 10 uA 3 Output leakage current IOL -10 - 10 uA 4 Note : 1.VIH (max) = 2.2V AC for pulse width ≤ 3ns acceptable. 2.VIL (min) = -1.0V AC for pulse width ≤ 3ns acceptable. 3.Any input 0V ≤ VIN ≤ VDDQ, all other pins are not under test = 0V. 4.Dout is disabled, 0V ≤ VOUT ≤ VDDQ. CAPACITANCE (VDD = 1.8V, TA = 25 °C , f = 1MHz) Pin Symbol Min Max Unit CLOCK CCLK 2.0 4.0 pF RAS , CAS , WE , CS , CKE, LDQM, UDQM CIN 2.0 4.0 pF ADDRESS CADD 2.0 4.0 pF DQ0 ~DQ15 COUT 3.5 6.0 pF ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 5/29 DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 °C ~ 70 °C ) Version Parameter Symbol Test Condition CAS Latency -7.5 -10 Unit Note Operating Current (One Bank Active) ICC1 Burst Length = 1 tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA 55 35 mA 1 Precharge Standby ICC2P CKE ≤ VIL(max), tCC =15ns 0.3 mA Current in power-down mode ICC2PS CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞ 0.2 mA ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC =15ns Input signals are changed one time during 30ns 3 mA Precharge Standby Current in non power-down mode ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 1 mA ICC3P CKE ≤ VIL(max), tCC =15ns 1.5 Active Standby Current in power-down mode ICC3PS CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞ 1 mA ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns Input signals are changed one time during 30ns Active Standby Current 10 mA in non power-down mode (One Bank Active) ICC3NS CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞ Input signals are stable 2.5 mA Operating Current (Burst Mode) ICC4 IOL= 0Ma, Page Burst All Band Activated, tCCD = tCCD (min) 70 60 mA 1 Refresh Current ICC5 tRC ≥ tRC(min) 40 40 mA 2 TCSR range 45 70 °C Self Refresh Current ICC6 CKE ≤ 0.2V 2 Banks 180 200 1 Bank 160 180 uA Deep Power Down Current ICC7 CKE ≤ 0.2V 10 uA Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min). 2.Refresh period is 64ms. Addresses are changed only one time during tCC(min). ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 6/29 AC OPERATING TEST CONDITIONS (VDD=1.8V ± 0.1V,TA= 0 C° ~ 70 C° ) Parameter Value Unit Input levels (Vih/Vil) 0.9 x VDDQ / 0.2 V Input timing measurement reference level 0.5 x VDDQ V Input rise and fall time tr / tf = 1 / 1 ns Output timing measurement reference level 0.5 x VDDQ V Output load condition See Fig.2 OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Version Parameter Symbol -7.5 -10 Unit Note Row active to row active delay tRRD(min) 15 20 ns 1 RAS to CAS delay tRCD(min) 22.5 30 ns 1 Row precharge time tRP(min) 22.5 30 ns 1 tRAS(min) 45 50 ns 1 Row active time tRAS(max) 100 us Row cycle time tRC(min) 67.5 90 ns 1 Last data in to new col. Address delay tCDL(min) 1 CLK 2 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. Address to col. Address delay tCCD(min) 1 CLK 3 CAS latency=3 2 Number of valid output data CAS latency=2 1 ea 4 Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks. Z0=50 1.8V Output (Fig.2) AC Output Load Circuit 20 pF Vtt =0.5x VDDQ VOH(DC) = VDDQ-0.2V, IOH = -0.1mA VOL(DC) = 0.2V, IOL = 0.1mA 20 pF Output (Fig.1) DC Output Load circuit 10.6K 13.9K 50ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 7/29 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -7.5 -10 Parameter Symbol Min Max Min Max Unit Note CAS Latency =3 7.5 9 CLK cycle time CAS Latency =2 tCC 12 1000 15 1000 ns 1 CLK to valid CAS Latency =3 - 7 - 8 output delay CAS Latency =2 tSAC - 10 - 10 ns 1 Output data hold time tOH 2.0 - 2.0 - ns 2 CLK high pulse width tCH 2.5 - 2.5 - ns 3 CLK low pulse width tCL 2.5 - 2.5 - ns 3 Input setup time tSS 2.5 - 2.5 - ns 3 Input hold time tSH 1.5 - 1.5 - ns 3 CLK to output in Low-Z tSLZ 1 - 1 - ns 2 CAS Latency =3 - 6 - 7 CLK to output in Hi-Z CAS Latency =2 tSHZ - 9 - 10 ns - *All AC parameters are measured from half to half. Note: 1.Parameters depend on programmed CAS latency. 2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter. 3.Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the parameter. ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 8/29 MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address BA A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function 0 RFU W.B.L TM CAS Latency BT Burst Length Test Mode CAS Latency Burst Type Burst Length A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 1 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 0 1 0 4 4 1 1 Reserved 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Full Page Reserved Full Page Length : 256 ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 9/29 Extended Mode Register BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 1 0 ATCSR 0 0 DS TCSR PASR Extended Mode Register A2-0 Self Refresh Coverage 000 Full Array 001 1/2 of Full Array 010 1/4 of Full Array 011 RFU 100 RFU 101 RFU 110 RFU PASR 111 RFU A6-A5 Driver Strength 00 Full Strength 01 1/2 Strength 10 1/4 Strength DS 11 RFU A9 ATCSR ATCSR 0 Enable 1 R TRUTH TABLE (Deep Power Down Mode) COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A9~A0 Entry H L L H H L X Deep Power Down Mode Exit L H X X X X X X (V= Valid, X= Don’t Care, H= Logic High , L = Logic Low) A4-A3 Maximum Case Temperature 11 85oC 00 70oC 01 45oC TCSR 10 15oC ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 10/29 Burst Length and Sequence (Burst of Two) Starting Address (column address A0 binary) Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (decimal) 0 0,1 0,1 1 1,0 1,0 (Burst of Four) Starting Address (column address A1-A0, binary) Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (decimal) 00 0,1,2,3 0,1,2,3 01 1,2,3,0 1,0,3,2 10 2,3,0,1 2,3,0,1 11 3,0,1,2 3,2,1,0 (Burst of Eight) Starting Address (column address A2-A0, binary) Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (decimal) 000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6 010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5 011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4 100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2 110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1 111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0 Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx32 divice. POWER UP SEQUENCE 1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs. 2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3.Issue precharge commands for all banks of the devices. 4.Issue 2 or more auto-refresh commands. 5.Issue mode register set command to initialize the mode register. Cf.)Sequence of 4 & 5 is regardless of the order.ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 11/29 SIMPLIFIED TRUTH TABLE COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A9~A0 Note Mode Register Set H X L L L L X OP CODE 1,2 Register Extended Mode Register Set H X L L L L X OP CODE 1,2 Auto Refresh H 3 Entry H L L L L H X X 3 L H H H 3 Refresh Self Refresh Exit L H H X X X X X 3 Bank Active & Row Addr. H X L L H H X V Row Address Auto Precharge Disable L 4 Read & Column Address Auto Precharge Enable H X L H L H X V H Column Address (A0~A7) 4,5 Write & Column Auto Precharge Disable L 4 Address Auto Precharge Enable H X L H L L X V H Column Address (A0~A7) 4,5 Burst Stop H X L H H L X X 6 Bank Selection V L 4 Precharge Both Banks H X L L H L X X H X 4 H X X X Entry H L L V V V Clock Suspend or X Active Power Down Exit L H X X X X X X H X X X Entry H L L H H H X H X X X Precharge Power Down Mode Exit L H L V V V X X DQM H X V X 7 H H X X X No Operation Command H X L H H H X X Deep Power Down Mode Entry H L L H H L X Exit L H X X X X X X (V= Valid, X= Don’t Care, H= Logic High , L = Logic Low) Note: 1. OP Code: Operation Code A0~A10/AP, BA: Program keys.(@MRS). BA=0 for MRS and BA=1 for EMRS. 2. MRS/EMRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by “Auto”. Auto / self refresh can be issued only at both banks precharge state. 4. BA: Bank select address. If “Low”: at read, write, row active and precharge, bank A is selected. If “High”: at read, write, row active and precharge, bank B is selected. If A10/AP is “High” at row precharge, BA ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read /write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 12/29 Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1 : D o n ' t C a r e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE C S RAS CAS ADDR W E D Q DQM A10/AP t C H t C L t C C Row Active BA *Note1 HIGH t RCD t S S t S S t S H t S H t S S t S H t S S t S S t S H t S S t S S t S H R a C a C b C c R b BS BS BS BS BS BS R a Qa D b Q c R b Read Write Read Precharge Row Active t R C t RAS t R P t CCD t RAC *Note2 *Note2,3 *Note2,3 *Note4 *Note2 *Note 3 *Note 3 *Note2,3 t S H t SLZ t SAC t O H t S H t S S t S H *Note 3 *Note4ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 13/29 *Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA. BA Active & Read/Write 0 Bank A 1 Bank B 3.Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/AP BA Operation 0 0 Disable auto precharge, leave bank A active at end of burst. 1 Disable auto precharge, leave bank B active at end of burst. 1 0 Enable auto precharge, precharge bank A at end of burst. 1 Enable auto precharge, precharge bank B at end of burst. 4.A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA precharge 0 0 Bank A 0 1 Bank B 1 X Both Banks ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 14/29 Power Up Sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE ADDR D Q DQM A10/AP t R P Key RAa RAa Precharge All Banks Auto Refresh Auto Refresh Mode Register Set (A-Bank) Row Active : Don't care t R C t R C High level is necessary High level is necessary BA High-Z CS RAS CAS WE Key KeyESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 15/29 Read & Write Cycle at Same Bank @Burst Length = 4 *Note: 1.Minimum row cycle times is required to complete internal DRAM operation. 2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC 4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst) Burst can’t end in Full Page Mode. tRCD tRC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE CS RAS CAS ADDR DQM BA CL=2 CL=3 Ra Rb Cb0 tOH tSAC tSHZ tSHZ tRDL Row Active Read Precharge (A-Bank) (A-Bank) (A-Bank) Precharge (A-Bank) Write (A-Bank) Row Active (A-Bank) *Note3 *Note3 *Note4 *Note4 : Don't care *Note1 Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 tRAC tRAC tRDL Ca0 A10/AP Ra Rb HIGH *Note2 WE tO H QC tSACESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 16/29 Page Read & Write Cycle at Same Bank @ Burst Length=4 *Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. CLOCK CKE CS RAS CAS BA ADDR A10/AP CL=2 CL=3 WE DQM HIGH tRCD *Note2 Ra Ca0 Cb0 Cc0 Cd0 Ra Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1 Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd2 tCDL *Note1 Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRDL *Note3ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 17/29 Page Read Cycle at Different Bank @ Burst Length=4 *Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege. 2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. CLOCK CKE CS RAS CAS BA ADDR A10/AP CL=2 CL=3 WE DQM HIGH *Note2 RAa CAa RBb RAa Read (A-Bank) Row Active Row Active (B-Bank) (A-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Read (B-Bank) Precharge (A-Bank) : Don't care DQ CBb CAc CBd CAe QAa0 *Note1 RBb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 18/29 Page Write Cycle at Different Bank @Burst Length = 4 *Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same. CLOCK CKE CS RAS CAS BA ADDR A10/AP WE DQM HIGH Row Active (A-Bank) Row Active (B-Bank) Write (A-Bank) Precharge (Both Banks) : Don't care DQ Write (A-Bank) Write (B-Bank) Write (B-Bank) DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 RAa RBb RAa CAa RBb CBb CAc CBd *Note2 tCDL tRDL *Note1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 19/29 Read & Write Cycle at Different Bank @ Burst Length = 4 *Note: 1.tCDL should be met to complete write.ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 20/29 Read & Write Cycle with auto Precharge @ Burst Length =4 *Note: 1.tCDL Should be controlled to meet minimum tRAS before internal precharge start (In the case of Burst Length=1 & 2 and BRSW mode) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE CAS ADDR W E D Q DQM A10/AP BA CL=2 CL=3 Row Active ( A - Bank ) Row Active ( B - Bank ) Read with Auto Precharge ( A - Bank ) Auto Precharge Start Point (B-Bank) : D o n ' t C a r e Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 R a Ra Ca R b C b R b Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 Write with Auto Precharge (B-Bank) HIGH Auto Precharge Start Point ( A - Bank) C S RASESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 21/29 Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4 *Note:1.DQM is needed to prevent bus contention. CLOCK CKE ADDR D Q DQM A10/AP R a C a C b C c R a Qa0 Qa1 Qa2 Qa3 t SHZ Qb0 Qb1 t SHZ Dc0 Dc2 *Note1 Row Active Read Clock Suspension Read Read DQM Write Write DQM Clock Suspension Write DQM :Don't Care BA C S RAS CAS W E 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 22/29 Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page *Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue. 2.About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycle”. 3.Burst stop is valid at every burst length. CLOCK CKE ADDR D Q DQM A10/AP BA RAa CAa CAb RAa QAa0 QAa1 QAb0 QAb1 QAb2 *Note1 Row Active (A-Bank) Read (A-Bank) Burst Stop Read (A-Bank) :Don't Care HIGH CL=2 CL=3 QAa2 QAa3 QAa4 QAb3 QAb4 QAb5 QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 1 1 2 2 Precharge (A-Bank) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CS RAS CAS WE *Note2ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 23/29 Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page *Note: 1. Burst can’t end in full page mode, so auto precharge can’t issue. 2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. Input data after Row precharge cycle will be masked internally. 3.Burst stop is valid at every burst length. CLOCK CKE ADDR D Q DQM A10/AP RAa CAa CAb RAa DAa0 DAa1 DAb0 DAb1 DAb2 Row Active (A-Bank) Write (A-Bank) Burst Stop Write (A-Bank) :Don't Care HIGH DAa2 DAa3 DAa4 DAb3 DAb4 DAb5 Precharge (A-Bank) t BDL t RDL *Note2 C S RAS CAS W E BA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 24/29 Burst Read Single bit Write Cycle @Burst Length=2 *Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set). At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length. 2.When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge command will be issued after two clock cycles. CLOCK CKE ADDR CL=2 DQM A10/AP BA RAa RAc RAa QAb0 Row Active (A-Bank) Write (A-Bank) :Don't Care HIGH QAb1 Precharge (A-Bank) CAa RBb CAb CBc CAd RAc DBc0 D Q CL=3 DAa0 QAb0 QAb1 DBc0 Row Active (B-Bank) Row Active (A-Bank) Write with Auto Precharge (B-Bank) Read (A-Bank) DAa0 QAd0 QAd1 QAd0 QAd1 *Note1 C S RAS CAS W E RBb *Note2 Read with Auto Precharge (A-Bank) ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 25/29 Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4 *Note :1.Both banks should be in idle state prior to entering precharge power down mode. 2.CKE should be set high at least 1CLK+tss prior to Row active command. 3.Can not violate minimum refresh specification. (64ms) CLOCK CKE ADDR D Q DQM A10/AP Active Power-down Exit Precharge : Don't care *Note3 *Note2 *Note1 t S S R a R a Qa0 Qa1 Qa2 t SHZ Precharge Power-Down Entry Precharge Power-Down Exit Row Active Active Power-down Entry Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 C a B A RAS CAS C S W E tS S tS SESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 26/29 Self Refresh Entry & Exit Cycle *Note: TO ENTER SELF REFRESH MODE 1. CS , RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE. 3. The device remains in self refresh mode as long as CKE stays “Low”. cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS Starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. CLOCK CKE ADDR D Q DQM A10/AP Self Refresh Entry Auto Refresh : Don't care Self Refresh Exit Hi-Z Hi-Z W E BA CAS RAS C S *Note2 *Note1 *Note4 t RCmin *Note6 *Note5 *Note7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t S S *Note3ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 27/29 Mode Register Set Cycle Auto Refresh Cycle *Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note: 1. CS ,RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table. CLOCK CKE ADDR Key :Don't Care HIGH C S RAS CAS HIGH *Note3 R a *Note1 D Q Hi-Z DQM 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 Hi-Z *Note2 t R C MRS New Command Auto Refresh New Command W E 0ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 28/29 PACKING DIMENSIONS 90-BALL SDRAM ( 8x13 mm ) Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max A 1.00 0.039 A1 0.30 0.35 0.40 0.012 0.014 0.016 A2 0.586 0.023 øb 0.40 0.45 0.50 0.016 0.018 0.020 D 7.90 8.00 8.10 0.311 0.315 0.319 E 12.90 13.00 13.10 0.508 0.512 0.516 D1 6.40 0.252 E1 11.20 0.441 e 0.80 0.031 Controlling dimension : Millimeter.ESMT M52D32321A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.4 29/29 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. CRUCIAL PART NUMBER MODULE TYPE DENSITY SPEED RANK VOLTAGE COMP CONFIG CAS LATENCY MICRON PART NUMBER CT4G4RFS8213 RDIMM 288-pin 4GB 2133MT/s Single 1.2V 512M x 8 CL15 MTA9ASF51272PZ-2G1A2 CT8G4RFS4213 RDIMM 288-pin 8GB 2133MT/s Single 1.2V 1024M x 4 CL15 MTA18ASF1G72PZ-2G1A2 CT16G4RFD4213 RDIMM 288-pin 16GB 2133MT/s Dual 1.2V 1024M x 4 CL15 MTA36ASF2G72PZ-2G1A2 CT4G4DFS8213 UDIMM 288-pin 4GB 2133MT/s Single 1.2V 512M x 8 CL15 MTA8ATF51264AZ-2G1A1 CT8G4DFD8213 UDIMM 288-pin 8GB 2133MT/s Dual 1.2V 512M x 8 CL15 MTA16ATF1G64AZ-2G1A1 1 Product performance and efficiency improvements are noted as comparisons between DDR3 and DDR4 memory technologies at their introduction. When it was introduced, DDR3-1066 operated at 1.5V and had an estimated component density of 8Gb, compared to DDR4-2133, which will operate at 1.2V and have an estimated component density of 16Gb. When voltage reductions and all other energy-saving DDR4 features are factored in, DDR4 modules are projected to consume up to 40% less power. 2Limited lifetime warranty valid everywhere except Germany and France, where warranty is valid for ten years from date of purchase. 3Program benefits may vary and are subject to change without notice. Customer admittance and continued inclusion to the program is up to the sole discretion of Micron Technology, Inc. REVISION: 04/18/2014 ©2014 Micron Technology, Inc. All rights reserved. Information is subject to change without notice. Crucial and the Crucial logo are trademarks or registered trademarks of Micron Technology, Inc. All other trademarks and service marks are property of their respective owners. Products and specifications are subject to change without notice. Neither Crucial nor Micron Technology is responsible for omissions or errors in typography or photography. NOW SAMPLING: Crucial® DDR4 Server Memory Get early access to Crucial DDR4 modules! Introducing the Crucial DDR4 Technology Enablement Program (TEP) HOW IT WORKS Enroll in the Crucial DDR4 TEP program and get early access to DDR4 modules and information. Start the enrollment process today by visiting www.crucial.com/usa/en/memory-ddr4-info. ELIGIBILITY Channel partners who are currently developing or evaluating DDR4-capable platforms BENEFITS3 • Early access to select Crucial DDR4 modules • Notification of new DDR4 modules as they become available • Access to technical resources to aid in product development and evaluation Now Sampling The following modules are now included as part of the Crucial DDR4 TEP program. Qualified participants are encouraged to inquire about pricing and availability. Additional module types, densities, and speeds will be available later this year. Stay tuned! DDR4 Server Memory: Product Highlights1 • Increase data throughput – up to 50% more memory bandwidth • Enable up to twice the installed server memory capacity • Reduce power consumption – up to 40% more energy efficient • Easier system cooling – less heat generated per module • Optimized for future Intel® Xeon® processor E5-2600 v3 product family • Compatible with OEM servers and warranties • Backed by the Reliance Program • Limited lifetime warranty2 Overcome one of the greatest server limitations: memory. From cloud computing and virtualization to HPC, Big Data and more, memory-dependent server applications require increasingly higher densities of memory and higher levels of performance than are attainable on current DDR3 technology. Enter Crucial DDR4 server memory. More speed. More bandwidth. More efficient. Next generation DDR4 memory is here. © 2007 Microchip Technology Inc. DS39605F PIC18F1220/1320 Data Sheet 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt TechnologyDS39605F-page ii © 2007 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.© 2007 Microchip Technology Inc. DS39605F-page 1 Low-Power Features: • Power Managed modes: - Run: CPU on, peripherals on - Idle: CPU off, peripherals on - Sleep: CPU off, peripherals off • Power Consumption modes: - PRI_RUN: 150 μA, 1 MHz, 2V - PRI_IDLE: 37 μA, 1 MHz, 2V - SEC_RUN: 14 μA, 32 kHz, 2V - SEC_IDLE: 5.8 μA, 32 kHz, 2V - RC_RUN: 110 μA, 1 MHz, 2V - RC_IDLE: 52 μA, 1 MHz, 2V - Sleep: 0.1 μA, 1 MHz, 2V • Timer1 Oscillator: 1.1 μA, 32 kHz, 2V • Watchdog Timer: 2.1 μA • Two-Speed Oscillator Start-up Oscillators: • Four Crystal modes: - LP, XT, HS: up to 25 MHz - HSPLL: 4-10 MHz (16-40 MHz internal) • Two External RC modes, up to 4 MHz • Two External Clock modes, up to 40 MHz • Internal oscillator block: - 8 user-selectable frequencies: 31 kHz, 125 kHz, 250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz - 125 kHz to 8 MHz calibrated to 1% - Two modes select one or two I/O pins - OSCTUNE – Allows user to shift frequency • Secondary oscillator using Timer1 @ 32 kHz • Fail-Safe Clock Monitor - Allows for safe shutdown if peripheral clock stops Peripheral Highlights: • High current sink/source 25 mA/25 mA • Three external interrupts • Enhanced Capture/Compare/PWM (ECCP) module: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-Shutdown and Auto-Restart - Capture is 16-bit, max resolution 6.25 ns (TCY/16) - Compare is 16-bit, max resolution 100 ns (TCY) • Compatible 10-bit, up to 13-channel Analog-toDigital Converter module (A/D) with programmable acquisition time • Enhanced USART module: - Supports RS-485, RS-232 and LIN 1.2 - Auto-Wake-up on Start bit - Auto-Baud Detect Special Microcontroller Features: • 100,000 erase/write cycle Enhanced Flash program memory typical • 1,000,000 erase/write cycle Data EEPROM memory typical • Flash/Data EEPROM Retention: > 40 years • Self-programmable under software control • Priority levels for interrupts • 8 x 8 Single-Cycle Hardware Multiplier • Extended Watchdog Timer (WDT): - Programmable period from 41 ms to 131s - 2% stability over VDD and Temperature • Single-supply 5V In-Circuit Serial Programming™ (ICSP™) via two pins • In-Circuit Debug (ICD) via two pins • Wide operating voltage range: 2.0V to 5.5V Device Program Memory Data Memory I/O 10-bit A/D (ch) ECCP (PWM) EUSART Timers Flash 8/16-bit (bytes) # Single-Word Instructions SRAM (bytes) EEPROM (bytes) PIC18F1220 4K 2048 256 256 16 7 1 Y 1/3 PIC18F1320 8K 4096 256 256 16 7 1 Y 1/3 18/20/28-Pin High-Performance, Enhanced Flash MCUs with 10-bit A/D and nanoWatt Technology PIC18F1220/1320PIC18F1220/1320 DS39605F-page 2 © 2007 Microchip Technology Inc. Pin Diagrams RB3/CCP1/P1A RB2/P1B/INT2 OSC1/CLKI/RA7 OSC2/CLKO/RA6 VDD/AVDD RB7/PGD/T1OSI/ RB6/PGC/T1OSO/ RB5/PGM/KBI1 RB4/AN6/RX/ RA0/AN0 RA1/AN1/LVDIN RA4/T0CKI MCLR/VPP/RA5 VSS/AVSS RA2/AN2/VREFRA3/AN3/VREF+ RB0/AN4/INT0 RB1/AN5/TX/ 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 PIC18F1X20 18-Pin PDIP, SOIC RB3/CCP1/P1A RB2/P1B/INT2 OSC1/CLKI/RA7 OSC2/CLKO/RA6 VDD RB7/PGD/T1OSI/ RB6/PGC/T1OSO/ RB5/PGM/KBI1 RB4/AN6/RX/ RA0/AN0 RA1/AN1/LVDIN RA4/T0CKI MCLR/VPP/RA5 VSS RA2/AN2/VREFRA3/AN3/VREF+ RB0/AN4/INT0 RB1/AN5/TX/ 1 2 3 4 5 7 8 9 10 20 19 18 17 16 14 13 12 11 PIC18F1X20 AVSS 6 15 AVDD 20-Pin SSOP 28-Pin QFN 16 2 RA4/T0CKI RA0/AN0 NC MCLR/VPP/RA5 NC AVSS NC RA2/AN2/VREFRA3/AN3/VREF+ RA1/AN1/LVDIN OSC1/CLKI/RA7 OSC2/CLKO/RA6 VDD NC AVDD RB7/PGD/T1OSI/P1D/KBI3 RB6/PGC/T1OSO/T13CKI/P1C/KBI2 NC RB5/PGM/KBI1 7 PIC18F1X20 1 3 6 5 4 15 21 19 20 17 18 28 27 26 25 24 23 22 8 9 10 11 12 13 14 VSS NC NC RB2/P1B/INT2 RB0/AN4/INT0 RB1/AN5/TX/CK/INT1 NC RB4/AN6/RX/DT/KBI0 RB3/CCP1/P1A T13CKI/P1C/KBI2 P1D/KBI3 CK/INT1 DT/KBI0 P1D/KBI3 T13CKI/P1C/KBI2 CK/INT1 DT/KBI0© 2007 Microchip Technology Inc. DS39605F-page 3 PIC18F1220/1320 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Oscillator Configurations ............................................................................................................................................................ 11 3.0 Power Managed Modes ............................................................................................................................................................. 19 4.0 Reset.......................................................................................................................................................................................... 33 5.0 Memory Organization................................................................................................................................................................. 41 6.0 Flash Program Memory.............................................................................................................................................................. 57 7.0 Data EEPROM Memory ............................................................................................................................................................. 67 8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 71 9.0 Interrupts .................................................................................................................................................................................... 73 10.0 I/O Ports ..................................................................................................................................................................................... 87 11.0 Timer0 Module ........................................................................................................................................................................... 99 12.0 Timer1 Module ......................................................................................................................................................................... 103 13.0 Timer2 Module ......................................................................................................................................................................... 109 14.0 Timer3 Module ......................................................................................................................................................................... 111 15.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 115 16.0 Enhanced Addressable Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .......................................... 131 17.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 155 18.0 Low-Voltage Detect.................................................................................................................................................................. 165 19.0 Special Features of the CPU.................................................................................................................................................... 171 20.0 Instruction Set Summary.......................................................................................................................................................... 191 21.0 Development Support............................................................................................................................................................... 233 22.0 Electrical Characteristics.......................................................................................................................................................... 237 23.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 267 24.0 Packaging Information.............................................................................................................................................................. 285 Appendix A: Revision History............................................................................................................................................................. 291 Appendix B: Device Differences ........................................................................................................................................................ 291 Appendix C: Conversion Considerations ........................................................................................................................................... 292 Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 292 Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 293 Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 293 Index .................................................................................................................................................................................................. 295 The Microchip Web Site..................................................................................................................................................................... 303 Customer Change Notification Service .............................................................................................................................................. 303 Customer Support.............................................................................................................................................................................. 303 Reader Response .............................................................................................................................................................................. 304 PIC18F1220/1320 Product Identification System .............................................................................................................................. 305PIC18F1220/1320 DS39605F-page 4 © 2007 Microchip Technology Inc. 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DS39605F-page 5 PIC18F1220/1320 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high endurance Enhanced Flash program memory. On top of these features, the PIC18F1220/1320 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 New Core Features 1.1.1 nanoWatt TECHNOLOGY All of the devices in the PIC18F1220/1320 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. • Multiple Idle Modes: The controller can also run with its CPU core disabled, but the peripherals are still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. • On-the-fly Mode Switching: The power managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design. • Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.1 and 2.1 μA, respectively. 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F1220/1320 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators. • Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output), or one pin (oscillator input, with the second pin reassigned as general I/O). • Two External RC Oscillator modes, with the same pin options as the External Clock modes. • An internal oscillator block, which provides an 8 MHz clock (±2% accuracy) and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of 6 user-selectable clock frequencies (from 125 kHz to 4 MHz) for a total of 8 clock frequencies. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: • Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation, or a safe application shutdown. • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Poweron Reset, or wake-up from Sleep mode, until the primary clock source is available. This allows for code execution during what would otherwise be the clock start-up interval and can even allow an application to perform routine background activities and return to Sleep without returning to full power operation. 1.2 Other Special Features • Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. • Enhanced CCP module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown, for disabling PWM outputs on interrupt or other select conditions and auto-restart, to reactivate outputs once the condition has cleared. • Enhanced USART: This serial communication module features automatic wake-up on Start bit and automatic baud rate detection and supports RS-232, RS-485 and LIN 1.2 protocols, making it ideally suited for use in Local Interconnect Network (LIN) bus applications. • 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 2 minutes that is stable across operating voltage and temperature. • PIC18F1220 • PIC18F1320PIC18F1220/1320 DS39605F-page 6 © 2007 Microchip Technology Inc. 1.3 Details on Individual Family Members Devices in the PIC18F1220/1320 family are available in 18-pin, 20-pin and 28-pin packages. A block diagram for this device family is shown in Figure 1-1. The devices are differentiated from each other only in the amount of on-chip Flash program memory (4 Kbytes for the PIC18F1220 device, 8 Kbytes for the PIC18F1320 device). These and other features are summarized in Table 1-1. A block diagram of the PIC18F1220/1320 device architecture is provided in Figure 1-1. The pinouts for this device family are listed in Table 1-2. TABLE 1-1: DEVICE FEATURES Features PIC18F1220 PIC18F1320 Operating Frequency DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 4096 8192 Program Memory (Instructions) 2048 4096 Data Memory (Bytes) 256 256 Data EEPROM Memory (Bytes) 256 256 Interrupt Sources 15 15 I/O Ports Ports A, B Ports A, B Timers 4 4 Enhanced Capture/Compare/PWM Modules 1 1 Serial Communications Enhanced USART Enhanced USART 10-bit Analog-to-Digital Module 7 input channels 7 input channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Programmable Low-Voltage Detect Yes Yes Programmable Brown-out Reset Yes Yes Instruction Set 75 Instructions 75 Instructions Packages 18-pin SDIP 18-pin SOIC 20-pin SSOP 28-pin QFN 18-pin SDIP 18-pin SOIC 20-pin SSOP 28-pin QFN© 2007 Microchip Technology Inc. DS39605F-page 7 PIC18F1220/1320 FIGURE 1-1: PIC18F1220/1320 BLOCK DIAGRAM Instruction Decode & Control PORTA PORTB RA4/T0CKI MCLR/VPP/RA5(1) Enhanced Timer0 Timer1 Timer2 RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1/LVDIN RA0/AN0 Data Latch Data RAM Address Latch Address<12> 12(2) BSR FSR0 FSR1 FSR2 4 12 4 PCH PCL PCLATH 8 31 Level Stack Program Counter PRODH PRODL 8 x 8 Multiply WREG 8 BIT OP 8 8 ALU<8> 8 Address Latch (8 Kbytes) Data Latch 20 21 21 16 8 8 8 inc/dec logic 21 8 Data Bus<8> 8 Instruction 12 3 ROM Latch Timer3 Bank0, F PCLATU PCU OSC2/CLKO/RA6(2) USART 8 Register Table Latch Table Pointer <2> inc/dec logic RB0/AN4/INT0 RB4/AN6/RX/DT/KBI0 RB1/AN5/TX/CK/INT1 RB2/P1B/INT2 RB3/CCP1/P1A RB5/PGM/KBI1 RB6/PGC/T1OSO/ RB7/PGD/T1OSI/ OSC2/CLKI/RA7 Decode (2) Power-up Timer Power-on Reset Watchdog Timer VDD, VSS Brown-out Reset Precision Reference Voltage Low-Voltage Programming In-Circuit Debugger Oscillator Start-up Timer Timing Generation OSC1(2) OSC2(2) T1OSI T1OSO INTRC Oscillator Fail-Safe Clock Monitor Note 1: RA5 is available only when the MCLR Reset is disabled. 2: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. 8 CCP Enhanced T13CKI/P1C/KBI2 Program Memory (4 Kbytes) PIC18F1220 PIC18F1320 A/D Converter Data EEPROM P1D/KBI3 MCLR(1)PIC18F1220/1320 DS39605F-page 8 © 2007 Microchip Technology Inc. TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type Description PDIP/ SOIC SSOP QFN MCLR/VPP/RA5 MCLR VPP RA5 441 I P I ST — ST Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. OSC1/CLKI/RA7 OSC1 CLKI RA7 16 18 21 I I I/O ST CMOS ST Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. OSC2/CLKO/RA6 OSC2 CLKO RA6 15 17 20 O O I/O — — ST Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC, EC and INTRC modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes instruction cycle rate. General purpose I/O pin. PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 1 1 26 I/O I ST Analog Digital I/O. Analog input 0. RA1/AN1/LVDIN RA1 AN1 LVDIN 2 2 27 I/O I I ST Analog Analog Digital I/O. Analog input 1. Low-Voltage Detect input. RA2/AN2/VREFRA2 AN2 VREF- 677 I/O I I ST Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. RA3/AN3/VREF+ RA3 AN3 VREF+ 788 I/O I I ST Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. RA4/T0CKI RA4 T0CKI 3 3 28 I/O I ST/OD ST Digital I/O. Open-drain when configured as output. Timer0 external clock input. RA5 See the MCLR/VPP/RA5 pin. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-drain (no P diode to VDD) © 2007 Microchip Technology Inc. DS39605F-page 9 PIC18F1220/1320 PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN4/INT0 RB0 AN4 INT0 899 I/O I I TTL Analog ST Digital I/O. Analog input 4. External interrupt 0. RB1/AN5/TX/CK/INT1 RB1 AN5 TX CK INT1 9 10 10 I/O I O I/O I TTL Analog — ST ST Digital I/O. Analog input 5. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). External interrupt 1. RB2/P1B/INT2 RB2 P1B INT2 17 19 23 I/O O I TTL — ST Digital I/O. Enhanced CCP1/PWM output. External interrupt 2. RB3/CCP1/P1A RB3 CCP1 P1A 18 20 24 I/O I/O O TTL ST — Digital I/O. Capture 1 input/Compare 1 output/PWM 1 output. Enhanced CCP1/PWM output. RB4/AN6/RX/DT/KBI0 RB4 AN6 RX DT KBI0 10 11 12 I/O I I I/O I TTL Analog ST ST TTL Digital I/O. Analog input 6. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). Interrupt-on-change pin. RB5/PGM/KBI1 RB5 PGM KBI1 11 12 13 I/O I/O I TTL ST TTL Digital I/O. Low-Voltage ICSP Programming enable pin. Interrupt-on-change pin. RB6/PGC/T1OSO/ T13CKI/P1C/KBI2 RB6 PGC T1OSO T13CKI P1C KBI2 12 13 15 I/O I/O O I O I TTL ST — ST — TTL Digital I/O. In-Circuit Debugger and ICSP programming clock pin. Timer1 oscillator output. Timer1/Timer3 external clock output. Enhanced CCP1/PWM output. Interrupt-on-change pin. RB7/PGD/T1OSI/ P1D/KBI3 RB7 PGD T1OSI P1D KBI3 13 14 16 I/O I/O I O I TTL ST CMOS — TTL Digital I/O. In-Circuit Debugger and ICSP programming data pin. Timer1 oscillator input. Enhanced CCP1/PWM output. Interrupt-on-change pin. VSS 5 5, 6 3, 5 P — Ground reference for logic and I/O pins. VDD 14 15, 16 17, 19 P — Positive supply for logic and I/O pins. NC — — 18 — — No connect. TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP/ SOIC SSOP QFN Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-drain (no P diode to VDD) PIC18F1220/1320 DS39605F-page 10 © 2007 Microchip Technology Inc. NOTES:© 2007 Microchip Technology Inc. DS39605F-page 11 PIC18F1220/1320 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F1220 and PIC18F1320 devices can be operated in ten different oscillator modes. The user can program the configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: 1. LP Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL enabled 5. RC External Resistor/Capacitor with FOSC/4 output on RA6 6. RCIO External Resistor/Capacitor with I/O on RA6 7. INTIO1 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 8. INTIO2 Internal Oscillator with I/O on RA6 and RA7 9. EC External Clock with FOSC/4 output 10. ECIO External Clock with I/O on RA6 2.2 Crystal Oscillator/Ceramic Resonators In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION) TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. Typical Capacitor Values Used: Mode Freq OSC1 OSC2 XT 455 kHz 2.0 MHz 4.0 MHz 56 pF 47 pF 33 pF 56 pF 47 pF 33 pF HS 8.0 MHz 16.0 MHz 27 pF 22 pF 27 pF 22 pF Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table 2-2 for additional information. Resonators Used: 455 kHz 4.0 MHz 2.0 MHz 8.0 MHz 16.0 MHz Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the oscillator mode chosen. C1(1) C2(1) XTAL OSC2 OSC1 RF(3) Sleep To Logic PIC18FXXXX RS(2) InternalPIC18F1220/1320 DS39605F-page 12 © 2007 Microchip Technology Inc. TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2. FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) 2.3 HSPLL A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency crystal oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals. The HSPLL mode makes use of the HS mode oscillator for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLL is enabled only when the oscillator configuration bits are programmed for HSPLL mode. If programmed for any other mode, the PLL is not enabled. FIGURE 2-3: PLL BLOCK DIAGRAM Osc Type Crystal Freq Typical Capacitor Values Tested: C1 C2 LP 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF XT 1 MHz 33 pF 33 pF 4 MHz 27 pF 27 pF HS 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 32 kHz 4 MHz 200 kHz 8 MHz 1 MHz 20 MHz Note 1: Higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: RS may be required to avoid overdriving crystals with low drive level specification. 5: Always verify oscillator performance over the VDD and temperature range that is expected for the application. OSC1 Open OSC2 Clock from Ext. System PIC18FXXXX (HS Mode) MUX VCO Loop Filter Crystal Osc OSC2 OSC1 PLL Enable FIN FOUT SYSCLK Phase Comparator HS Oscillator Enable ÷4 (from Configuration Register 1H)© 2007 Microchip Technology Inc. DS39605F-page 13 PIC18F1220/1320 2.4 External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset, or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes, or to synchronize other logic. Figure 2-4 shows the pin connections for the EC Oscillator mode. FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows the pin connections for the ECIO Oscillator mode. FIGURE 2-5: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) 2.5 RC Oscillator For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation, due to tolerance of external R and C components used. Figure 2-6 shows how the R/C combination is connected. In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes, or to synchronize other logic. FIGURE 2-6: RC OSCILLATOR MODE The RCIO Oscillator mode (Figure 2-7) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). FIGURE 2-7: RCIO OSCILLATOR MODE OSC1/CLKI FOSC/4 OSC2/CLKO Clock from Ext. System PIC18FXXXX OSC1/CLKI RA6 I/O (OSC2) Clock from Ext. System PIC18FXXXX OSC2/CLKO CEXT REXT PIC18FXXXX OSC1 FOSC/4 Internal Clock VDD VSS Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ CEXT > 20 pF CEXT REXT PIC18FXXXX OSC1 Internal Clock VDD VSS Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ CEXT > 20 pF RA6 I/O (OSC2)PIC18F1220/1320 DS39605F-page 14 © 2007 Microchip Technology Inc. 2.6 Internal Oscillator Block The PIC18F1220/1320 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system’s clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the system clock. It also drives a postscaler, which can provide a range of clock frequencies from 125 kHz to 4 MHz. The INTOSC output is enabled when a system clock frequency from 125 kHz to 8 MHz is selected. The other clock source is the internal RC oscillator (INTRC), which provides a 31 kHz output. The INTRC oscillator is enabled by selecting the internal oscillator block as the system clock source, or when any of the following are enabled: • Power-up Timer • Fail-Safe Clock Monitor • Watchdog Timer • Two-Speed Start-up These features are discussed in greater detail in Section 19.0 “Special Features of the CPU”. The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (Register 2-2). 2.6.1 INTIO MODES Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available: • In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. 2.6.2 INTRC OUTPUT FREQUENCY The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz (see Table 22-6). This changes the frequency of the INTRC source from its nominal 31.25 kHz. Peripherals and features that depend on the INTRC source will be affected by this shift in frequency. Once set during factory calibration, the INTRC frequency will remain within ±2% as temperature and VDD change across their full specified operating ranges. 2.6.3 OSCTUNE REGISTER The internal oscillator’s output has been calibrated at the factory, but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register (Register 2-1). The tuning sensitivity is constant throughout the tuning range. When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new frequency. The INTRC clock will reach the new frequency within 8 clock cycles (approximately 8 * 32 μs = 256 μs). The INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. Operation of features that depend on the INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency.© 2007 Microchip Technology Inc. DS39605F-page 15 PIC18F1220/1320 REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER 2.7 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F1220/1320 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F1220/ 1320 devices offer two alternate clock sources. When enabled, these give additional options for switching to the various power managed operating modes. Essentially, there are three clock sources for these devices: • Primary oscillators • Secondary oscillators • Internal oscillator block The primary oscillators include the External Crystal and Resonator modes, the External RC modes, the External Clock modes and the internal oscillator block. The particular mode is defined on POR by the contents of Configuration Register 1H. The details of these modes are covered earlier in this chapter. The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power managed mode. PIC18F1220/1320 devices offer only the Timer1 oscillator as a secondary oscillator. This oscillator, in all power managed modes, is often the time base for functions such as a real-time clock. Most often, a 32.768 kHz watch crystal is connected between the RB6/T1OSO and RB7/T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground. These pins are also used during ICSP operations. The Timer1 oscillator is discussed in greater detail in Section 12.2 “Timer1 Oscillator”. In addition to being a primary clock source, the internal oscillator block is available as a power managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F1220/1320 devices are shown in Figure 2-8. See Section 12.0 “Timer1 Module” for further details of the Timer1 oscillator. See Section 19.1 “Configuration Bits” for configuration register details. U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency • • • • 000001 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111 • • • • 100000 = Minimum frequency Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 16 © 2007 Microchip Technology Inc. 2.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 2-2) controls several aspects of the system clock’s operation, both in full power operation and in power managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source that is used when the device is operating in power managed modes. The available clock sources are the primary clock (defined in Configuration Register 1H), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock selection has no effect until a SLEEP instruction is executed and the device enters a power managed mode of operation. The SCS bits are cleared on all forms of Reset. The Internal Oscillator Select bits, IRCF2:IRCF0, select the frequency output of the internal oscillator block that is used to drive the system clock. The choices are the INTRC source, the INTOSC source (8 MHz), or one of the six frequencies derived from the INTOSC postscaler (125 kHz to 4 MHz). If the internal oscillator block is supplying the system clock, changing the states of these bits will have an immediate change on the internal oscillator’s output. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the system clock. The OSTS indicates that the Oscillator Start-up Timer has timed out and the primary clock is providing the system clock in Primary Clock modes. The IOFS bit indicates when the internal oscillator block has stabilized and is providing the system clock in RC Clock modes or during Two-Speed Start-ups. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the system clock in Secondary Clock modes. In power managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the system clock, or the internal oscillator block has just started and is not yet stable. The IDLEN bit controls the selective shutdown of the controller’s CPU in power managed modes. The uses of these bits are discussed in more detail in Section 3.0 “Power Managed Modes”. FIGURE 2-8: PIC18F1220/1320 CLOCK DIAGRAM Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a SLEEP instruction will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts. PIC18F1220/1320 4 x PLL CONFIG1H <3:0> Secondary Oscillator T1OSCEN Enable Oscillator T1OSO T1OSI Clock Source Option for Other Modules OSC1 OSC2 Sleep Primary Oscillator HSPLL LP, XT, HS, RC, EC T1OSC CPU Peripherals IDLEN Postscaler MUX MUX 8 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 250 kHz OSCCON<6:4> 111 110 101 100 011 010 001 000 31 kHz INTRC Source Internal Oscillator Block WDT, FSCM 8 MHz Internal Oscillator (INTOSC) OSCCON<6:4> Clock Control OSCCON<1:0>© 2007 Microchip Technology Inc. DS39605F-page 17 PIC18F1220/1320 REGISTER 2-2: OSCCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 bit 7 IDLEN: Idle Enable bits 1 = Idle mode enabled; CPU core is not clocked in power managed modes 0 = Run mode enabled; CPU core is clocked in Run modes, but not Sleep mode bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8 MHz (8 MHz source drives clock directly) 110 = 4 MHz 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (INTRC source drives clock directly) bit 3 OSTS: Oscillator Start-up Time-out Status bit 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable bit 1-0 SCS1:SCS0: System Clock Select bits 1x = Internal oscillator block (RC modes) 01 = Timer1 oscillator (Secondary modes) 00 = Primary oscillator (Sleep and PRI_IDLE modes) Note 1: Depends on state of the IESO bit in Configuration Register 1H. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 18 © 2007 Microchip Technology Inc. 2.7.2 OSCILLATOR TRANSITIONS The PIC18F1220/1320 devices contain circuitry to prevent clocking “glitches” when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power Managed Modes”. 2.8 Effects of Power Managed Modes on the Various Clock Sources When the device executes a SLEEP instruction, the system is switched to one of the power managed modes, depending on the state of the IDLEN and SCS1:SCS0 bits of the OSCCON register. See Section 3.0 “Power Managed Modes” for details. When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In Secondary Clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the system clock. The Timer1 oscillator may also run in all power managed modes if required to clock Timer1 or Timer3. In Internal Oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the system clock source. The INTRC output can be used directly to provide the system clock and may be enabled to support various special features, regardless of the power managed mode (see Section 19.2 “Watchdog Timer (WDT)” through Section 19.4 “Fail-Safe Clock Monitor”). The INTOSC output at 8 MHz may be used directly to clock the system, or may be divided down first. The INTOSC output is disabled if the system clock is provided directly from the INTRC output. If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a realtime clock. Other features may be operating that do not require a system clock source (i.e., INTn pins, A/D conversions and others). 2.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Sections 4.1 through 4.5. The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 22-8) if enabled in Configuration Register 2L. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the HSPLL Oscillator mode is selected, the device is kept in Reset for an additional 2 ms following the HS mode OST delay, so the PLL can lock to the incoming clock frequency. There is a delay of 5 to 10 μs following POR while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIO modes are used as the primary clock source. TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE Oscillator Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output) RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6 ECIO Floating, pulled by external clock Configured as PORTA, bit 6 EC Floating, pulled by external clock At logic low (clock/4 output) LP, XT and HS Feedback inverter disabled at quiescent voltage level Feedback inverter disabled at quiescent voltage level Note: See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.© 2007 Microchip Technology Inc. DS39605F-page 19 PIC18F1220/1320 3.0 POWER MANAGED MODES The PIC18F1220/1320 devices offer a total of six operating modes for more efficient power management (see Table 3-1). These provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery powered devices). There are three categories of power managed modes: • Sleep mode • Idle modes • Run modes These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or INTOSC multiplexer); the Sleep mode does not use a clock source. The clock switching feature offered in other PIC18 devices (i.e., using the Timer1 oscillator in place of the primary oscillator) and the Sleep mode offered by all PIC® devices (where all system clocks are stopped) are both offered in the PIC18F1220/1320 devices (SEC_RUN and Sleep modes, respectively). However, additional power managed modes are available that allow the user greater flexibility in determining what portions of the device are operating. The power managed modes are event driven; that is, some specific event must occur for the device to enter or (more particularly) exit these operating modes. For PIC18F1220/1320 devices, the power managed modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when triggered by an interrupt, a Reset or a WDT time-out (PRI_RUN mode is the normal full power execution mode; the CPU and peripherals are clocked by the primary oscillator source). In addition, power managed Run modes may also exit to Sleep mode, or their corresponding Idle mode. 3.1 Selecting Power Managed Modes Selecting a power managed mode requires deciding if the CPU is to be clocked or not and selecting a clock source. The IDLEN bit controls CPU clocking, while the SCS1:SCS0 bits select a clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1. 3.1.1 CLOCK SOURCES The clock source is selected by setting the SCS bits of the OSCCON register (Register 2-2). Three clock sources are available for use in power managed Idle modes: the primary clock (as configured in Configuration Register 1H), the secondary clock (Timer1 oscillator) and the internal oscillator block. The secondary and internal oscillator block sources are available for the power managed modes (PRI_RUN mode is the normal full power execution mode; the CPU and peripherals are clocked by the primary oscillator source). TABLE 3-1: POWER MANAGED MODES Mode OSCCON Bits Module Clocking Available Clock and Oscillator Source IDLEN <7> SCS1:SCS0 <1:0> CPU Peripherals Sleep 0 00 Off Off None – All clocks are disabled PRI_RUN 0 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(1) This is the normal full power execution mode. SEC_RUN 0 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN 0 1x Clocked Clocked Internal Oscillator Block(1) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(1) Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.PIC18F1220/1320 DS39605F-page 20 © 2007 Microchip Technology Inc. 3.1.2 ENTERING POWER MANAGED MODES In general, entry, exit and switching between power managed clock sources requires clock source switching. In each case, the sequence of events is the same. Any change in the power managed mode begins with loading the OSCCON register and executing a SLEEP instruction. The SCS1:SCS0 bits select one of three power managed clock sources; the primary clock (as defined in Configuration Register 1H), the secondary clock (the Timer1 oscillator) and the internal oscillator block (used in RC modes). Modifying the SCS bits will have no effect until a SLEEP instruction is executed. Entry to the power managed mode is triggered by the execution of a SLEEP instruction. Figure 3-5 shows how the system is clocked while switching from the primary clock to the Timer1 oscillator. When the SLEEP instruction is executed, clocks to the device are stopped at the beginning of the next instruction cycle. Eight clock cycles from the new clock source are counted to synchronize with the new clock source. After eight clock pulses from the new clock source are counted, clocks from the new clock source resume clocking the system. The actual length of the pause is between eight and nine clock periods from the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. Three bits indicate the current clock source: OSTS and IOFS in the OSCCON register and T1RUN in the T1CON register. Only one of these bits will be set while in a power managed mode. When the OSTS bit is set, the primary clock is providing the system clock. When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source and is providing the system clock. When the T1RUN bit is set, the Timer1 oscillator is providing the system clock. If none of these bits are set, then either the INTRC clock source is clocking the system, or the INTOSC source is not yet stable. If the internal oscillator block is configured as the primary clock source in Configuration Register 1H, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable 8 MHz output. Entering an RC power managed mode (same frequency) would clear the OSTS bit. 3.1.3 MULTIPLE SLEEP COMMANDS The power managed mode that is invoked with the SLEEP instruction is determined by the settings of the IDLEN and SCS bits at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power managed mode specified by these same bits at that time. If the bits have changed, the device will enter the new power managed mode specified by the new bit settings. 3.1.4 COMPARISONS BETWEEN RUN AND IDLE MODES Clock source selection for the Run modes is identical to the corresponding Idle modes. When a SLEEP instruction is executed, the SCS bits in the OSCCON register are used to switch to a different clock source. As a result, if there is a change of clock source at the time a SLEEP instruction is executed, a clock switch will occur. In Idle modes, the CPU is not clocked and is not running. In Run modes, the CPU is clocked and executing code. This difference modifies the operation of the WDT when it times out. In Idle modes, a WDT time-out results in a wake from power managed modes. In Run modes, a WDT time-out results in a WDT Reset (see Table 3-2). During a wake-up from an Idle mode, the CPU starts executing code by entering the corresponding Run mode until the primary clock becomes ready. When the primary clock becomes ready, the clock source is automatically switched to the primary clock. The IDLEN and SCS bits are unchanged during and after the wake-up. Figure 3-2 shows how the system is clocked during the clock source switch. The example assumes the device was in SEC_IDLE or SEC_RUN mode when a wake is triggered (the primary clock was configured in HSPLL mode). Note 1: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. 2: Executing a SLEEP instruction does not necessarily place the device into Sleep mode; executing a SLEEP instruction is simply a trigger to place the controller into a power managed mode selected by the OSCCON register, one of which is Sleep mode.© 2007 Microchip Technology Inc. DS39605F-page 21 PIC18F1220/1320 3.2 Sleep Mode The power managed Sleep mode in the PIC18F1220/ 1320 devices is identical to that offered in all other PIC microcontrollers. It is entered by clearing the IDLEN and SCS1:SCS0 bits (this is the Reset state) and executing the SLEEP instruction. This shuts down the primary oscillator and the OSTS bit is cleared (see Figure 3-1). When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the system will not be clocked until the primary clock source becomes ready (see Figure 3-2), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 19.0 “Special Features of the CPU”). In either case, the OSTS bit is set when the primary clock is providing the system clocks. The IDLEN and SCS bits are not affected by the wake-up. 3.3 Idle Modes The IDLEN bit allows the microcontroller’s CPU to be selectively shut down while the peripherals continue to operate. Clearing IDLEN allows the CPU to be clocked. Setting IDLEN disables clocks to the CPU, effectively stopping program execution (see Register 2-2). The peripherals continue to be clocked regardless of the setting of the IDLEN bit. There is one exception to how the IDLEN bit functions. When all the low-power OSCCON bits are cleared (IDLEN:SCS1:SCS0 = 000), the device enters Sleep mode upon the execution of the SLEEP instruction. This is both the Reset state of the OSCCON register and the setting that selects Sleep mode. This maintains compatibility with other PIC devices that do not offer power managed modes. If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed approximately 10 μs while it becomes ready to execute code. When the CPU begins executing code, it is clocked by the same clock source as was selected in the power managed mode (i.e., when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals until the primary clock source becomes ready – this is essentially RC_RUN mode). This continues until the primary clock source becomes ready. When the primary clock becomes ready, the OSTS bit is set and the system clock source is switched to the primary clock (see Figure 3-4). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to full power operation. TABLE 3-2: COMPARISON BETWEEN POWER MANAGED MODES Power Managed Mode CPU is Clocked by ... WDT Time-out causes a ... Peripherals are Clocked by ... Clock during Wake-up (while primary becomes ready) Sleep Not clocked (not running) Wake-up Not clocked None or INTOSC multiplexer if Two-Speed Start-up or Fail-Safe Clock Monitor are enabled Any Idle mode Not clocked (not running) Wake-up Primary, Secondary or INTOSC multiplexer Unchanged from Idle mode (CPU operates as in corresponding Run mode) Any Run mode Primary or secondary clocks or INTOSC multiplexer Reset Primary or secondary clocks or INTOSC multiplexer Unchanged from Run modePIC18F1220/1320 DS39605F-page 22 © 2007 Microchip Technology Inc. FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE FIGURE 3-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q2 Q3 Q4 OSC1 Peripheral Sleep Program Q1 Q1 Counter Clock CPU Clock PC PC + 2 Q3 Q4 Q1 Q2 OSC1 Peripheral Program PC PLL Clock Q3 Q4 Output CPU Clock Q1 Q2 Q3 Q4 Q1 Q2 Clock Counter PC + 6 PC + 8 Q1 Q2 Q3 Q4 Wake Event Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. TOST(1) TPLL(1) OSTS bit Set PC + 2 PC + 4© 2007 Microchip Technology Inc. DS39605F-page 23 PIC18F1220/1320 3.3.1 PRI_IDLE MODE This mode is unique among the three Low-Power Idle modes, in that it does not disable the primary system clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. PRI_IDLE mode is entered by setting the IDLEN bit, clearing the SCS bits and executing a SLEEP instruction. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified in Configuration Register 1H. The OSTS bit remains set in PRI_IDLE mode (see Figure 3-3). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of approximately 10 μs is required between the wake event and code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-4). FIGURE 3-3: TRANSITION TIMING TO PRI_IDLE MODE FIGURE 3-4: TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE Q1 Peripheral Program PC PC + 2 OSC1 Q3 Q4 Q1 CPU Clock Clock Counter Q2 OSC1 Peripheral Program PC CPU Clock PC + 2 Q1 Q3 Q4 Clock Counter Q2 Wake Event CPU Start-up DelayPIC18F1220/1320 DS39605F-page 24 © 2007 Microchip Technology Inc. 3.3.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered by setting the Idle bit, modifying bits, SCS1:SCS0 = 01 and executing a SLEEP instruction. When the clock source is switched (see Figure 3-5) to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After a 10 μs delay following the wake event, the CPU begins executing code, being clocked by the Timer1 oscillator. The microcontroller operates in SEC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The Timer1 oscillator continues to run. FIGURE 3-5: TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE FIGURE 3-6: TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL) Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result. Q2 Q3 Q4 OSC1 Peripheral Program Q1 T1OSI Q1 Counter Clock CPU Clock PC PC + 2 12345678 Clock Transition Q1 Q3 Q4 OSC1 Peripheral Program PC PC + 2 T1OSI PLL Clock Q1 PC + 6 Q2 Output Q3 Q4 Q1 CPU Clock PC + 4 Clock Counter Q2 Q2 Q3 Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. Wake from Interrupt Event TPLL(1) 1 2 3 45678 Clock Transition OSTS bit Set TOST(1)© 2007 Microchip Technology Inc. DS39605F-page 25 PIC18F1220/1320 3.3.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. This mode is entered by setting the IDLEN bit, setting SCS1 (SCS0 is ignored) and executing a SLEEP instruction. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer (see Figure 3-7), the primary oscillator is shut down and the OSTS bit is cleared. If the IRCF bits are set to a non-zero value (thus, enabling the INTOSC output), the IOFS bit becomes set after the INTOSC output becomes stable, in about 1 ms. Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were previously at a non-zero value before the SLEEP instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a 10 μs delay following the wake event, the CPU begins executing code, being clocked by the INTOSC multiplexer. The microcontroller operates in RC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-8). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wakeup. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. FIGURE 3-7: TIMING TRANSITION TO RC_IDLE MODE FIGURE 3-8: TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN) Q2 Q3 Q4 OSC1 Peripheral Program Q1 INTRC Q1 Counter Clock CPU Clock PC PC + 2 12345678 Clock Transition Q1 Q3 Q4 OSC1 Peripheral Program PC PC + 2 INTOSC PLL Clock Q1 PC + 6 Q2 Output Q3 Q4 Q1 CPU Clock PC + 4 Clock Counter Q2 Q2 Q3 Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. Wake from Interrupt Event TOST(1) TPLL(1) 12345678 Clock Transition OSTS bit Set Multiplexer Q4PIC18F1220/1320 DS39605F-page 26 © 2007 Microchip Technology Inc. 3.4 Run Modes If the IDLEN bit is clear when a SLEEP instruction is executed, the CPU and peripherals are both clocked from the source selected using the SCS1:SCS0 bits. While these operating modes may not afford the power conservation of Idle or Sleep modes, they do allow the device to continue executing instructions by using a lower frequency clock source. RC_RUN mode also offers the possibility of executing code at a frequency greater than the primary clock. Wake-up from a power managed Run mode can be triggered by an interrupt, or any Reset, to return to full power operation. As the CPU is executing code in Run modes, several additional exits from Run modes are possible. They include exit to Sleep mode, exit to a corresponding Idle mode and exit by executing a RESET instruction. While the device is in any of the power managed Run modes, a WDT time-out will result in a WDT Reset. 3.4.1 PRI_RUN MODE The PRI_RUN mode is the normal full power execution mode. If the SLEEP instruction is never executed, the microcontroller operates in this mode (a SLEEP instruction is executed to enter all other power managed modes). All other power managed modes exit to PRI_RUN mode when an interrupt or WDT time-out occur. There is no entry to PRI_RUN mode. The OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 2.7.1 “Oscillator Control Register”). 3.4.2 SEC_RUN MODE The SEC_RUN mode is the compatible mode to the “clock switching” feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source. SEC_RUN mode is entered by clearing the IDLEN bit, setting SCS1:SCS0 = 01 and executing a SLEEP instruction. The system clock source is switched to the Timer1 oscillator (see Figure 3-9), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. When a wake event occurs, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The Timer1 oscillator continues to run. Firmware can force an exit from SEC_RUN mode. By clearing the T1OSCEN bit (T1CON<3>), an exit from SEC_RUN back to normal full power operation is triggered. The Timer1 oscillator will continue to run and provide the system clock, even though the T1OSCEN bit is cleared. The primary clock is started. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the Timer1 oscillator is disabled, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. FIGURE 3-9: TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, system clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result. Q2 Q3 Q4 OSC1 Peripheral Program Q1 T1OSI Q1 Counter Clock CPU Clock PC PC + 2 12345678 Clock Transition Q2 Q3 Q4 Q1 Q2 Q3 PC + 2© 2007 Microchip Technology Inc. DS39605F-page 27 PIC18F1220/1320 3.4.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer and the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing sensitive, or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator block (either of the INTIO1 or INTIO2 oscillators), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. This mode is entered by clearing the IDLEN bit, setting SCS1 (SCS0 is ignored) and executing a SLEEP instruction. The IRCF bits may select the clock frequency before the SLEEP instruction is executed. When the clock source is switched to the INTOSC multiplexer (see Figure 3-10), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to immediately change the system clock speed. Executing a SLEEP instruction is not required to select a new clock frequency from the INTOSC multiplexer. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the system clocks. If the IRCF bits are changed from all clear (thus, enabling the INTOSC output), the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the system continue while the INTOSC source stabilizes, in approximately 1 ms. If the IRCF bits were previously at a non-zero value before the SLEEP instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. When a wake event occurs, the system continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-8). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. FIGURE 3-10: TIMING TRANSITION TO RC_RUN MODE Note: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. Q1 Q2 Q3 OSC1 Peripheral Program Q4 INTRC Q4 Counter Clock CPU Clock PC PC + 2 12345678 Clock Transition Q1 Q2 Q3 Q4 Q1 Q2 Q3 PC + 4PIC18F1220/1320 DS39605F-page 28 © 2007 Microchip Technology Inc. 3.4.4 EXIT TO IDLE MODE An exit from a power managed Run mode to its corresponding Idle mode is executed by setting the IDLEN bit and executing a SLEEP instruction. The CPU is halted at the beginning of the instruction following the SLEEP instruction. There are no changes to any of the clock source status bits (OSTS, IOFS or T1RUN). While the CPU is halted, the peripherals continue to be clocked from the previously selected clock source. 3.4.5 EXIT TO SLEEP MODE An exit from a power managed Run mode to Sleep mode is executed by clearing the IDLEN and SCS1:SCS0 bits and executing a SLEEP instruction. The code is no different than the method used to invoke Sleep mode from the normal operating (full power) mode. The primary clock and internal oscillator block are disabled. The INTRC will continue to operate if the WDT is enabled. The Timer1 oscillator will continue to run, if enabled in the T1CON register (Register 12-1). All clock source status bits are cleared (OSTS, IOFS and T1RUN). 3.5 Wake from Power Managed Modes An exit from any of the power managed modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power managed modes. The clocking subsystem actions are discussed in each of the power managed modes (see Sections 3.2 through 3.4). Device behavior during Low-Power mode exits is summarized in Table 3-3. 3.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit a power managed mode and resume full power operation. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Low-Power mode by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “Interrupts”). Note: If application code is timing sensitive, it should wait for the OSTS bit to become set before continuing. Use the interval during the low-power exit sequence (before OSTS is set) to perform timing insensitive “housekeeping” tasks.© 2007 Microchip Technology Inc. DS39605F-page 29 PIC18F1220/1320 TABLE 3-3: ACTIVITY AND EXIT DELAY ON WAKE FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock in Power Managed Mode Primary System Clock Power Managed Mode Exit Delay Clock Ready Status Bit (OSCCON) Activity during Wake-up from Power Managed Mode Exit by Interrupt Exit by Reset Primary System Clock (PRI_IDLE mode) LP, XT, HS 5-10 μs(5) OSTS CPU and peripherals clocked by primary clock and executing instructions. Not clocked or Two-Speed Start-up (if enabled)(3). HSPLL EC, RC, INTRC(1) — INTOSC(2) IOFS T1OSC or INTRC(1) LP, XT, HS OST OSTS CPU and peripherals clocked by selected power managed mode clock and executing instructions until primary clock source becomes ready. HSPLL OST + 2 ms EC, RC, INTRC(1) 5-10 μs(5) — INTOSC(2) 1 ms(4) IOFS INTOSC(2) LP, XT, HS OST OSTS HSPLL OST + 2 ms EC, RC, INTRC(1) 5-10 μs(5) — INTOSC(2) None IOFS Sleep mode LP, XT, HS OST OSTS Not clocked or Two-Speed Start-up (if enabled) until primary clock source becomes ready(3). HSPLL OST + 2 ms EC, RC, INTRC(1) 5-10 μs(5) — INTOSC(2) 1 ms(4) IOFS Note 1: In this instance, refers specifically to the INTRC clock source. 2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies. 3: Two-Speed Start-up is covered in greater detail in Section 19.3 “Two-Speed Start-up”. 4: Execution continues during the INTOSC stabilization period. 5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other required delays (see Section 3.3 “Idle Modes”).PIC18F1220/1320 DS39605F-page 30 © 2007 Microchip Technology Inc. 3.5.2 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock (defined in Configuration Register 1H) becomes ready. At that time, the OSTS bit is set and the device begins executing code. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 19.3 “Two-Speed Start-up”) or Fail-Safe Clock Monitor (see Section 19.4 “Fail-Safe Clock Monitor”) are enabled in Configuration Register 1H, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Since the OSCCON register is cleared following all Resets, the INTRC clock source is selected. A higher speed clock may be selected by modifying the IRCF bits in the OSCCON register. Execution is clocked by the internal oscillator block until either the primary clock becomes ready, or a power managed mode is entered before the primary clock becomes ready; the primary clock is then shut down. 3.5.3 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions, depending on which power managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in a wake from the power managed mode (see Sections 3.2 through 3.4). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 19.2 “Watchdog Timer (WDT)”). The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the system clock source. 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power managed modes do not invoke the OST at all. These are: • PRI_IDLE mode, where the primary clock source is not stopped; or • the primary clock source is not any of LP, XT, HS or HSPLL modes. In these cases, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay (approximately 10 μs) following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 3.6 INTOSC Frequency Drift The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz (see Table 22-6). However, this frequency may drift as VDD or temperature changes, which can affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register (Register 2-1). This has the side effect that the INTRC clock source frequency is also affected. However, the features that use the INTRC source often do not require an exact frequency. These features include the Fail-Safe Clock Monitor, the Watchdog Timer and the RC_RUN/ RC_IDLE modes when the INTRC clock source is selected. Being able to adjust the INTOSC requires knowing when an adjustment is required, in which direction it should be made and in some cases, how large a change is needed. Three examples follow but other techniques may be used.© 2007 Microchip Technology Inc. DS39605F-page 31 PIC18F1220/1320 3.6.1 EXAMPLE – EUSART An adjustment may be indicated when the EUSART begins to generate framing errors, or receives data with errors while in Asynchronous mode. Framing errors indicate that the system clock frequency is too high – try decrementing the value in the OSCTUNE register to reduce the system clock frequency. Errors in data may suggest that the system clock speed is too low – increment OSCTUNE. 3.6.2 EXAMPLE – TIMERS This technique compares system clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast – decrement OSCTUNE. 3.6.3 EXAMPLE – CCP IN CAPTURE MODE A CCP module can use free running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast – decrement OSCTUNE. If the measured time is much less than the calculated time, the internal oscillator block is running too slow – increment OSCTUNE.PIC18F1220/1320 DS39605F-page 32 © 2007 Microchip Technology Inc. NOTES:© 2007 Microchip Technology Inc. DS39605F-page 33 PIC18F1220/1320 4.0 RESET The PIC18F1220/1320 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state”, depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register (Register 4-1), RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 4-2. These bits are used in software to determine the nature of the Reset. See Table 4-3 for a full description of the Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. The Enhanced MCU devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. The MCLR input provided by the MCLR pin can be disabled with the MCLRE bit in Configuration Register 3H (CONFIG3H<7>). FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT S R Q External Reset MCLR VDD OSC1 WDT Time-out VDD Rise Detect OST/PWRT INTRC(1) POR Pulse OST 10-bit Ripple Counter PWRT Chip_Reset 11-bit Ripple Counter Enable OST(2) Enable PWRT Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 4-1 for time-out situations. Brown-out Reset BOR RESET Instruction Stack Pointer Stack Full/Underflow Reset Sleep ( )_IDLE 1024 Cycles 65.5 ms 32 μs MCLREPIC18F1220/1320 DS39605F-page 34 © 2007 Microchip Technology Inc. 4.1 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin through a resistor (1k to 10 kΩ) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. FIGURE 4-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) 4.2 Power-up Timer (PWRT) The Power-up Timer (PWRT) of the PIC18F1220/1320 is an 11-bit counter, which uses the INTRC source as the clock input. This yields a count of 2048 x 32 μs = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay will vary from chip-to-chip due to VDD, temperature and process variation. See DC parameter 33 for details. The PWRT is enabled by clearing configuration bit, PWRTEN. 4.3 Oscillator Start-up Timer (OST) The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter 33). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset, or on exit from most low-power modes. 4.4 PLL Lock Time-out With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the Oscillator Start-up Time-out. 4.5 Brown-out Reset (BOR) A configuration bit, BOR, can disable (if clear/ programmed), or enable (if set) the Brown-out Reset circuitry. If VDD falls below VBOR (parameter D005) for greater than TBOR (parameter 35), the brown-out situation will reset the chip. A Reset may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT (parameter 33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. Enabling BOR Reset does not automatically enable the PWRT. 4.6 Time-out Sequence On power-up, the time-out sequence is as follows: First, after the POR pulse has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel. Table 4-2 shows the Reset conditions for some Special Function Registers, while Table 4-3 shows the Reset conditions for all the registers. Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 kΩ is recommended to make sure that the voltage drop across R does not violate the device’s electrical specification. 3: R1 ≥ 1 kΩ will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). C R1 D R VDD MCLR PIC18FXXXX VDD© 2007 Microchip Technology Inc. DS39605F-page 35 PIC18F1220/1320 TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS REGISTER 4-1: RCON REGISTER BITS AND POSITIONS TABLE 4-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Oscillator Configuration Power-up(2) and Brown-out Exit from Low-Power Mode PWRTEN = 0 PWRTEN = 1 HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) 5-10 μs(3) 5-10 μs(3) RC, RCIO 66 ms(1) 5-10 μs(3) 5-10 μs(3) INTIO1, INTIO2 66 ms(1) 5-10 μs(3) 5-10 μs(3) Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the 4x PLL to lock. 3: The program memory bias start-up time is always invoked on POR, wake-up from Sleep, or on any exit from power managed mode that disables the CPU and instruction execution. R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IPEN — — RI TO PD POR BOR bit 7 bit 0 Note: Refer to Section 5.14 “RCON Register” for bit definitions. Condition Program Counter RCON Register RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 0--1 1100 1 1 1 0 0 0 0 RESET Instruction 0000h 0--0 uuuu 0 u u u u u u Brown-out 0000h 0--1 11u- 1 1 1 u 0 u u MCLR during Power Managed Run modes 0000h 0--u 1uuu u 1 u u u u u MCLR during Power Managed Idle modes and Sleep 0000h 0--u 10uu u 1 0 u u u u WDT Time-out during Full Power or Power Managed Run 0000h 0--u 0uuu u 0 u u u u u MCLR during Full Power Execution 0000h 0--u uuuu u u u u u u u Stack Full Reset (STVR = 1) 1 u Stack Underflow Reset (STVR = 1) u 1 Stack Underflow Error (not an actual Reset, STVR = 0) 0000h u--u uuuu u u u u u u 1 WDT Time-out during Power Managed Idle or Sleep PC + 2 u--u 00uu u 0 0 u u u u Interrupt Exit from Power Managed modes PC + 2 u--u u0uu u u 0 u u u u Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h).PIC18F1220/1320 DS39605F-page 36 © 2007 Microchip Technology Inc. TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TOSU 1220 1320 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 1220 1320 0000 0000 0000 0000 uuuu uuuu(3) TOSL 1220 1320 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 1220 1320 00-0 0000 00-0 0000 uu-u uuuu(3) PCLATU 1220 1320 ---0 0000 ---0 0000 ---u uuuu PCLATH 1220 1320 0000 0000 0000 0000 uuuu uuuu PCL 1220 1320 0000 0000 0000 0000 PC + 2(2) TBLPTRU 1220 1320 --00 0000 --00 0000 --uu uuuu TBLPTRH 1220 1320 0000 0000 0000 0000 uuuu uuuu TBLPTRL 1220 1320 0000 0000 0000 0000 uuuu uuuu TABLAT 1220 1320 0000 0000 0000 0000 uuuu uuuu PRODH 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 1220 1320 0000 000x 0000 000u uuuu uuuu(1) INTCON2 1220 1320 1111 -1-1 1111 -1-1 uuuu -u-u(1) INTCON3 1220 1320 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 1220 1320 N/A N/A N/A POSTINC0 1220 1320 N/A N/A N/A POSTDEC0 1220 1320 N/A N/A N/A PREINC0 1220 1320 N/A N/A N/A PLUSW0 1220 1320 N/A N/A N/A FSR0H 1220 1320 ---- 0000 ---- 0000 ---- uuuu FSR0L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu WREG 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 1220 1320 N/A N/A N/A POSTINC1 1220 1320 N/A N/A N/A POSTDEC1 1220 1320 N/A N/A N/A PREINC1 1220 1320 N/A N/A N/A PLUSW1 1220 1320 N/A N/A N/A FSR1H 1220 1320 ---- 0000 ---- 0000 ---- uuuu FSR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: Bit 5 of PORTA is enabled if MCLR is disabled.© 2007 Microchip Technology Inc. DS39605F-page 37 PIC18F1220/1320 BSR 1220 1320 ---- 0000 ---- 0000 ---- uuuu INDF2 1220 1320 N/A N/A N/A POSTINC2 1220 1320 N/A N/A N/A POSTDEC2 1220 1320 N/A N/A N/A PREINC2 1220 1320 N/A N/A N/A PLUSW2 1220 1320 N/A N/A N/A FSR2H 1220 1320 ---- 0000 ---- 0000 ---- uuuu FSR2L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 1220 1320 ---x xxxx ---u uuuu ---u uuuu TMR0H 1220 1320 0000 0000 0000 0000 uuuu uuuu TMR0L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 1220 1320 1111 1111 1111 1111 uuuu uuuu OSCCON 1220 1320 0000 q000 0000 q000 uuuu qquu LVDCON 1220 1320 --00 0101 --00 0101 --uu uuuu WDTCON 1220 1320 ---- ---0 ---- ---0 ---- ---u RCON(4) 1220 1320 0--1 11q0 0--q qquu u--u qquu TMR1H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 1220 1320 0000 0000 u0uu uuuu uuuu uuuu TMR2 1220 1320 0000 0000 0000 0000 uuuu uuuu PR2 1220 1320 1111 1111 1111 1111 1111 1111 T2CON 1220 1320 -000 0000 -000 0000 -uuu uuuu ADRESH 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1220 1320 00-0 0000 00-0 0000 uu-u uuuu ADCON1 1220 1320 -000 0000 -000 0000 -uuu uuuu ADCON2 1220 1320 0-00 0000 0-00 0000 u-uu uuuu CCPR1H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 1220 1320 0000 0000 0000 0000 uuuu uuuu PWM1CON 1220 1320 0000 0000 0000 0000 uuuu uuuu ECCPAS 1220 1320 0000 0000 0000 0000 uuuu uuuu TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: Bit 5 of PORTA is enabled if MCLR is disabled.PIC18F1220/1320 DS39605F-page 38 © 2007 Microchip Technology Inc. TMR3H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 1220 1320 0-00 0000 u-uu uuuu u-uu uuuu SPBRGH 1220 1320 0000 0000 0000 0000 uuuu uuuu SPBRG 1220 1320 0000 0000 0000 0000 uuuu uuuu RCREG 1220 1320 0000 0000 0000 0000 uuuu uuuu TXREG 1220 1320 0000 0000 0000 0000 uuuu uuuu TXSTA 1220 1320 0000 0010 0000 0010 uuuu uuuu RCSTA 1220 1320 0000 000x 0000 000x uuuu uuuu BAUDCTL 1220 1320 -1-1 0-00 -1-1 0-00 -u-u u-uu EEADR 1220 1320 0000 0000 0000 0000 uuuu uuuu EEDATA 1220 1320 0000 0000 0000 0000 uuuu uuuu EECON2 1220 1320 0000 0000 0000 0000 0000 0000 EECON1 1220 1320 xx-0 x000 uu-0 u000 uu-0 u000 IPR2 1220 1320 1--1 -11- 1--1 -11- u--u -uuPIR2 1220 1320 0--0 -00- 0--0 -00- u--u -uu-(1) PIE2 1220 1320 0--0 -00- 0--0 -00- u--u -uuIPR1 1220 1320 -111 -111 -111 -111 -uuu -uuu PIR1 1220 1320 -000 -000 -000 -000 -uuu -uuu(1) PIE1 1220 1320 -000 -000 -000 -000 -uuu -uuu OSCTUNE 1220 1320 --00 0000 --00 0000 --uu uuuu TRISB 1220 1320 1111 1111 1111 1111 uuuu uuuu TRISA(5) 1220 1320 11-1 1111(5) 11-1 1111(5) uu-u uuuu(5) LATB 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 1220 1320 xx-x xxxx(5) uu-u uuuu(5) uu-u uuuu(5) PORTB 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5,6) 1220 1320 xx0x 0000(5,6) uu0u 0000(5,6) uuuu uuuu(5,6) TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: Bit 5 of PORTA is enabled if MCLR is disabled.© 2007 Microchip Technology Inc. DS39605F-page 39 PIC18F1220/1320 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 TPWRT TOST VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TPWRT TOST VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TPWRT TOSTPIC18F1220/1320 DS39605F-page 40 © 2007 Microchip Technology Inc. FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 0V 1V 5V TPWRT TOST TPWRT TOST VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET PLL TIME-OUT TPLL Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer.© 2007 Microchip Technology Inc. DS39605F-page 41 PIC18F1220/1320 5.0 MEMORY ORGANIZATION There are three memory types in Enhanced MCU devices. These memory types are: • Program Memory • Data RAM • Data EEPROM Data and program memory use separate busses, which allows for concurrent access of these types. Additional detailed information for Flash program memory and data EEPROM is provided in Section 6.0 “Flash Program Memory” and Section 7.0 “Data EEPROM Memory”, respectively. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F1220 5.1 Program Memory Organization A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all ‘0’s (a NOP instruction). The PIC18F1220 has 4 Kbytes of Flash memory and can store up to 2,048 single-word instructions. The PIC18F1320 has 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory maps for the PIC18F1220 and PIC18F1320 devices are shown in Figure 5-1 and Figure 5-2, respectively. FIGURE 5-2: PROGRAM MEMORY MAP AND STACK FOR PIC18F1320 PC<20:0> Stack Level 1 • Stack Level 31 Reset Vector Low Priority Interrupt Vector • • CALL,RCALL,RETURN RETFIE,RETLW 21 0000h 0018h On-Chip Program Memory High Priority Interrupt Vector 0008h User Memory Space 1FFFFFh 1000h 0FFFh Read ‘0’ 200000h PC<20:0> Stack Level 1 • Stack Level 31 Reset Vector Low Priority Interrupt Vector • • CALL,RCALL,RETURN RETFIE,RETLW 21 0000h 0018h 2000h 1FFFh On-Chip Program Memory High Priority Interrupt Vector 0008h User Memory Space Read ‘0’ 1FFFFFh 200000hPIC18F1220/1320 DS39605F-page 42 © 2007 Microchip Technology Inc. 5.2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The stack operates as a 31-word by 21-bit RAM and a 5-bit stack pointer, with the Stack Pointer initialized to 00000B after all Resets. There is no RAM associated with Stack Pointer, 00000B. This is only a Reset value. During a CALL type instruction, causing a push onto the stack, the Stack Pointer is first incremented and the RAM location pointed to by the Stack Pointer (STKPTR) register is written with the contents of the PC (already pointing to the instruction following the CALL). During a RETURN type instruction, causing a pop from the stack, the contents of the RAM location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the top-of-stack Special File Registers. Data can also be pushed to or popped from the stack using the top-of-stack SFRs. Status bits indicate if the stack is full, has overflowed or underflowed. 5.2.1 TOP-OF-STACK ACCESS The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 5-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These values can be placed on a user defined software stack. At return time, the software can replace the TOSU, TOSH and TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. 5.2.2 RETURN STACK POINTER (STKPTR) The STKPTR register (Register 5-1) contains the stack pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. At Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVR (Stack Overflow Reset Enable) configuration bit. (Refer to Section 19.1 “Configuration Bits” for a description of the device configuration bits.) If STVR is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVR is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or a POR occurs. FIGURE 5-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. 00011 001A34h 11111 11110 11101 00010 00001 00000 00010 Return Address Stack Top-of-Stack 000D58h TOSU TOSH TOSL 00h 1Ah 34h STKPTR<4:0>© 2007 Microchip Technology Inc. DS39605F-page 43 PIC18F1220/1320 REGISTER 5-1: STKPTR REGISTER 5.2.3 PUSH AND POP INSTRUCTIONS Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execution, is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the Stack Pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place data or a return address on the stack. The ability to pull the TOS value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the POP instruction. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. 5.2.4 STACK FULL/UNDERFLOW RESETS These Resets are enabled by programming the STVR bit in Configuration Register 4L. When the STVR bit is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset. When the STVR bit is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7(1) STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6(1) STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 44 © 2007 Microchip Technology Inc. 5.3 Fast Register Stack A “fast return” option is available for interrupts. A fast register stack is provided for the Status, WREG and BSR registers and is only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the registers are then loaded back into the working registers, if the RETFIE, FAST instruction is used to return from the interrupt. All interrupt sources will push values into the stack registers. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. Users must save the key registers in software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. If no interrupts are used, the fast register stack can be used to restore the Status, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a CALL LABEL, FAST instruction must be executed to save the Status, WREG and BSR registers to the fast register stack. A RETURN, FAST instruction is then executed to restore these registers from the fast register stack. Example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. EXAMPLE 5-1: FAST REGISTER STACK CODE EXAMPLE 5.4 PCL, PCLATH and PCLATU The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bits wide. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register may be performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits and is not directly readable or writable. Updates to the PCU register may be performed through the PCLATU register. The contents of PCLATH and PCLATU will be transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.8.1 “Computed GOTO”). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the LSB of PCL is fixed to a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK • • SUB1 • • RETURN, FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK© 2007 Microchip Technology Inc. DS39605F-page 45 PIC18F1220/1320 5.5 Clocking Scheme/Instruction Cycle The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the Program Counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-4. 5.6 Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-2). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 5-4: CLOCK/INSTRUCTION CYCLE EXAMPLE 5-2: INSTRUCTION PIPELINE FLOW Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC Mode) PC PC + 2 PC + 4 Fetch INST (PC) Execute INST (PC – 2) Fetch INST (PC + 2) Execute INST (PC) Fetch INST (PC + 4) Execute INST (PC + 2) Internal Phase Clock All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1PIC18F1220/1320 DS39605F-page 46 © 2007 Microchip Technology Inc. 5.7 Instructions in Program Memory The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 5-5 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’ (see Section 5.4 “PCL, PCLATH and PCLATU”). The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-5 shows how the instruction ‘GOTO 000006h’ is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 20.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 5-5: INSTRUCTIONS IN PROGRAM MEMORY 5.7.1 TWO-WORD INSTRUCTIONS PIC18F1220/1320 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to ‘1’s and is decoded as a NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two-word instruction is preceded by a conditional instruction that results in a skip operation. A program example that demonstrates this concept is shown in Example 5-3. Refer to Section 20.0 “Instruction Set Summary” for further details of the instruction set. EXAMPLE 5-3: TWO-WORD INSTRUCTIONS Word Address LSB = 1 LSB = 0 ↓ Program Memory Byte Locations → 000000h 000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 000006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code© 2007 Microchip Technology Inc. DS39605F-page 47 PIC18F1220/1320 5.8 Look-up Tables Look-up tables are implemented two ways: • Computed GOTO • Table Reads 5.8.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (see Example 5-4). A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions, that returns the value 0xnn to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSB = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. EXAMPLE 5-4: COMPUTED GOTO USING AN OFFSET VALUE 5.8.2 TABLE READS/TABLE WRITES A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to/from program memory, one byte at a time. The table read/table write operation is discussed further in Section 6.1 “Table Reads and Table Writes”. 5.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 5-6 shows the data memory organization for the PIC18F1220/1320 devices. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented. The data memory contains Special Function Registers (SFR) and General Purpose Registers (GPR). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratch pad operations in the user’s application. The SFRs start at the last location of Bank 15 (FFFh) and extend towards F80h. Any remaining space beyond the SFRs in the Bank may be implemented as GPRs. GPRs start at the first location of Bank 0 and grow upwards. Any read of an unimplemented location will read as ‘0’s. The entire data memory may be accessed directly or indirectly. Direct addressing may require the use of the BSR register. Indirect addressing requires the use of a File Select Register (FSRn) and a corresponding Indirect File Operand (INDFn). Each FSR holds a 12-bit address value that can be used to access any location in the Data Memory map without banking. See Section 5.12 “Indirect Addressing, INDF and FSR Registers” for indirect addressing details. The instruction set and architecture allow operations across all banks. This may be accomplished by indirect addressing or by the use of the MOVFF instruction. The MOVFF instruction is a two-word/two-cycle instruction that moves a value from one register to another. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 5.10 “Access Bank” provides a detailed description of the Access RAM. 5.9.1 GENERAL PURPOSE REGISTER FILE Enhanced MCU devices may have banked memory in the GPR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Data RAM is available for use as GPR registers by all instructions. The second half of Bank 15 (F80h to FFFh) contains SFRs. All other banks of data memory contain GPRs, starting with Bank 0. MOVFW OFFSET CALL TABLE ORG 0xnn00 TABLE ADDWF PCL RETLW 0xnn RETLW 0xnn RETLW 0xnn . . .PIC18F1220/1320 DS39605F-page 48 © 2007 Microchip Technology Inc. FIGURE 5-6: DATA MEMORY MAP FOR PIC18F1220/1320 DEVICES Bank 0 Bank 14 Bank 15 BSR<3:0> Data Memory Map = 0000 = 1111 080h 07Fh F80h FFFh 00h 7Fh 80h FFh Access Bank When a = 0, The BSR is ignored and the Access Bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When a = 1, The BSR specifies the Bank used by the instruction. F7Fh F00h EFFh 0FFh 000h Access RAM FFh 00h FFh 00h GPR SFR Unused Access RAM High Access RAM Low Bank 1 to Unused = 1110 Read ‘00h’ = 0001 (SFRs)© 2007 Microchip Technology Inc. DS39605F-page 49 PIC18F1220/1320 5.9.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the “core” function and those related to the peripheral functions. Those registers related to the “core” are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control. The unused SFR locations will be unimplemented and read as ‘0’s. TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F1220/1320 DEVICES Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(2) FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(2) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(2) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(2) FBCh — F9Ch — FFBh PCLATU FDBh PLUSW2(2) FBBh — F9Bh OSCTUNE FFAh PCLATH FDAh FSR2H FBAh — F9Ah — FF9h PCL FD9h FSR2L FB9h — F99h — FF8h TBLPTRU FD8h STATUS FB8h — F98h — FF7h TBLPTRH FD7h TMR0H FB7h PWM1CON F97h — FF6h TBLPTRL FD6h TMR0L FB6h ECCPAS F96h — FF5h TABLAT FD5h T0CON FB5h — F95h — FF4h PRODH FD4h — FB4h — F94h — FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h — FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h — FEFh INDF0(2) FCFh TMR1H FAFh SPBRG F8Fh — FEEh POSTINC0(2) FCEh TMR1L FAEh RCREG F8Eh — FEDh POSTDEC0(2) FCDh T1CON FADh TXREG F8Dh — FECh PREINC0(2) FCCh TMR2 FACh TXSTA F8Ch — FEBh PLUSW0(2) FCBh PR2 FABh RCSTA F8Bh — FEAh FSR0H FCAh T2CON FAAh BAUDCTL F8Ah LATB FE9h FSR0L FC9h — FA9h EEADR F89h LATA FE8h WREG FC8h — FA8h EEDATA F88h — FE7h INDF1(2) FC7h — FA7h EECON2 F87h — FE6h POSTINC1(2) FC6h — FA6h EECON1 F86h — FE5h POSTDEC1(2) FC5h — FA5h — F85h — FE4h PREINC1(2) FC4h ADRESH FA4h — F84h — FE3h PLUSW1(2) FC3h ADRESL FA3h — F83h — FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h — FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: Unimplemented registers are read as ‘0’. 2: This is not a physical register.PIC18F1220/1320 DS39605F-page 50 © 2007 Microchip Technology Inc. TABLE 5-2: REGISTER FILE SUMMARY (PIC18F1220/1320) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 36, 42 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 36, 42 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 36, 42 STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 36, 43 PCLATU — — bit 21(3) Holding Register for PC<20:16> ---0 0000 36, 44 PCLATH Holding Register for PC<15:8> 0000 0000 36, 44 PCL PC Low Byte (PC<7:0>) 0000 0000 36, 44 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 36, 60 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 36, 60 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 36, 60 TABLAT Program Memory Table Latch 0000 0000 36, 60 PRODH Product Register High Byte xxxx xxxx 36, 71 PRODL Product Register Low Byte xxxx xxxx 36, 71 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 36, 75 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 36, 76 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 36, 77 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 36, 53 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 36, 53 POSTDEC0 Uses contents of FSR0 to address data memory– value of FSR0 post-decremented (not a physical register) N/A 36, 53 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 36, 53 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register) N/A 36, 53 FSR0H — — — — Indirect Data Memory Address Pointer 0 High ---- 0000 36, 53 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 36, 53 WREG Working Register xxxx xxxx 36 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 36, 53 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 36, 53 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 36, 53 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 36, 53 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register) N/A 36, 53 FSR1H — — — — Indirect Data Memory Address Pointer 1 High ---- 0000 36, 53 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 36, 53 BSR — — — — Bank Select Register ---- 0000 37, 52 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 37, 53 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 37, 53 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 37, 53 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 37, 53 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register) N/A 37, 53 FSR2H — — — — Indirect Data Memory Address Pointer 2 High ---- 0000 37, 53 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 37, 53 STATUS — — — N OV Z DC C ---x xxxx 37, 55 TMR0H Timer0 Register High Byte 0000 0000 37, 101 TMR0L Timer0 Register Low Byte xxxx xxxx 37, 101 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 37, 99 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000 37, 17 LVDCON — — IVRST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 37, 167 WDTCON — — — — — — — SWDTEN --- ---0 37, 180 RCON IPEN — — RI TO PD POR BOR 0--1 11q0 35, 56, 84 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read ‘0’ in all other oscillator modes. 2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes. 3: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 4: The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RA5 reads ‘0’. This bit is read-only.© 2007 Microchip Technology Inc. DS39605F-page 51 PIC18F1220/1320 TMR1H Timer1 Register High Byte xxxx xxxx 37, 108 TMR1L Timer1 Register Low Byte xxxx xxxx 37, 108 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 37, 103 TMR2 Timer2 Register 0000 0000 37, 109 PR2 Timer2 Period Register 1111 1111 37, 109 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 37, 109 ADRESH A/D Result Register High Byte xxxx xxxx 37, 164 ADRESL A/D Result Register Low Byte xxxx xxxx 37, 164 ADCON0 VCFG1 VCFG0 — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 37, 155 ADCON1 — PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 37, 156 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 37, 157 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 37. 116 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 37, 116 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 37, 115 PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 37, 126 ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 37, 127 TMR3H Timer3 Register High Byte xxxx xxxx 38, 113 TMR3L Timer3 Register Low Byte xxxx xxxx 38, 113 T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 38, 111 SPBRGH EUSART Baud Rate Generator High Byte 0000 0000 38 SPBRG EUSART Baud Rate Generator Low Byte 0000 0000 38, 135 RCREG EUSART Receive Register 0000 0000 38, 143, 142 TXREG EUSART Transmit Register 0000 0000 38, 140, 142 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 38, 132 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 38, 133 BAUDCTL — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 38 EEADR EEPROM Address Register 0000 0000 38, 67 EEDATA EEPROM Data Register 0000 0000 38, 70 EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 38, 58, 67 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 38, 59, 68 IPR2 OSCFIP — — EEIP — LVDIP TMR3IP — 1--1 -11- 38, 83 PIR2 OSCFIF — — EEIF — LVDIF TMR3IF — 0--0 -00- 38, 79 PIE2 OSCFIE — — EEIE — LVDIE TMR3IE — 0--0 -00- 38, 81 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 38, 82 PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 38, 78 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 38, 80 OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 38, 15 TRISB Data Direction Control Register for PORTB 1111 1111 38, 98 TRISA TRISA7(2) TRISA6(1) — Data Direction Control Register for PORTA 11-1 1111 38, 89 LATB Read/Write PORTB Data Latch xxxx xxxx 38, 98 LATA LATA<7>(2) LATA<6>(1) — Read/Write PORTA Data Latch xx-x xxxx 38, 89 PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 38, 98 PORTA RA7(2) RA6(1) RA5(4) Read PORTA pins, Write PORTA Data Latch xx0x 0000 38, 89 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F1220/1320) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read ‘0’ in all other oscillator modes. 2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes. 3: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 4: The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RA5 reads ‘0’. This bit is read-only.PIC18F1220/1320 DS39605F-page 52 © 2007 Microchip Technology Inc. 5.10 Access Bank The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. This data memory region can be used for: • Intermediate computational values • Local variables of subroutines • Faster context saving/switching of variables • Common variables • Faster evaluation/control of SFRs (no banking) The Access Bank is comprised of the last 128 bytes in Bank 15 (SFRs) and the first 128 bytes in Bank 0. These two sections will be referred to as Access RAM High and Access RAM Low, respectively. Figure 5-6 indicates the Access RAM areas. A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register or in the Access Bank. This bit is denoted as the ‘a’ bit (for access bit). When forced in the Access Bank (a = 0), the last address in Access RAM Low is followed by the first address in Access RAM High. Access RAM High maps the Special Function Registers, so these registers can be accessed without any software overhead. This is useful for testing status flags and modifying control bits. 5.11 Bank Select Register (BSR) The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into as many as sixteen banks. When using direct addressing, the BSR should be configured for the desired bank. BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read ‘0’s and writes will have no effect (see Figure 5-7). A MOVLB instruction has been provided in the instruction set to assist in selecting banks. If the currently selected bank is not implemented, any read will return all ‘0’s and all writes are ignored. The Status register bits will be set/cleared as appropriate for the instruction performed. Each Bank extends up to FFh (256 bytes). All data memory is implemented as static RAM. A MOVFF instruction ignores the BSR, since the 12-bit addresses are embedded into the instruction word. Section 5.12 “Indirect Addressing, INDF and FSR Registers” provides a description of indirect addressing, which allows linear addressing of the entire RAM space. FIGURE 5-7: DIRECT ADDRESSING Note 1: For register file map detail, see Table 5-1. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. Data Memory(1) Direct Addressing Bank Select(2) Location Select(3) BSR<3:0> 7 From Opcode 0 (3) 00h 01h 0Eh 0Fh Bank 0 Bank 1 Bank 14 Bank 15 1FFh 100h 0FFh 000h EFFh E00h FFFh F00h BSR<7:4> 000 0© 2007 Microchip Technology Inc. DS39605F-page 53 PIC18F1220/1320 5.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 5-8 shows how the fetched instruction is modified prior to being executed. Indirect addressing is possible by using one of the INDF registers. Any instruction, using the INDF register, actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = 0), will read 00h. Writing to the INDF register indirectly, results in a no operation (NOP). The FSR register contains a 12-bit address, which is shown in Figure 5-9. The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose address is contained in the FSRn register (FSRn is a pointer). This is indirect addressing. Example 5-5 shows a simple use of indirect addressing to clear the RAM in Bank 1 (locations 100h-1FFh) in a minimum number of instructions. EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING There are three indirect addressing registers. To address the entire data memory space (4096 bytes), these registers are 12-bit wide. To store the 12 bits of addressing information, two 8-bit registers are required: 1. FSR0: composed of FSR0H:FSR0L 2. FSR1: composed of FSR1H:FSR1L 3. FSR2: composed of FSR2H:FSR2L In addition, there are registers INDF0, INDF1 and INDF2, which are not physically implemented. Reading or writing to these registers activates indirect addressing, with the value in the corresponding FSR register being the address of the data. If an instruction writes a value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads the data from the address pointed to by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. If INDF0, INDF1 or INDF2 are read indirectly via an FSR, all ‘0’s are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the Status bits are not affected. 5.12.1 INDIRECT ADDRESSING OPERATION Each FSR register has an INDF register associated with it, plus four additional register addresses. Performing an operation using one of these five registers determines how the FSR will be modified during indirect addressing. When data access is performed using one of the five INDFn locations, the address selected will configure the FSRn register to: • Do nothing to FSRn after an indirect access (no change) – INDFn • Auto-decrement FSRn after an indirect access (post-decrement) – POSTDECn • Auto-increment FSRn after an indirect access (post-increment) – POSTINCn • Auto-increment FSRn before an indirect access (pre-increment) – PREINCn • Use the value in the WREG register as an offset to FSRn. Do not modify the value of the WREG or the FSRn register after an indirect access (no change) – PLUSWn When using the auto-increment or auto-decrement features, the effect on the FSR is not reflected in the Status register. For example, if the indirect address causes the FSR to equal ‘0’, the Z bit will not be set. Auto-incrementing or auto-decrementing an FSR affects all 12 bits. That is, when FSRnL overflows from an increment, FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a stack pointer, in addition to its uses for table operations in data memory. Each FSR has an address associated with it that performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the FSRn is configured to add the signed value in the WREG register and the value in FSR to form the address before an indirect access. The FSR value is not changed. The WREG offset range is -128 to +127. If an FSR register contains a value that points to one of the INDFn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a NOP (Status bits are not affected). If an indirect addressing write is performed when the target address is an FSRnH or FSRnL register, the data is written to the FSR register, but no pre- or post-increment/ decrement is performed. LFSR FSR0,0x100 ; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H, 1 ; All done with ; Bank1? GOTO NEXT ; NO, clear next CONTINUE ; YES, continue PIC18F1220/1320 DS39605F-page 54 © 2007 Microchip Technology Inc. FIGURE 5-8: INDIRECT ADDRESSING OPERATION FIGURE 5-9: INDIRECT ADDRESSING Opcode Address File Address = Access of an Indirect Addressing Register FSR Instruction Executed Instruction Fetched RAM Opcode File 12 12 12 BSR<3:0> 4 8 0h FFFh Note 1: For register file map detail, see Table 5-1. Data Memory(1) Indirect Addressing FSRnH:FSRnL 3 0 0FFFh 0000h Location Select 11 0 0 7© 2007 Microchip Technology Inc. DS39605F-page 55 PIC18F1220/1320 5.13 Status Register The Status register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the Status register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed. Therefore, the result of an instruction with the Status register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the Status register, because these instructions do not affect the Z, C, DC, OV or N bits in the Status register. For other instructions that do not affect Status bits, see the instruction set summaries in Table 20-1. REGISTER 5-2: STATUS REGISTER Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. bit 0 C: Carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 56 © 2007 Microchip Technology Inc. 5.14 RCON Register The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. REGISTER 5-3: RCON REGISTER Note 1: If the BOR configuration bit is set (Brownout Reset enabled), the BOR bit is ‘1’ on a Power-on Reset. After a Brown-out Reset has occurred, the BOR bit will be cleared and must be set by firmware to indicate the occurrence of the next Brown-out Reset. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Cleared by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 57 PIC18F1220/1320 6.0 FLASH PROGRAM MEMORY The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A “Bulk Erase” operation may not be issued from user code. While writing or erasing program memory, instruction fetches cease until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: • Table Read (TBLRD) • Table Write (TBLWT) The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into TABLAT in the data RAM space. Figure 6-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from TABLAT in the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5 “Writing to Flash Program Memory”. Figure 6-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned (TBLPTRL<0> = 0). The EEPROM on-chip timer controls the write and erase times. The write and erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. FIGURE 6-1: TABLE READ OPERATION Table Pointer(1) Table Latch (8-bit) Program Memory TBLPTRH TBLPTRL TABLAT TBLPTRU Instruction: TBLRD* Note 1: Table Pointer points to a byte in program memory. Program Memory (TBLPTR)PIC18F1220/1320 DS39605F-page 58 © 2007 Microchip Technology Inc. FIGURE 6-2: TABLE WRITE OPERATION 6.2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: • EECON1 register • EECON2 register • TABLAT register • TBLPTR registers 6.2.1 EECON1 AND EECON2 REGISTERS EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. Control bit, CFGS, determines if the access will be to the configuration registers, or to program memory/data EEPROM memory. When set, subsequent operations access configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The FREE bit controls program memory erase operations. When the FREE bit is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit enables and disables erase and write operations. When set, erase and write operations are allowed. When clear, erase and write operations are disabled – the WR bit cannot be set while the WREN bit is clear. This process helps to prevent accidental writes to memory due to errant (unexpected) code execution. Firmware should keep the WREN bit clear at all times, except when starting erase or write operations. Once firmware has set the WR bit, the WREN bit may be cleared. Clearing the WREN bit will not affect the operation in progress. The WRERR bit is set when a write operation is interrupted by a Reset. In these situations, the user can check the WRERR bit and rewrite the location. It will be necessary to reload the data and address registers (EEDATA and EEADR) as these registers have cleared as a result of the Reset. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.3 “Reading the Flash Program Memory” regarding table reads. Table Pointer(1) Table Latch (8-bit) TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) TBLPTRU Instruction: TBLWT* Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. Holding Registers Program Memory Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software.© 2007 Microchip Technology Inc. DS39605F-page 59 PIC18F1220/1320 REGISTER 6-1: EECON1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access configuration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation – TBLPTR<5:0> are ignored) 0 = Perform write only bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation was prematurely terminated (any Reset during self-timed programming) 0 = The write operation completed normally Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Write Enable bit 1 = Allows erase or write cycles 0 = Inhibits erase or write cycles bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle completed bit 0 RD: Read Control bit 1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Read completed Legend: R = Readable bit S = Settable only U = Unimplemented bit, read as ‘0’ W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 60 © 2007 Microchip Technology Inc. 6.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The table latch is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. Setting the 22nd bit allows access to the device ID, the user ID and the configuration bits. The Table Pointer (TBLPTR) register is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low-order 21 bits. 6.2.4 TABLE POINTER BOUNDARIES TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program or configuration memory into TABLAT. When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight program memory holding registers is written to. When the timed write to program memory (long write) begins, the 19 MSbs of the Table Pointer (TBLPTR<21:3>) will determine which program memory block of 8 bytes is written to (TBLPTR<2:0> are ignored). For more detail, see Section 6.5 “Writing to Flash Program Memory”. When an erase of program memory is executed, the 16 MSbs of the Table Pointer (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*- TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write 21 16 15 8 7 0 ERASE – TBLPTR<21:6> LONG WRITE – TBLPTR<21:3> READ or WRITE – TBLPTR<21:0> TBLPTRU TBLPTRH TBLPTRL© 2007 Microchip Technology Inc. DS39605F-page 61 PIC18F1220/1320 6.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and place it into data RAM. Table reads from program memory are performed one byte at a time. TBLPTR points to a byte address in program space. Executing a TBLRD instruction places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD Odd (High) Byte Program Memory Even (Low) Byte TABLAT TBLPTR Instruction Register (IR) Read Register LSB = 1 TBLPTR LSB = 0 MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment TBLPTR MOVFW TABLAT ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment TBLPTR MOVFW TABLAT ; get data MOVWF WORD_ODDPIC18F1220/1320 DS39605F-page 62 © 2007 Microchip Technology Inc. 6.4 Erasing Flash Program Memory The minimum erase block size is 32 words or 64 bytes under firmware control. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in Flash memory is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The CFGS bit must be clear to access program Flash and data EEPROM memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. The WR bit is set as part of the required instruction sequence (as shown in Example 6-2) and starts the actual erase operation. It is not necessary to load the TABLAT register with any data as it is ignored. For protection, the write initiate sequence using EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. 6.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is: 1. Load Table Pointer with address of row being erased. 2. Set the EECON1 register for the erase operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN bit to enable writes; • set FREE bit to enable the erase. 3. Disable interrupts. 4. Write 55h to EECON2. 5. Write AAh to EECON2. 6. Set the WR bit. This will begin the row erase cycle. 7. The CPU will stall for duration of the erase (about 2 ms using internal timer). 8. Execute a NOP. 9. Re-enable interrupts. EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, EEPGD ; point to FLASH program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55H Required MOVLW AAh Sequence MOVWF EECON2 ; write AAH BSF EECON1, WR ; start erase (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts© 2007 Microchip Technology Inc. DS39605F-page 63 PIC18F1220/1320 6.5 Writing to Flash Program Memory The programming block size is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction must be executed 8 times for each programming operation. All of the table write operations will essentially be short writes, because only the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY 6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. Read 64 bytes into RAM. 2. Update data values in RAM as necessary. 3. Load Table Pointer with address being erased. 4. Do the row erase procedure (see Section 6.4.1 “Flash Program Memory Erase Sequence”). 5. Load Table Pointer with address of first byte being written. 6. Write the first 8 bytes into the holding registers with auto-increment. 7. Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN bit to enable byte writes. 8. Disable interrupts. 9. Write 55h to EECON2. 10. Write AAh to EECON2. 11. Set the WR bit. This will begin the write cycle. 12. The CPU will stall for duration of the write (about 2 ms using internal timer). 13. Execute a NOP. 14. Re-enable interrupts. 15. Repeat steps 6-14 seven times to write 64 bytes. 16. Verify the memory (table read). This procedure will require about 18 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 6-3. Holding Register TABLAT Holding Register TBLPTR = xxxxx7 Holding Register TBLPTR = xxxxx1 Holding Register TBLPTR = xxxxx0 8 8 8 8 Write Register TBLPTR = xxxxx2 Program MemoryPIC18F1220/1320 DS39605F-page 64 © 2007 Microchip Technology Inc. EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64 ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW ; 6 LSB = 0 MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data and increment FSR0 DECFSZ COUNTER ; done? GOTO READ_BLOCK ; repeat MODIFY_WORD MOVLW DATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word and increment FSR0 MOVWF POSTINC0 MOVLW NEW_DATA_HIGH ; update buffer word MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW ; 6 LSB = 0 MOVWF TBLPTRL BCF EECON1, CFGS ; point to PROG/EEPROM memory BSF EECON1, EEPGD ; point to FLASH program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h ; Required sequence MOVWF EECON2 ; write 55H MOVLW AAh MOVWF EECON2 ; write AAH BSF EECON1, WR ; start erase (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts WRITE_BUFFER_BACK MOVLW 8 ; number of write buffer groups of 8 bytes MOVWF COUNTER_HI MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L PROGRAM_LOOP MOVLW 8 ; number of bytes in holding register MOVWF COUNTER© 2007 Microchip Technology Inc. DS39605F-page 65 PIC18F1220/1320 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) 6.5.2 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location. 6.6 Flash Program Operation During Code Protection See Section 19.0 “Special Features of the CPU” for details on code protection of Flash program memory. TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY WRITE_WORD_TO_HREGS MOVF POSTINC0, W ; get low byte of buffer data and increment FSR0 MOVWF TABLAT ; present data to table latch TBLWT+* ; short write ; to internal TBLWT holding register, increment TBLPTR DECFSZ COUNTER ; loop until buffers are full GOTO WRITE_WORD_TO_HREGS PROGRAM_MEMORY BCF INTCON, GIE ; disable interrupts MOVLW 55h ; required sequence MOVWF EECON2 ; write 55H MOVLW AAh MOVWF EECON2 ; write AAH BSF EECON1, WR ; start program (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts DECFSZ COUNTER_HI ; loop until done GOTO PROGRAM_LOOP BCF EECON1, WREN ; disable write to memory Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 --00 0000 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000 TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000 TABLAT Program Memory Table Latch 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u EECON2 EEPROM Control Register 2 (not a physical register) — — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 IPR2 OSCFIP — — EEIP — LVDIP TMR3IP — 1--1 -11- 1--1 -11- PIR2 OSCFIF — — EEIF — LVDIF TMR3IF — 0--0 -00- 0--0 -00- PIE2 OSCFIE — — EEIE — LVDIE TMR3IE — 0--0 -00- 0--0 -00- Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.PIC18F1220/1320 DS39605F-page 66 © 2007 Microchip Technology Inc. NOTES:© 2007 Microchip Technology Inc. DS39605F-page 67 PIC18F1220/1320 7.0 DATA EEPROM MEMORY The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are four SFRs used to read and write the program and data EEPROM memory. These registers are: • EECON1 • EECON2 • EEDATA • EEADR The EEPROM data memory allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. These devices have 256 bytes of data EEPROM with an address range from 00h to FFh. The EEPROM data memory is rated for high erase/ write cycle endurance. A byte write automatically erases the location and writes the new data (erasebefore-write). The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip to chip. Please refer to parameter D122 (Table 22-1 in Section 22.0 “Electrical Characteristics”) for exact limits. 7.1 EEADR The address register can address 256 bytes of data EEPROM. 7.2 EECON1 and EECON2 Registers EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. Control bit, CFGS, determines if the access will be to the configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The WREN bit enables and disables erase and write operations. When set, erase and write operations are allowed. When clear, erase and write operations are disabled – the WR bit cannot be set while the WREN bit is clear. This mechanism helps to prevent accidental writes to memory due to errant (unexpected) code execution. Firmware should keep the WREN bit clear at all times, except when starting erase or write operations. Once firmware has set the WR bit, the WREN bit may be cleared. Clearing the WREN bit will not affect the operation in progress. The WRERR bit is set when a write operation is interrupted by a Reset. In these situations, the user can check the WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EEADR), as these registers have cleared as a result of the Reset. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.1 “Table Reads and Table Writes” regarding table reads. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when write is complete. It must be cleared in software.PIC18F1220/1320 DS39605F-page 68 © 2007 Microchip Technology Inc. REGISTER 7-1: EECON1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation was prematurely terminated (MCLR or WDT Reset during self-timed erase or program operation) 0 = The write operation completed normally Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Erase/Write Enable bit 1 = Allows erase/write cycles 0 = Inhibits erase/write cycles bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle, or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is completed bit 0 RD: Read Control bit 1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Read completed Legend: R = Readable bit S = Settable only U = Unimplemented bit, read as ‘0’ W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 69 PIC18F1220/1320 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation). 7.4 Writing to the Data EEPROM Memory To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 7-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by software. 7.5 Write Verify Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.6 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. EXAMPLE 7-1: DATA EEPROM READ EXAMPLE 7-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW AAh ; MOVWF EECON2 ; Write AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable Interrupts SLEEP ; Wait for interrupt to signal write complete BCF EECON1, WREN ; Disable writesPIC18F1220/1320 DS39605F-page 70 © 2007 Microchip Technology Inc. 7.7 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in configuration words. External read and write operations are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect configuration bit. Refer to Section 19.0 “Special Features of the CPU” for additional information. 7.8 Using the Data EEPROM The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 7-3. EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification D124. CLRF EEADR ; Start at address 0 BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes Loop ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW AAh ; MOVWF EECON2 ; Write AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA Loop ; Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u EEADR EEPROM Address Register 0000 0000 0000 0000 EEDATA EEPROM Data Register 0000 0000 0000 0000 EECON2 EEPROM Control Register 2 (not a physical register) — — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 IPR2 OSCFIP — — EEIP — LVDIP TMR3IP — 1--1 -11- 1--1 -11- PIR2 OSCFIF — — EEIF — LVDIF TMR3IF — 0--0 -00- 0--0 -00- PIE2 OSCFIE — — EEIE — LVDIE TMR3IE — 0--0 -00- 0--0 -00- Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.© 2007 Microchip Technology Inc. DS39605F-page 71 PIC18F1220/1320 8.0 8 x 8 HARDWARE MULTIPLIER 8.1 Introduction An 8 x 8 hardware multiplier is included in the ALU of the PIC18F1220/1320 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the Status register. Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: • Higher computational throughput • Reduces code size requirements for multiply algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors. Table 8-1 shows a performance comparison between Enhanced devices using the single-cycle hardware multiply and performing the same function without the hardware multiply. TABLE 8-1: PERFORMANCE COMPARISON 8.2 Operation Example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. Example 8-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. EXAMPLE 8-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY ROUTINE Routine Multiply Method Program Memory (Words) Cycles (Max) Time @ 40 MHz @ 10 MHz @ 4 MHz 8 x 8 unsigned Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs Hardware multiply 1 1 100 ns 400 ns 1 μs 8 x 8 signed Without hardware multiply 33 91 9.1 μs 36.4 μs 91 μs Hardware multiply 6 6 600 ns 2.4 μs 6 μs 16 x 16 unsigned Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs 16 x 16 signed Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs Hardware multiply 35 40 4 μs 16 μs 40 μs MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL MOVF ARG1, W MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL BTFSC ARG2, SB ; Test Sign Bit SUBWF PRODH, F ; PRODH = PRODH ; - ARG1 MOVF ARG2, W BTFSC ARG1, SB ; Test Sign Bit SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 PIC18F1220/1320 DS39605F-page 72 © 2007 Microchip Technology Inc. Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0. EQUATION 8-1: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM EXAMPLE 8-3: 16 x 16 UNSIGNED MULTIPLY ROUTINE Example 8-4 shows the sequence to do a 16 x 16 signed multiply. Equation 8-2 shows the algorithm used. The 32-bit result is stored in four registers, RES3:RES0. To account for the sign bits of the arguments, each argument pairs’ Most Significant bit (MSb) is tested and the appropriate subtractions are done. EQUATION 8-2: 16 x 16 SIGNED MULTIPLICATION ALGORITHM EXAMPLE 8-4: 16 x 16 SIGNED MULTIPLY ROUTINE MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L -> ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVFF PRODL, RES0 ; ; MOVF ARG1H, W MULWF ARG2H ; ARG1H * ARG2H -> ; PRODH:PRODL MOVFF PRODH, RES3 ; MOVFF PRODL, RES2 ; ; MOVF ARG1L, W MULWF ARG2H ; ARG1L * ARG2H -> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3,F ; ; MOVF ARG1H, W ; MULWF ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ; RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28 ) + (ARG1L • ARG2H • 28 ) + (ARG1L • ARG2L) MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L -> ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVFF PRODL, RES0 ; ; MOVF ARG1H, W MULWF ARG2H ; ARG1H * ARG2H -> ; PRODH:PRODL MOVFF PRODH, RES3 ; MOVFF PRODL, RES2 ; ; MOVF ARG1L, W MULWF ARG2H ; ARG1L * ARG2H -> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ; ; MOVF ARG1H, W ; MULWF ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1, F ; Add cross MOVF PRODH, W ; products ADDWFC RES2, F ; CLRF WREG ; ADDWFC RES3, F ; ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L, W ; SUBWF RES2 ; MOVF ARG1H, W ; SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + (-1 • ARG1H<7> • ARG2H:ARG2L • 216) © 2007 Microchip Technology Inc. DS39605F-page 73 PIC18F1220/1320 9.0 INTERRUPTS The PIC18F1220/1320 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation. These registers are: • RCON • INTCON • INTCON2 • INTCON3 • PIR1, PIR2 • PIE1, PIE2 • IPR1, IPR2 It is recommended that the Microchip header files supplied with MPLAB® IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. In general, each interrupt source has three bits to control its operation. The functions of these bits are: • Flag bit to indicate that an interrupt event occurred • Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set • Priority bit to select high priority or low priority (INT0 has no priority bit and is always high priority) The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL, if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit. Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.PIC18F1220/1320 DS39605F-page 74 © 2007 Microchip Technology Inc. FIGURE 9-1: INTERRUPT LOGIC TMR0IE GIEH/GIE GIEL/PEIE Wake-up if in Low-Power Mode Interrupt to CPU Vector to Location 0008h INT2IF INT2IE INT2IP INT1IF INT1IE INT1IP TMR0IF TMR0IE TMR0IP INT0IF INT0IE RBIF RBIE RBIP IPEN TMR0IF TMR0IP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP RBIF RBIE RBIP INT0IF INT0IE GIEL\PEIE Interrupt to CPU Vector to Location IPEN IPEN 0018h INT0IF INT0IE INT0IF INT0IE ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts ADIF ADIE ADIP High Priority Interrupt Generation Low Priority Interrupt Generation RCIF RCIE RCIP Additional Peripheral Interrupts GIE\GIEH© 2007 Microchip Technology Inc. DS39605F-page 75 PIC18F1220/1320 9.1 INTCON Registers The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 9-1: INTCON REGISTER Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 76 © 2007 Microchip Technology Inc. REGISTER 9-2: INTCON2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.© 2007 Microchip Technology Inc. DS39605F-page 77 PIC18F1220/1320 REGISTER 9-3: INTCON3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.PIC18F1220/1320 DS39605F-page 78 © 2007 Microchip Technology Inc. 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1, PIR2). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. U-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full bit 3 Unimplemented: Read as ‘0’ bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 79 PIC18F1220/1320 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 OSCFIF — — EEIF — LVDIF TMR3IF — bit 7 bit 0 bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 Unimplemented: Read as ‘0’ bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low-Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 80 © 2007 Microchip Technology Inc. 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 Unimplemented: Read as ‘0’ bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 81 PIC18F1220/1320 REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 OSCFIE — — EEIE — LVDIE TMR3IE — bit 7 bit 0 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 Unimplemented: Read as ‘0’ bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 82 © 2007 Microchip Technology Inc. 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 U-0 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 Unimplemented: Read as ‘0’ bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 83 PIC18F1220/1320 REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 U-0 OSCFIP — — EEIP — LVDIP TMR3IP — bit 7 bit 0 bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 Unimplemented: Read as ‘0’ bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 84 © 2007 Microchip Technology Inc. 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from a low-power mode. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 9-10: RCON REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register 5-3. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register 5-3. bit 2 PD: Power-down Detection Flag bit For details of bit operation, see Register 5-3. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 5-3. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-3. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 85 PIC18F1220/1320 9.6 INTn Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered: either rising if the corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE. Flag bit, INTxF, must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wake-up the processor from low-power modes if bit INTxE was set prior to going into low-power modes. If the Global Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0. It is always a high priority interrupt source. 9.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow (FFh → 00h) in the TMR0 register will set flag bit, TMR0IF. In 16-bit mode, an overflow (FFFFh → 0000h) in the TMR0H:TMR0L registers will set flag bit, TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 11.0 “Timer0 Module” for further details on the Timer0 module. 9.8 PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>). 9.9 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, Status and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 5.3 “Fast Register Stack”), the user may need to save the WREG, Status and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example 9-1 saves and restores the WREG, Status and BSR registers during an Interrupt Service Routine. EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUSPIC18F1220/1320 DS39605F-page 86 © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS39605F-page 87 PIC18F1220/1320 10.0 I/O PORTS Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: • TRIS register (data direction register) • PORT register (reads the levels on the pins of the device) • LAT register (output latch) The Data Latch (LATA) register is useful for readmodify-write operations on the value that the I/O pins are driving. A simplified model of a generic I/O port without the interfaces to other peripherals is shown in Figure 10-1. FIGURE 10-1: GENERIC I/O PORT OPERATION 10.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The sixth pin of PORTA (MCLR/VPP/RA5) is an input only pin. Its operation is controlled by the MCLRE configuration bit in Configuration Register 3H (CONFIG3H<7>). When selected as a port pin (MCLRE = 0), it functions as a digital input only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device’s Master Clear input. In either configuration, RA5 also functions as the programming voltage input during programming. Pins RA6 and RA7 are multiplexed with the main oscillator pins; they are enabled as oscillator or I/O pins by the selection of the main oscillator in Configuration Register 1H (see Section 19.1 “Configuration Bits” for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as ‘0’. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the LVD input. The operation of pins RA3:RA0 as A/D converter inputs is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register 1). The RA4/T0CKI pin is a Schmitt Trigger input and an open-drain output. All other PORTA pins have TTL input levels and full CMOS output drivers. The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. EXAMPLE 10-1: INITIALIZING PORTA Data Bus WR LAT WR TRIS RD Port Data Latch TRIS Latch RD TRIS Input Buffer I/O pin(1) D Q CK D Q CK EN Q D EN RD LAT or Port Note 1: I/O pins have diode protection to VDD and VSS. Note: On a Power-on Reset, RA5 is enabled as a digital input only if Master Clear functionality is disabled. Note: On a Power-on Reset, RA3:RA0 are configured as analog inputs and read as ‘0’. RA4 is always a digital pin. CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches CLRF LATA ; Alternate method ; to clear output ; data latches MOVLW 0x7F ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVLW 0xD0 ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as outputs ; RA<7:4> as inputsPIC18F1220/1320 DS39605F-page 88 © 2007 Microchip Technology Inc. FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 PINS FIGURE 10-3: BLOCK DIAGRAM OF OSC2/CLKO/RA6 PIN FIGURE 10-4: BLOCK DIAGRAM OF RA4/T0CKI PIN FIGURE 10-5: BLOCK DIAGRAM OF OSC1/CLKI/RA7 PIN Data Bus Q D EN P N WR LATA WR TRISA Data Latch TRIS Latch RD TRISA RD PORTA VSS VDD I/O pin(1) Note 1: I/O pins have protection diodes to VDD and VSS. Analog Input Mode To A/D Converter and LVD Modules RD LATA or PORTA D Q CK Q D Q CK Q Schmitt Trigger Input Buffer Data Bus D Q CK Q Q D EN P N WR LATA WR Data Latch TRIS Latch RD RD PORTA VSS VDD I/O pin(1) Note 1: I/O pins have protection diodes to VDD and VSS. or PORTA RD LATA RA6 Enable ECIO or Enable RCIO TRISA D Q CK Q TRISA Schmitt Trigger Input Buffer Data Bus WR TRISA RD PORTA Data Latch TRIS Latch Schmitt Trigger Input Buffer N VSS I/O pin(1) TMR0 Clock Input D Q CK Q D Q CK Q EN Q D EN RD LATA WR LATA or PORTA Note 1: I/O pins have protection diodes to VDD and VSS. RD TRISA Data Bus D Q CK Q Q D EN P N WR LATA WR Data Latch TRIS Latch RD RD PORTA VSS VDD I/O pin(1) Note 1: I/O pins have protection diodes to VDD and VSS. or PORTA RD LATA Enable RA7 TRISA D Q CK Q TRISA RA7 Enable To Oscillator Schmitt Trigger Input Buffer© 2007 Microchip Technology Inc. DS39605F-page 89 PIC18F1220/1320 FIGURE 10-6: MCLR/VPP/RA5 PIN BLOCK DIAGRAM TABLE 10-1: PORTA FUNCTIONS TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA MCLR/VPP/RA5 Data Bus RD PORTA RD LATA Schmitt Trigger MCLRE RD TRISA Q D EN Latch Filter Low-Level MCLR Detect High-Voltage Detect Internal MCLR HV Name Bit# Buffer Function RA0/AN0 bit 0 ST Input/output port pin or analog input. RA1/AN1/LVDIN bit 1 ST Input/output port pin, analog input or Low-Voltage Detect input. RA2/AN2/VREF- bit 2 ST Input/output port pin, analog input or VREF-. RA3/AN3/VREF+ bit 3 ST Input/output port pin, analog input or VREF+. RA4/T0CKI bit 4 ST Input/output port pin or external clock input for Timer0. Output is open-drain type. MCLR/VPP/RA5 bit 5 ST Master Clear input or programming voltage input (if MCLR is enabled); input only port pin or programming voltage input (if MCLR is disabled). OSC2/CLKO/RA6 bit 6 ST OSC2, clock output or I/O pin. OSC1/CLKI/RA7 bit 7 ST OSC1, clock input or I/O pin. Legend: TTL = TTL input, ST = Schmitt Trigger input Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets PORTA RA7(1) RA6(1) RA5(2) RA4 RA3 RA2 RA1 RA0 xx0x 0000 uu0u 0000 LATA LATA7(1) LATA6(1) — LATA Data Output Register xx-x xxxx uu-u uuuu TRISA TRISA7(1) TRISA6(1) — PORTA Data Direction Register 11-1 1111 11-1 1111 ADCON1 — PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: RA5 is an input only if MCLR is disabled.PIC18F1220/1320 DS39605F-page 90 © 2007 Microchip Technology Inc. 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 10-2: INITIALIZING PORTB Pins RB0-RB2 are multiplexed with INT0-INT2; pins RB0, RB1 and RB4 are multiplexed with A/D inputs; pins RB1 and RB4 are multiplexed with EUSART; and pins RB2, RB3, RB6 and RB7 are multiplexed with ECCP. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Four of the PORTB pins (RB7:RB4) have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB (except with the MOVFF instruction). This will end the mismatch condition. b) Clear flag bit, RBIF. A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF, to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. FIGURE 10-7: BLOCK DIAGRAM OF RB0/AN4/INT0 PIN Note: On a Power-on Reset, RB4:RB0 are configured as analog inputs by default and read as ‘0’; RB7:RB5 are configured as digital inputs. CLRF PORTB ; Initialize PORTB by ; clearing output ; data latches CLRF LATB ; Alternate method ; to clear output ; data latches MOVLW 0x70 ; Set RB0, RB1, RB4 as MOVWF ADCON1 ; digital I/O pins MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs Data Latch RBPU(2) P VDD Data Bus WR LATB WR TRISB RD TRISB RD PORTB Weak Pull-up INTx I/O pin(1) Schmitt Trigger Buffer TRIS Latch RD LATB or PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). To A/D Converter Analog Input Mode TTL Input Buffer D Q CK D Q CK EN Q D EN© 2007 Microchip Technology Inc. DS39605F-page 91 PIC18F1220/1320 FIGURE 10-8: BLOCK DIAGRAM OF RB1/AN5/TX/CK/INT1 PIN Data Latch RBPU(2) P VDD D Q CK D Q CK Q D EN Data Bus WR LATB WR TRISB RD TRISB RD PORTB Weak Pull-up RD PORTB RB1 pin(1) TRIS Latch RD LATB or PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). To A/D Converter INT1/CK Input Analog Input Mode 1 0 TX/CK Data EUSART Enable Schmitt Trigger Input Buffer TX/CK TRIS Analog Input Mode TTL Input BufferPIC18F1220/1320 DS39605F-page 92 © 2007 Microchip Technology Inc. FIGURE 10-9: BLOCK DIAGRAM OF RB2/P1B/INT2 PIN Data Latch RBPU(2) P VDD D Q CK D Q CK Q D EN Data Bus WR LATB or WR TRISB RD TRISB RD PORTB Weak Pull-up RD PORTB RB2 pin(1) TTL Input Buffer TRIS Latch RD LATB PORTB P1B Data 1 0 Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). P1B Enable INT2 Input Schmitt Trigger P1B/D Tri-State Auto-Shutdown© 2007 Microchip Technology Inc. DS39605F-page 93 PIC18F1220/1320 FIGURE 10-10: BLOCK DIAGRAM OF RB3/CCP1/P1A PIN Data Bus WR LATB or WR TRISB Data Latch TRIS Latch RD TRISB D Q CK Q Q D EN ECCP1/P1A Data Out 1 0 D Q CK Q P N VDD VSS RD PORTB ECCP1 Input RB3 pin PORTB RD LATB Schmitt Trigger VDD Weak Pull-up P RBPU(2) TTL Input Buffer Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 3: ECCP1 pin output enable active for any PWM mode and Compare mode, where CCP1M<3:0> = 1000 or 1001. 4: ECCP1 pin input enable active for Capture mode only. ECCP1(3) pin Output Enable P1A/C Tri-State Auto-Shutdown ECCP1(4) pin Input EnablePIC18F1220/1320 DS39605F-page 94 © 2007 Microchip Technology Inc. FIGURE 10-11: BLOCK DIAGRAM OF RB4/AN6/RX/DT/KBI0 PIN Data Bus WR LATB or WR TRISB Data Latch TRIS Latch RD TRISB D Q CK Q Q D EN DT Data 1 0 D Q CK Q RD PORTB RB4 pin PORTB RD LATB RBPU(2) P Weak Pull-up Q1 From other Q D EN Set RBIF RB7:RB4 pins RD PORTB Q3 To A/D Converter EUSART Enabled TTL Input Buffer Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). DT TRIS Analog Input Mode RX/DT Input Analog Input Mode Schmitt Trigger VDD© 2007 Microchip Technology Inc. DS39605F-page 95 PIC18F1220/1320 FIGURE 10-12: BLOCK DIAGRAM OF RB5/PGM/KBI1 PIN Data Latch From other RBPU(2) P VDD I/O pin(1) D Q CK D Q CK Q D EN Q D EN Data Bus WR LATB WR TRISB Set RBIF TRIS Latch RD TRISB RD PORTB RB7:RB5 and Weak Pull-up RD PORTB Latch TTL Input Buffer ST Buffer RB7:RB5 in Serial Programming Mode Q3 Q1 RD LATB or PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). RB4 pinsPIC18F1220/1320 DS39605F-page 96 © 2007 Microchip Technology Inc. FIGURE 10-13: BLOCK DIAGRAM OF RB6/PGC/T1OSO/T13CKI/P1C/KBI2 PIN Data Bus WR LATB or WR TRISB Data Latch TRIS Latch RD TRISB D Q CK Q Q D EN P1C Data 1 0 D Q CK Q RD PORTB RB6 pin PORTB RD LATB Schmitt Trigger RBPU(2) P Weak Pull-up Q1 From other Q D EN Set RBIF RB7:RB4 pins RD PORTB Q3 PGC From RB7 pin Timer1 Oscillator T1OSCEN T13CKI Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). TTL Buffer ECCP1 P1C/D Enable P1B/D Tri-State Auto-Shutdown VDD© 2007 Microchip Technology Inc. DS39605F-page 97 PIC18F1220/1320 FIGURE 10-14: BLOCK DIAGRAM OF RB7/PGD/T1OSI/P1D/KBI3 PIN Data Bus WR LATB or WR TRISB Data Latch TRIS Latch RD TRISB D Q CK Q Q D EN P1D Data 1 0 D Q CK Q RD PORTB RB7 pin PORTB RD LATB Schmitt Trigger To RB6 pin RBPU(2) P Weak Pull-up Q1 From other Q D EN Set RBIF RB7:RB4 pins RD PORTB Q3 PGD ECCP1 P1C/D Enable TTL Input Buffer Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). P1B/D Tri-State Auto-Shutdown T1OSCEN VDDPIC18F1220/1320 DS39605F-page 98 © 2007 Microchip Technology Inc. TABLE 10-3: PORTB FUNCTIONS TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit# Buffer Function RB0/AN4/INT0 bit 0 TTL(1)/ST(2) Input/output port pin, analog input or external interrupt input 0. RB1/AN5/TX/CK/INT1 bit 1 TTL(1)/ST(2) Input/output port pin, analog input, Enhanced USART Asynchronous Transmit, Addressable USART Synchronous Clock or external interrupt input 1. RB2/P1B/INT2 bit 2 TTL(1)/ST(2) Input/output port pin or external interrupt input 2. Internal software programmable weak pull-up. RB3/CCP1/P1A bit 3 TTL(1)/ST(3) Input/output port pin or Capture1 input/Compare1 output/ PWM output. Internal software programmable weak pull-up. RB4/AN6/RX/DT/KBI0 bit 4 TTL(1)/ST(4) Input/output port pin (with interrupt-on-change), analog input, Enhanced USART Asynchronous Receive or Addressable USART Synchronous Data. RB5/PGM/KBI1 bit 5 TTL(1)/ST(5) Input/output port pin (with interrupt-on-change). Internal software programmable weak pull-up. Low-Voltage ICSP enable pin. RB6/PGC/T1OSO/T13CKI/ P1C/KBI2 bit 6 TTL(1)/ST(5,6) Input/output port pin (with interrupt-on-change), Timer1/ Timer3 clock input or Timer1oscillator output. Internal software programmable weak pull-up. Serial programming clock. RB7/PGD/T1OSI/P1D/KBI3 bit 7 TTL(1)/ST(5) Input/output port pin (with interrupt-on-change) or Timer1 oscillator input. Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a TTL input when configured as a port input pin. 2: This buffer is a Schmitt Trigger input when configured as the external interrupt. 3: This buffer is a Schmitt Trigger input when configured as the CCP1 input. 4: This buffer is a Schmitt Trigger input when used as EUSART receive input. 5: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 6: This buffer is a TTL input when used as the T13CKI input. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxq qqqq uuuu uuuu LATB LATB Data Output Register xxxx xxxx uuuu uuuu TRISB PORTB Data Direction Register 1111 1111 1111 1111 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 1111 -1-1 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 11-0 0-00 ADCON1 — PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000 Legend: x = unknown, u = unchanged, q = value depends on condition. Shaded cells are not used by PORTB.© 2007 Microchip Technology Inc. DS39605F-page 99 PIC18F1220/1320 11.0 TIMER0 MODULE The Timer0 module has the following features: • Software selectable as an 8-bit or 16-bit timer/ counter • Readable and writable • Dedicated 8-bit software programmable prescaler • Clock source selectable to be external or internal • Interrupt-on-overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode • Edge select for external clock Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11-1) is a readable and writable register that controls all the aspects of Timer0, including the prescale selection. REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 100 © 2007 Microchip Technology Inc. FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. RA4/T0CKI T0SE 0 1 1 0 T0CS FOSC/4 Programmable Prescaler Sync with Internal Clocks TMR0 (2 TCY Delay) Data Bus 8 PSA T0PS2, T0PS1, T0PS0 Set Interrupt Flag bit TMR0IF on Overflow 3 pin Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. T0SE 0 1 1 0 T0CS FOSC/4 Programmable Prescaler Sync with Internal Clocks TMR0L (2 TCY Delay) Data Bus<7:0> 8 PSA T0PS2, T0PS1, T0PS0 Set Interrupt Flag bit TMR0IF on Overflow 3 TMR0 TMR0H High Byte 8 8 8 Read TMR0L Write TMR0L RA4/T0CKI pin© 2007 Microchip Technology Inc. DS39605F-page 101 PIC18F1220/1320 11.1 Timer0 Operation Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the T0SE bit selects the rising edge. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 11.2 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable. The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, x, ..., etc.) will clear the prescaler count. 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). 11.3 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF bit. The interrupt can be masked by clearing the TMR0IE bit. The TMR0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from Low-Power Sleep mode, since the timer requires clock cycles even when T0CS is set. 11.4 16-Bit Mode Timer Reads and Writes TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of Timer0 (refer to Figure 11-2). The high byte of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0, without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte. A write to the high byte of Timer0 must also take place through the TMR0H Buffer register. Timer0 high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0 Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TMR0L Timer0 Module Low Byte Register xxxx xxxx uuuu uuuu TMR0H Timer0 Module High Byte Register 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111 TRISA RA7(1) RA6(1) — PORTA Data Direction Register 11-1 1111 11-1 1111 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins, depending on the oscillator mode selected in Configuration Word 1H.PIC18F1220/1320 DS39605F-page 102 © 2007 Microchip Technology Inc. NOTES:© 2007 Microchip Technology Inc. DS39605F-page 103 PIC18F1220/1320 12.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers: TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module special event trigger • Status of system clock operation Figure 12-1 is a simplified block diagram of the Timer1 module. Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). The Timer1 oscillator can be used as a secondary clock source in power managed modes. When the T1RUN bit is set, the Timer1 oscillator is providing the system clock. If the Fail-Safe Clock Monitor is enabled and the Timer1 oscillator fails while providing the system clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications, with only a minimal addition of external components and code overhead. REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = System clock is derived from Timer1 oscillator 0 = System clock is derived from another source bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RB6/PGC/T1OSO/T13CKI/P1C/KBI2 (on the rising edge) 0 = Internal clock (Fosc/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 104 © 2007 Microchip Technology Inc. 12.1 Timer1 Operation Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input, or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/T1OSO/ T13CKI/P1C/KBI2 pins become inputs. That is, the TRISB7:TRISB6 values are ignored and the pins read as ‘0’. Timer1 also has an internal “Reset input”. This Reset can be generated by the CCP module (see Section 15.4.4 “Special Event Trigger”). FIGURE 12-1: TIMER1 BLOCK DIAGRAM FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE TMR1H TMR1L T1SYNC TMR1CS T1CKPS1:T1CKPS0 Peripheral Clocks FOSC/4 Internal Clock TMR1ON On/Off Prescaler 1, 2, 4, 8 Synchronize det 1 0 0 1 Synchronized Clock Input 2 TMR1IF Overflow TMR1 CLR CCP Special Event Trigger T1OSCEN Enable Oscillator(1) T1OSC Interrupt Flag bit Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. T1OSI T13CKI/T1OSO Timer 1 TMR1L T1OSC T1SYNC TMR1CS T1CKPS1:T1CKPS0 Peripheral Clocks T1OSCEN Enable Oscillator(1) TMR1IF Overflow Interrupt FOSC/4 Internal Clock TMR1ON on/off Prescaler 1, 2, 4, 8 Synchronize det 1 0 0 1 Synchronized Clock Input 2 T13CKI/T1OSO T1OSI TMR1 Flag bit Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. High Byte Data Bus<7:0> 8 TMR1H 8 8 8 Read TMR1L Write TMR1L CLR CCP Special Event Trigger© 2007 Microchip Technology Inc. DS39605F-page 105 PIC18F1220/1320 12.2 Timer1 Oscillator A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated for 32 kHz crystals. It will continue to run during all power managed modes. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. FIGURE 12-3: EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Note: The Timer1 oscillator shares the T1OSI and T1OSO pins with the PGD and PGC pins used for programming and debugging. When using the Timer1 oscillator, In-Circuit Serial Programming (ICSP) may not function correctly (high voltage or low voltage), or the In-Circuit Debugger (ICD) may not communicate with the controller. As a result of using either ICSP or ICD, the Timer1 crystal may be damaged. If ICSP or ICD operations are required, the crystal should be disconnected from the circuit (disconnect either lead), or installed after programming. The oscillator loading capacitors may remain in-circuit during ICSP or ICD operation. Osc Type Freq C1 C2 LP 32 kHz 22 pF(1) 22 pF(1) Note 1: Microchip suggests this value as a starting point in validating the oscillator circuit. Oscillator operation should then be tested to ensure expected performance under all expected conditions (VDD and temperature). 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only. Note: See the Notes with Table 12-1 for additional information about capacitor selection. C1 C2 XTAL PIC18FXXXX PGD/T1OSI PGC/T1OSO 32.768 kHz 22 pF 22 pF PGD PGC PIC18F1220/1320 DS39605F-page 106 © 2007 Microchip Technology Inc. 12.3 Timer1 Oscillator Layout Considerations The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the oscillator (such as the CCP1 pin in output compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 12-4, may be helpful when used on a single sided PCB, or in addition to a ground plane. FIGURE 12-4: OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING 12.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). 12.5 Resetting Timer1 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion, if the A/D module is enabled (see Section 15.4.4 “Special Event Trigger” for more information). Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer1. 12.6 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid, due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. RA1 RA4 RB0 MCLR VSS RA2 RA3 Note: Not drawn to scale. RB2 OSC1 RB5 OSC2 VDD RB7 RB6 C2 X1 C3 C4 X2 C5 C1 Note: The special event triggers from the CCP1 module will not set interrupt flag bit, TMR1IF (PIR1<0>). © 2007 Microchip Technology Inc. DS39605F-page 107 PIC18F1220/1320 12.7 Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the one described in Section 12.2 “Timer1 Oscillator”, above), gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow, triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it; the simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 0x80 ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’ ; Configure for external clock, MOVWF T1OSC ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done MOVLW .01 ; Reset hours to 1 MOVWF hours RETURN ; DonePIC18F1220/1320 DS39605F-page 108 © 2007 Microchip Technology Inc. TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.© 2007 Microchip Technology Inc. DS39605F-page 109 PIC18F1220/1320 13.0 TIMER2 MODULE The Timer2 module timer has the following features: • 8-bit timer (TMR2 register) • 8-bit period register (PR2) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2 Timer2 has a control register shown in Register 13-1. TMR2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. Figure 13-1 is a simplified block diagram of the Timer2 module. Register 13-1 shows the Timer2 Control register. The prescaler and postscaler selection of Timer2 are controlled by this register. 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: • A write to the TMR2 register • A write to the T2CON register • Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 110 © 2007 Microchip Technology Inc. 13.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. 13.3 Output of TMR2 The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module, which optionally uses it to generate the shift clock. FIGURE 13-1: TIMER2 BLOCK DIAGRAM TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Comparator TMR2 Sets Flag TMR2 Output(1) Reset Postscaler Prescaler PR2 2 FOSC/4 1:1 to 1:16 1:1, 1:4, 1:16 EQ 4 bit TMR2IF TOUTPS3:TOUTPS0 T2CKPS1:T2CKPS0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 TMR2 Timer2 Module Register 0000 0000 0000 0000 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.© 2007 Microchip Technology Inc. DS39605F-page 111 PIC18F1220/1320 14.0 TIMER3 MODULE The Timer3 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers; TMR3H and TMR3L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module trigger Figure 14-1 is a simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. Register 12-1 shows the Timer1 Control register. This register controls the operating mode of the Timer1 module, as well as contains the Timer1 Oscillator Enable bit (T1OSCEN), which can be a clock source for Timer3. REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6 Unimplemented: Read as ‘0’ bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T3CCP1: Timer3 and Timer1 to CCP1 Enable bits 1 = Timer3 is the clock source for compare/capture CCP module 0 = Timer1 is the clock source for compare/capture CCP module bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 112 © 2007 Microchip Technology Inc. 14.1 Timer3 Operation Timer3 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/PGC/ T1OSO/T13CKI/P1C/KBI2 pins become inputs. That is, the TRISB7:TRISB6 value is ignored and the pins are read as ‘0’. Timer3 also has an internal “Reset input”. This Reset can be generated by the CCP module (see Section 15.4.4 “Special Event Trigger”). FIGURE 14-1: TIMER3 BLOCK DIAGRAM FIGURE 14-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE TMR3H TMR3L T1OSC T3SYNC TMR3CS T3CKPS1:T3CKPS0 Peripheral Clocks T1OSCEN Enable Oscillator(1) TMR3IF Overflow Interrupt FOSC/4 Internal Clock TMR3ON On/Off Prescaler 1, 2, 4, 8 Synchronize det 1 0 0 1 Synchronized Clock Input 2 T1OSO/ T1OSI Flag bit Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. T13CKI CLR CCP Special Event Trigger T3CCPx Timer3 TMR3L T1OSC T3SYNC TMR3CS T3CKPS1:T3CKPS0 Peripheral T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock TMR3ON On/Off Prescaler 1, 2, 4, 8 Synchronize det 1 0 0 1 Synchronized Clock Input 2 T1OSO/ T1OSI TMR3 T13CKI CLR CCP Special Event Trigger T3CCPx To Timer1 Clock Input Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. High Byte Data Bus<7:0> 8 TMR3H 8 8 8 Read TMR3L Write TMR3L Set TMR3IF Flag bit on Overflow Clocks© 2007 Microchip Technology Inc. DS39605F-page 113 PIC18F1220/1320 14.2 Timer1 Oscillator The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a lowpower oscillator rated for 32 kHz crystals. See Section 12.2 “Timer1 Oscillator” for further details. 14.3 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR3 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled/disabled by setting/clearing TMR3 Interrupt Enable bit, TMR3IE (PIE2<1>). 14.4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3. See Section 15.4.4 “Special Event Trigger” for more information. Timer3 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer3 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer3 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer3. TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Note: The special event triggers from the CCP module will not set interrupt flag bit, TMR3IF (PIR1<0>). Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR2 OSCFIF — — EEIF — LVDIF TMR3IF — 0--0 -00- 0--0 -00- PIE2 OSCFIE — — EEIE — LVDIE TMR3IE — 0--0 -00- 0--0 -00- IPR2 OSCFIP — — EEIP — LVDIP TMR3IP — 1--1 -11- 1--1 -11- TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 u-uu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.PIC18F1220/1320 DS39605F-page 114 © 2007 Microchip Technology Inc. NOTES:© 2007 Microchip Technology Inc. DS39605F-page 115 PIC18F1220/1320 15.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE The Enhanced CCP module is implemented as a standard CCP module with Enhanced PWM capabilities. These capabilities allow for 2 or 4 output channels, user-selectable polarity, dead-band control and automatic shutdown and restart and are discussed in detail in Section 15.5 “Enhanced PWM Mode”. The control register for CCP1 is shown in Register 15-1. In addition to the expanded functions of the CCP1CON register, the ECCP module has two additional registers associated with Enhanced PWM operation and auto-shutdown features: • PWM1CON • ECCPAS REGISTER 15-1: CCP1CON REGISTER FOR ENHANCED CCP OPERATION R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7-6 P1M1:P1M0: PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B1:DC1B0: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M3:CCP1M0: ECCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (ECCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (ECCP1IF bit is set) 1001 = Compare mode, clear output on match (ECCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (ECCP1IF bit is set, ECCP1 pin returns to port pin operation) 1011 = Compare mode, trigger special event (ECCP1IF bit is set; ECCP resets TMR1 or TMR3 and starts an A/D conversion if the A/D module is enabled) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 116 © 2007 Microchip Technology Inc. 15.1 ECCP Outputs The Enhanced CCP module may have up to four outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTB. The pin assignments are summarized in Table 15-1. To configure I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1Mn and CCP1Mn bits (CCP1CON<7:6> and <3:0>, respectively). The appropriate TRISB direction bits for the port pins must also be set as outputs. TABLE 15-1: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES 15.2 CCP Module Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. TABLE 15-2: CCP MODE – TIMER RESOURCE 15.3 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on pin RB3/CCP1/P1A. An event is defined as one of the following: • every falling edge • every rising edge • every 4th rising edge • every 16th rising edge The event is selected by control bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF (PIR1<2>), is set; it must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value. 15.3.1 CCP PIN CONFIGURATION In Capture mode, the RB3/CCP1/P1A pin should be configured as an input by setting the TRISB<3> bit. 15.3.2 TIMER1/TIMER3 MODE SELECTION The timers that are to be used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with the CCP module is selected in the T3CON register. 15.3.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit, CCP1IE (PIE1<2>), clear while changing capture modes to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode. ECCP Mode CCP1CON Configuration RB3 RB2 RB6 RB7 Compatible CCP 00xx 11xx CCP1 RB2/INT2 RB6/PGC/T1OSO/T13CKI/KBI2 RB7/PGD/T1OSI/KBI3 Dual PWM 10xx 11xx P1A P1B RB6/PGC/T1OSO/T13CKI/KBI2 RB7/PGD/T1OSI/KBI3 Quad PWM x1xx 11xx P1A P1B P1C P1D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode. Note 1: TRIS register values must be configured appropriately. CCP Mode Timer Resource Capture Compare PWM Timer1 or Timer3 Timer1 or Timer3 Timer2 Note: If the RB3/CCP1/P1A is configured as an output, a write to the port can cause a capture condition. © 2007 Microchip Technology Inc. DS39605F-page 117 PIC18F1220/1320 15.3.4 CCP PRESCALER There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 15-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. EXAMPLE 15-1: CHANGING BETWEEN CAPTURE PRESCALERS FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM 15.4 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 register pair value, or the TMR3 register pair value. When a match occurs, the RB3/CCP1/P1A pin: • Is driven high • Is driven low • Toggles output (high-to-low or low-to-high) • Remains unchanged (interrupt only) The action on the pin is based on the value of control bits, CCP1M3:CCP1M0. At the same time, interrupt flag bit, CCP1IF, is set. 15.4.1 CCP PIN CONFIGURATION The user must configure the RB3/CCP1/P1A pin as an output by clearing the TRISB<3> bit. 15.4.2 TIMER1/TIMER3 MODE SELECTION Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 15.4.3 SOFTWARE INTERRUPT MODE When generate software interrupt is chosen, the RB3/ CCP1/P1A pin is not affected. CCP1IF is set and an interrupt is generated (if enabled). 15.4.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special event trigger also sets the GO/DONE bit (ADCON0<1>). This starts a conversion of the currently selected A/D channel if the A/D is on. CLRF CCP1CON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and CCP ON MOVWF CCP1CON ; Load CCP1CON with ; this value CCPR1H CCPR1L TMR1H TMR1L Set Flag bit CCP1IF TMR3 Enable Q’s CCP1CON<3:0> CCP1 pin Prescaler ÷ 1, 4, 16 and Edge Detect TMR3H TMR3L TMR1 Enable T3CCP1 T3CCP1 Note: Clearing the CCP1CON register will force the RB3/CCP1/P1A compare output latch to the default low level. This is not the PORTB I/O data latch.PIC18F1220/1320 DS39605F-page 118 © 2007 Microchip Technology Inc. FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 CCPR1H CCPR1L TMR1H TMR1L Comparator Q S R Output Logic Special Event Trigger Set Flag bit CCP1IF RB3/CCP1/P1A pin Match TRISB<3> CCP1CON<3:0> Mode Select Output Enable Special Event Trigger will: Reset Timer1 or Timer3, but does not set Timer1 or Timer3 interrupt flag bit and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion. TMR3H TMR3L T3CCP1 0 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 TRISB PORTB Data Direction Register 1111 1111 1111 1111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 u-uu uuuu ADCON0 VCFG1 VCFG0 — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.© 2007 Microchip Technology Inc. DS39605F-page 119 PIC18F1220/1320 15.5 Enhanced PWM Mode The Enhanced PWM Mode provides additional PWM output options for a broader range of control applications. The module is an upwardly compatible version of the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active-high or active-low). The module’s output mode and polarity are configured by setting the P1M1:P1M0 and CCP1M3CCP1M0 bits of the CCP1CON register (CCP1CON<7:6> and CCP1CON<3:0>, respectively). Figure 15-3 shows a simplified block diagram of PWM operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the period boundary when Timer2 resets) in order to prevent glitches on any of the outputs. The exception is the PWM Delay register, ECCP1DEL, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). Because of the buffering, the module waits until the assigned timer resets instead of starting immediately. This means that Enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle (4 TOSC). As before, the user must manually configure the appropriate TRIS bits for output. 15.5.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the equation: EQUATION 15-1: PWM PERIOD PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set (if PWM duty cycle = 0%, the CCP1 pin will not be set) • The PWM duty cycle is copied from CCPR1L into CCPR1H 15.5.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the equation: EQUATION 15-2: PWM DUTY CYCLE CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: EQUATION 15-3: PWM RESOLUTION 15.5.3 PWM OUTPUT CONFIGURATIONS The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations: • Single Output • Half-Bridge Output • Full-Bridge Output, Forward mode • Full-Bridge Output, Reverse mode The Single Output mode is the Standard PWM mode discussed in Section 15.5 “Enhanced PWM Mode”. The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 15-4. TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz Note: The Timer2 postscaler (see Section 13.0 “Timer2 Module”) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM Period = [(PR2) + 1] • 4 • TOSC • (TMR2 Prescale Value) Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • TOSC • (TMR2 Prescale Value) ( ) PWM Resolution (max) = FOSC FPWM log log(2) bits PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58PIC18F1220/1320 DS39605F-page 120 © 2007 Microchip Technology Inc. FIGURE 15-3: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE FIGURE 15-4: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) CCPR1L CCPR1H (Slave) Comparator TMR2 Comparator PR2 (Note 1) R Q S Duty Cycle Registers CCP1CON<5:4> Clear Timer, set CCP1 pin and latch D.C. Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. TRISB<3> RB3/CCP1/P1A TRISB<2> RB2/P1B/INT2 TRISB<6> RB6/PGC/T1OSO/T13CKI/ TRISB<7> RB7/PGD/T1OSI/P1D/KBI3 Output Controller P1M1<1:0> 2 CCP1M<3:0> 4 CCP1DEL CCP1/P1A P1B P1C P1D P1C/KBI2 0 Period 00 10 01 11 SIGNAL PR2+1 CCP1CON<7:6> P1A Modulated P1A Modulated P1B Modulated P1A Active P1B Inactive P1C Inactive P1D Modulated P1A Inactive P1B Modulated P1C Active P1D Inactive Duty Cycle (Single Output) (Half-Bridge) (Full-Bridge, Forward) (Full-Bridge, Reverse) Delay(1) Delay(1)© 2007 Microchip Technology Inc. DS39605F-page 121 PIC18F1220/1320 FIGURE 15-5: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 Period 00 10 01 11 SIGNAL PR2+1 CCP1CON<7:6> P1A Modulated P1A Modulated P1B Modulated P1A Active P1B Inactive P1C Inactive P1D Modulated P1A Inactive P1B Modulated P1C Active P1D Inactive Duty Cycle (Single Output) (Half-Bridge) (Full-Bridge, Forward) (Full-Bridge, Reverse) Delay(1) Delay(1) Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section 15.5.6 “Programmable Dead-Band Delay”).PIC18F1220/1320 DS39605F-page 122 © 2007 Microchip Technology Inc. 15.5.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the RB3/CCP1/P1A pin, while the complementary PWM output signal is output on the RB2/P1B/INT2 pin (Figure 15-6). This mode can be used for half-bridge applications, as shown in Figure 15-7, or for full-bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge Output mode, the programmable deadband delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits, PDC6:PDC0 (PWM1CON<6:0>), sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 15.5.6 “Programmable Dead-Band Delay” for more details of the dead-band delay operations. The TRISB<3> and TRISB<2> bits must be cleared to configure P1A and P1B as outputs. FIGURE 15-6: HALF-BRIDGE PWM OUTPUT (ACTIVE-HIGH) FIGURE 15-7: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Period Duty Cycle td td (1) P1A P1B td = Dead-Band Delay Period (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. PIC18F1220/1320 P1A P1B FET Driver FET Driver Load + V - + V - FET Driver FET Driver V+ V- Load FET Driver FET Driver PIC18F1220/1320 P1A P1B Standard Half-Bridge Circuit (“Push-Pull”) Half-Bridge Output Driving a Full-Bridge Circuit© 2007 Microchip Technology Inc. DS39605F-page 123 PIC18F1220/1320 15.5.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin RB3/CCP1/P1A is continuously active and pin RB7/PGD/T1OSI/P1D/KBI3 is modulated. In the Reverse mode, pin RB6/PGC/ T1OSO/T13CKI/P1C/KBI2 is continuously active and pin RB2/P1B/INT2 is modulated. These are illustrated in Figure 15-8. The TRISB<3:2> and TRISB<7:6> bits must be cleared to make the P1A, P1B, P1C and P1D pins output. FIGURE 15-8: FULL-BRIDGE PWM OUTPUT (ACTIVE-HIGH) Period Duty Cycle P1A P1B P1C P1D Forward Mode (1) Period Duty Cycle P1A P1C P1D P1B Reverse Mode (1) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register.PIC18F1220/1320 DS39605F-page 124 © 2007 Microchip Technology Inc. FIGURE 15-9: EXAMPLE OF FULL-BRIDGE APPLICATION 15.5.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows the user to control the Forward/Reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle. Just before the end of the current PWM period, the modulated outputs (P1B and P1D) are placed in their inactive state, while the unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. This occurs in a time interval of (4 TOSC * (Timer2 Prescale Value) before the next PWM period begins. The Timer2 prescaler will be either 1,4 or 16, depending on the value of the T2CKPS bit (T2CON<1:0>). During the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (P1B and P1D) remain inactive. This relationship is shown in Figure 15-10. Note that in the Full-Bridge Output mode, the ECCP module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. Figure 15-11 shows an example where the PWM direction changes from forward to reverse, at a near 100% duty cycle. At time t1, the output P1A and P1D become inactive, while output P1C becomes active. In this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices QC and QD (see Figure 15-9) for the duration of ‘t’. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, one of the following requirements must be met: 1. Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. PIC18F1220/1320 P1A P1C FET Driver FET Driver V+ V- Load FET Driver FET Driver P1B P1D QA QB QD QC© 2007 Microchip Technology Inc. DS39605F-page 125 PIC18F1220/1320 FIGURE 15-10: PWM DIRECTION CHANGE (ACTIVE-HIGH) FIGURE 15-11: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE (ACTIVE-HIGH) DC PWM Period(1) SIGNAL Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C toggle one Timer2 count before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. PWM Period One Timer2 Count(2) P1A P1B P1C P1D DC Forward Period Reverse Period P1A tON tOFF t = tOFF – tON P1B P1C P1D External Switch D Potential Shoot-Through Current Note 1: tON is the turn-on delay of power switch QC and its driver. 2: tOFF is the turn-off delay of power switch QD and its driver. External Switch C t1 DC DCPIC18F1220/1320 DS39605F-page 126 © 2007 Microchip Technology Inc. 15.5.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shootthrough current) may flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In the Half-Bridge Output mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 15-6 for an illustration. The lower seven bits of the PWM1CON register (Register 15-2) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). 15.5.7 ENHANCED PWM AUTO-SHUTDOWN When the ECCP is programmed for any of the Enhanced PWM modes, the active output pins may be configured for auto-shutdown. Auto-shutdown immediately places the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs. A shutdown event can be caused by the INT0, INT1 or INT2 pins (or any combination of these three sources). The auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. The autoshutdown sources to be used are selected using the ECCPAS2:ECCPAS0 bits (bits <6:4> of the ECCPAS register). When a shutdown occurs, the output pins are asynchronously placed in their shutdown states, specified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits (ECCPAS<3:0>). Each pin pair (P1A/P1C and P1B/P1D) may be set to drive high, drive low or be tristated (not driving). The ECCPASE bit (ECCPAS<7>) is also set to hold the Enhanced PWM outputs in their shutdown states. The ECCPASE bit is set by hardware when a shutdown event occurs. If automatic restarts are not enabled, the ECCPASE bit is cleared by firmware when the cause of the shutdown clears. If automatic restarts are enabled, the ECCPASE bit is automatically cleared when the cause of the auto-shutdown has cleared. If the ECCPASE bit is set when a PWM period begins, the PWM outputs remain in their shutdown state for that entire PWM period. When the ECCPASE bit is cleared, the PWM outputs will return to normal operation at the beginning of the next PWM period. REGISTER 15-2: PWM1CON: PWM CONFIGURATION REGISTER Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 127 PIC18F1220/1320 REGISTER 15-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM/AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 0 = ECCP outputs are operating 1 = A shutdown event has occurred; ECCP outputs are in shutdown state bit 6 ECCPAS2: ECCP Auto-Shutdown bit 2 0 = INT0 pin has no effect 1 = INT0 pin low causes shutdown bit 5 ECCPAS1: ECCP Auto-Shutdown bit 1 0 = INT2 pin has no effect 1 = INT2 pin low causes shutdown bit 4 ECCPAS0: ECCP Auto-Shutdown bit 0 0 = INT1 pin has no effect 1 = INT1 pin low causes shutdown bit 3-2 PSSACn: Pins A and C Shutdown State Control bits 00 = Drive Pins A and C to ‘0’ 01 = Drive Pins A and C to ‘1’ 1x = Pins A and C tri-state bit 1-0 PSSBDn: Pins B and D Shutdown State Control bits 00 = Drive Pins B and D to ‘0’ 01 = Drive Pins B and D to ‘1’ 1x = Pins B and D tri-state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 128 © 2007 Microchip Technology Inc. 15.5.7.1 Auto-Shutdown and Automatic Restart The auto-shutdown feature can be configured to allow automatic restarts of the module, following a shutdown event. This is enabled by setting the PRSEN bit of the PWM1CON register (PWM1CON<7>). In Shutdown mode with PRSEN = 1 (Figure 15-12), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCPASE bit is automatically cleared. If PRSEN = 0 (Figure 15-13), once a shutdown condition occurs, the ECCPASE bit will remain set until it is cleared by firmware. Once ECCPASE is cleared, the Enhanced PWM will resume at the beginning of the next PWM period. Independent of the PRSEN bit setting, the ECCPASE bit cannot be cleared as long as the cause of the shutdown persists. The Auto-Shutdown mode can be forced by writing a ‘1’ to the ECCPASE bit. 15.5.8 START-UP CONSIDERATIONS When the ECCP module is used in the PWM mode, the application hardware must use the proper external pullup and/or pull-down resistors on the PWM output pins. When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the off state, until the microcontroller drives the I/O pins with the proper signal levels, or activates the PWM output(s). The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended, since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP module may cause damage to the application circuit. The ECCP module must be enabled in the proper output mode and complete a full PWM cycle, before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. FIGURE 15-12: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED) FIGURE 15-13: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED) Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. Shutdown PWM ECCPASE bit Activity Event PWM Period PWM Period PWM Period Duty Cycle Dead Time Duty Cycle Duty Cycle Dead Time Dead Time Shutdown PWM ECCPASE bit Activity Event PWM Period PWM Period PWM Period ECCPASE Cleared by Firmware Duty Cycle Dead Time Duty Cycle Duty Cycle Dead Time Dead Time© 2007 Microchip Technology Inc. DS39605F-page 129 PIC18F1220/1320 15.5.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. Configure the PWM pins P1A and P1B (and P1C and P1D, if used) as inputs by setting the corresponding TRISB bits. 2. Set the PWM period by loading the PR2 register. 3. Configure the ECCP module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: • Select one of the available output configurations and direction with the P1M1:P1M0 bits. • Select the polarities of the PWM output signals with the CCP1M3:CCP1M0 bits. 4. Set the PWM duty cycle by loading the CCPR1L register and CCP1CON<5:4> bits. 5. For Half-Bridge Output mode, set the deadband delay by loading PWM1CON<6:0> with the appropriate value. 6. If auto-shutdown operation is required, load the ECCPAS register: • Select the auto-shutdown sources using the ECCPAS<2:0> bits. • Select the shutdown states of the PWM output pins using PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits. • Set the ECCPASE bit (ECCPAS<7>). 7. If auto-restart operation is required, set the PRSEN bit (PWM1CON<7>). 8. Configure and start TMR2: • Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). • Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). • Enable Timer2 by setting the TMR2ON bit (T2CON<2>). 9. Enable PWM outputs after a new PWM cycle has started: • Wait until TMR2 overflows (TMR2IF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRISB bits. • Clear the ECCPASE bit (ECCPAS<7>). 15.5.10 OPERATION IN LOW-POWER MODES In the Low-Power Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the ECCP pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If TwoSpeed Start-ups are enabled, the initial start-up frequency may not be stable if the INTOSC is being used. In PRI_IDLE mode, the primary clock will continue to clock the ECCP module without change. In all other low-power modes, the selected low-power mode clock will clock Timer2. Other low-power mode clocks will most likely be different than the primary clock frequency. 15.5.10.1 Operation with Fail-Safe Clock Monitor If the Fail-Safe Clock Monitor is enabled (CONFIG1H<6> is programmed), a clock failure will force the device into the Low-Power RC_RUN mode and the OSCFIF bit (PIR2<7>) will be set. The ECCP will then be clocked from the INTRC clock source, which may have a different clock frequency than the primary clock. By loading the IRCF2:IRCF0 bits on Resets, the user can enable the INTOSC at a high clock speed in the event of a clock failure. See the previous section for additional details. 15.5.11 EFFECTS OF A RESET Both power-on and subsequent Resets will force all ports to input mode and the CCP registers to their Reset states. This forces the Enhanced CCP module to reset to a state compatible with the standard CCP module.PIC18F1220/1320 DS39605F-page 130 © 2007 Microchip Technology Inc. TABLE 15-5: REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u RCON IPEN — — RI TO PD POR BOR 0--1 11qq 0--q qquu PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 TMR2 Timer2 Module Register 0000 0000 0000 0000 PR2 Timer2 Module Period Register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 TRISB PORTB Data Direction Register 1111 1111 1111 1111 CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000 PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 uuuu uuuu OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 qq00 0000 qq00 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module in Enhanced PWM mode.© 2007 Microchip Technology Inc. DS39605F-page 131 PIC18F1220/1320 16.0 ENHANCED ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Addressable Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The Enhanced Addressable USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These features make it ideally suited for use in Local Interconnect Network (LIN) bus systems. The EUSART can be configured in the following modes: • Asynchronous (full duplex) with: - Auto-wake-up on character reception - Auto-baud calibration - 12-bit Break character transmission • Synchronous – Master (half duplex) with selectable clock polarity • Synchronous – Slave (half duplex) with selectable clock polarity The RB1/AN5/TX/CK/INT1 and RB4/AN6/RX/DT/KBI0 pins must be configured as follows for use with the Universal Synchronous Asynchronous Receiver Transmitter: • SPEN (RCSTA<7>) bit must be set ( = 1), • PCFG6:PCFG5 (ADCON1<5:6>) must be set ( = 1), • TRISB<4> bit must be set ( = 1) and • TRISB<1> bit must be set ( = 1). The operation of the Enhanced USART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCTL) These are detailed in on the following pages in Register 16-1, Register 16-2 and Register 16-3, respectively. 16.1 Asynchronous Operation in Power Managed Modes The EUSART may operate in Asynchronous mode while the peripheral clocks are being provided by the internal oscillator block. This makes it possible to remove the crystal or resonator that is commonly connected as the primary clock on the OSC1 and OSC2 pins. The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz (see Table 22-6). However, this frequency may drift as VDD or temperature changes and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output back to 8 MHz. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source (see Section 3.6 “INTOSC Frequency Drift” for more information). The other method adjusts the value in the Baud Rate Generator (BRG). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. Note: The EUSART control will automatically reconfigure the pin from input to output as needed.PIC18F1220/1320 DS39605F-page 132 © 2007 Microchip Technology Inc. REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR Idle 0 = TSR busy bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 133 PIC18F1220/1320 REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, generates RCIF interrupt and loads RCREG when RX9D is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 134 © 2007 Microchip Technology Inc. REGISTER 16-3: BAUDCTL: BAUD RATE CONTROL REGISTER U-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receiver is Idle 0 = Receiver is busy bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character – requires reception of a Sync byte (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 135 PIC18F1220/1320 16.2 EUSART Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator, that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCTL<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 also control the baud rate. In Synchronous mode, bit BRGH is ignored. Table 16-1 shows the formula for computation of the baud rate for different EUSART modes which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table 16-1. From this, the error in baud rate can be determined. An example calculation is shown in Example 16-1. Typical baud rates and error values for the various asynchronous modes are shown in Table 16-2. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. 16.2.1 POWER MANAGED MODE OPERATION The system clock is used to generate the desired baud rate; however, when a power managed mode is entered, the clock source may be operating at a different frequency than in PRI_RUN mode. In Sleep mode, no clocks are present and in PRI_IDLE mode, the primary clock source continues to provide clocks to the Baud Rate Generator; however, in other power managed modes, the clock frequency will probably change. This may require the value in SPBRG to be adjusted. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit and make sure that the receive operation is Idle before changing the system clock. 16.2.2 SAMPLING The data on the RB4/AN6/RX/DT/KBI0 pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. TABLE 16-1: BAUD RATE FORMULAS EXAMPLE 16-1: CALCULATING BAUD RATE ERROR Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 000 8-bit/Asynchronous FOSC/[64 (n + 1)] 001 8-bit/Asynchronous FOSC/[16 (n + 1)] 010 16-bit/Asynchronous 011 16-bit/Asynchronous 10x 8-bit/Synchronous FOSC/[4 (n + 1)] 11x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate= 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16%PIC18F1220/1320 DS39605F-page 136 © 2007 Microchip Technology Inc. TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 -010 0000 -010 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x BAUDCTL — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES BAUD RATE (K) SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — BAUD RATE (K) SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51 1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12 2.4 2.404 0.16 25 2403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — —© 2007 Microchip Technology Inc. DS39605F-page 137 PIC18F1220/1320 BAUD RATE (K) SYNC = 0, BRGH = 1, BRG16 = 0 FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 2.4 — — — — — — 2.441 1.73 255 2403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — BAUD RATE (K) SYNC = 0, BRGH = 1, BRG16 = 0 FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 — — — — — — 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — BAUD RATE (K) SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — BAUD RATE (K) SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)PIC18F1220/1320 DS39605F-page 138 © 2007 Microchip Technology Inc. BAUD RATE (K) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16 BAUD RATE (K) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832 1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207 2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103 9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25 19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12 57.6 58.824 2.12 16 55555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — — TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)© 2007 Microchip Technology Inc. DS39605F-page 139 PIC18F1220/1320 16.2.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 16-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Detect must receive a byte with the value 55h (ASCII “U”, which is also the LIN bus Sync character), in order to calculate the proper bit rate. The measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRG begins counting up using the preselected clock source on the first rising edge of RX. After eight bits on the RX pin, or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG registers. Once the 5th edge is seen (should correspond to the Stop bit), the ABDEN bit is automatically cleared. While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRG and SPBRGH will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes, by checking for 00h in the SPBRGH register. Refer to Table 16-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. 16.2.4 RECEIVING A SYNC (AUTO-BAUD RATE DETECT) To receive a Sync (Auto-Baud Rate Detect): 1. Configure the EUSART for asynchronous receive. TXEN should remain clear. SPBRGH:SPBRG may be left as is. The controller should operate in either PRI_RUN or PRI_IDLE. 2. Enable RXIF interrupts. Set RCIE, PEIE, GIE. 3. Enable Auto-Baud Rate Detect. Set ABDEN. 4. When the next RCIF interrupt occurs, the received baud rate has been measured. Read RCREG to clear RCIF and discard. Check SPBRGH:SPBRG for a valid value. The EUSART is ready for normal communications. Return from the interrupt. Allow the primary clock to run (PRI_RUN or PRI_IDLE). 5. Process subsequent RCIF interrupts normally as in asynchronous reception. Remain in PRI_RUN or PRI_IDLE until communications are complete. TABLE 16-4: BRG COUNTER CLOCK RATES Note 1: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature. BRG16 BRGH BRG Counter Clock 0 0 FOSC/512 0 1 FOSC/128 1 0 FOSC/128 1 1 FOSC/32 Note: During the ABD sequence, SPBRG and SPBRGH are both used as a 16-bit counter, independent of BRG16 setting.PIC18F1220/1320 DS39605F-page 140 © 2007 Microchip Technology Inc. FIGURE 16-1: AUTOMATIC BAUD RATE CALCULATION 16.3 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally independent, but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate, depending on the BRGH and BRG16 bits (TXSTA<2> and BAUDCTL<3>). Parity is not supported by the hardware, but can be implemented in software and stored as the 9th data bit. Asynchronous mode is available in all low-power modes; it is available in Sleep mode only when autowake-up on Sync Break is enabled. When in PRI_IDLE mode, no changes to the Baud Rate Generator values are required; however, other low-power mode clocks may operate at another frequency than the primary clock. Therefore, the Baud Rate Generator values may need to be adjusted. When operating in Asynchronous mode, the EUSART module consists of the following important elements: • Baud Rate Generator • Sampling Circuit • Asynchronous Transmitter • Asynchronous Receiver • Auto-Wake-up on Sync Break Character • 12-bit Break Character Transmit • Auto-Baud Rate Detection 16.3.1 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 16-2. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit, TXIF (PIR1<4>), is set. This interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless of the state of enable bit, TXIE, and cannot be cleared in software. Flag bit, TXIF, is not cleared immediately upon loading the Transmit Buffer register, TXREG. TXIF becomes valid in the second instruction cycle following the load instruction. Polling TXIF immediately following a load of TXREG will return invalid results. While flag bit, TXIF, indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit, TRMT, is a readonly bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. BRG Value RX pin ABDEN bit RCIF bit Bit 0 Bit 1 (Interrupt) Read RCREG BRG Clock Start Set by User Auto-Cleared XXXXh 0000h Edge #1 Bit 2 Bit 3 Edge #2 Bit 4 Bit 5 Edge #3 Bit 6 Bit 7 Edge #4 Edge #5 001Ch Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Stop Bit Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit, TXIF, is set when enable bit, TXEN, is set.© 2007 Microchip Technology Inc. DS39605F-page 141 PIC18F1220/1320 To set up an Asynchronous Transmission: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit TXIE. 4. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Load data to the TXREG register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 16-2: EUSART TRANSMIT BLOCK DIAGRAM FIGURE 16-3: ASYNCHRONOUS TRANSMISSION TXIF TXIE Interrupt TXEN Baud Rate CLK SPBRG Baud Rate Generator TX9D MSb LSb Data Bus TXREG Register TSR Register (8) 0 TX9 TRMT SPEN RB1/AN5/TX/CK/INT1 pin Pin Buffer and Control 8 • • • BRG16 SPBRGH Word 1 Word 1 Transmit Shift Reg Start bit bit 0 bit 1 bit 7/8 Write to TXREG Word 1 BRG Output (Shift Clock) RB1/AN5/TX/ TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) 1 TCY CK/INT1 (pin) Stop bitPIC18F1220/1320 DS39605F-page 142 © 2007 Microchip Technology Inc. FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) TABLE 16-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Transmit Shift Reg. Write to TXREG BRG Output (Shift Clock) RB1/AN5/TX/ TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Word 2 Word 1 Word 2 Stop bit Start bit Transmit Shift Reg. Word 1 Word 2 bit 0 bit 1 bit 7/8 bit 0 Note: This timing diagram shows two consecutive transmissions. 1 TCY 1 TCY CK/INT1 (pin) Start bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x TXREG EUSART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCTL — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.© 2007 Microchip Technology Inc. DS39605F-page 143 PIC18F1220/1320 16.3.2 EUSART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 16-5. The data is received on the RB4/AN6/RX/DT/KBI0 pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. To set up an Asynchronous Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit RCIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 7. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 16.3.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. FIGURE 16-5: EUSART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK Baud Rate Generator RB4/AN6/RX/DT/KBI0 Pin Buffer and Control SPEN Data Recovery CREN OERR FERR MSb RSR Register LSb RX9D RCREG Register FIFO Interrupt RCIF RCIE Data Bus 8 ÷ 64 ÷ 16 or Stop (8) 7 1 0 Start RX9 • • • BRG16 SPBRGH SPBRG or ÷ 4PIC18F1220/1320 DS39605F-page 144 © 2007 Microchip Technology Inc. To set up an Asynchronous Transmission: 1. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (see Section 16.2 “EUSART Baud Rate Generator (BRG)”). 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit TXIE. 4. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Load data to the TXREG register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 16-6: ASYNCHRONOUS RECEPTION TABLE 16-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Start bit bit 0 bit 7/8 bit 1 Stop bit 0 bit 7/8 bit Start bit Start bit 7/8 Stop bit bit RX (pin) Reg Rcv Buffer Reg Rcv Shift Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Word 1 RCREG Word 2 RCREG Stop bit Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x RCREG EUSART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCTL — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.© 2007 Microchip Technology Inc. DS39605F-page 145 PIC18F1220/1320 16.3.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCTL<1>). Once set, the typical receive sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN protocol.) Following a wake-up event, the module generates an RCIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 16-7) and asynchronously if the device is in Sleep mode (Figure 16-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared once a low-to-high transition is observed on the RX line, following the wakeup event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over. 16.3.4.1 Special Considerations Using Auto-Wake-up Since auto-wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the Stop bit may signal a false end-of-character and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all ‘0’s. This can be 00h (8 bytes) for standard RS-232 devices, or 000h (12 bits) for LIN bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient period, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. 16.3.4.2 Special Considerations Using the WUE Bit The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared after this when a rising edge is seen on RX/ DT. The interrupt condition is then cleared by reading the RCREG register. Ordinarily, the data in RCREG will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set) and the RCIF flag is set should not be used as an indicator of the integrity of the data in RCREG. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. FIGURE 16-7: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION FIGURE 16-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note 1: The EUSART remains in Idle while the WUE bit is set. Bit Set by User Cleared by hardware Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note 1: If the wake-up event requires a long oscillator warm-up time, the WUE bit may be cleared while the primary clock is still starting. 2: The EUSART remains in Idle while the WUE bit is set. Sleep Ends Enters Sleep Bit Set by User Cleared by hardware Note 1PIC18F1220/1320 DS39605F-page 146 © 2007 Microchip Technology Inc. 16.3.5 BREAK CHARACTER SEQUENCE The Enhanced USART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data. Note that the value of data written to TXREG will be ignored and all ‘0’s will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). Note that the data value written to the TXREG for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 16-9 for the timing of the Break character sequence. 16.3.5.1 Transmitting A Break Signal The Enhanced USART module has the capability of sending the Break signal that is required by the LIN bus standard. The Break signal consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Break signal is sent whenever the SENDB (TXSTA<3>) and TXEN (TXSTA<5>) bits are set and TXREG is loaded with data. The data written to TXREG will be ignored and all ‘0’s will be transmitted. SENDB is automatically cleared by hardware when the Break signal has been sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. To send a Break Signal: 1. Configure the EUSART for asynchronous transmissions (steps 1-5). Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (see Section 16.2 “EUSART Baud Rate Generator (BRG)”). 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit TXIE. 4. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF. 6. Set the SENDB bit. 7. Load a byte into TXREG. This triggers sending a Break signal. The Break signal is complete when TRMT is set. SENDB will also be cleared. See Figure 16-9 for the timing of the Break signal sequence. 16.3.6 RECEIVING A BREAK CHARACTER The Enhanced USART module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (12 bits for Break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section 16.3.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit before placing the EUSART in its Sleep mode. 16.3.6.1 Transmitting a Break Sync The following sequence will send a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. Configure the EUSART for the desired mode. 2. Set the TXEN and SENDB bits to set up the Break character. 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG.© 2007 Microchip Technology Inc. DS39605F-page 147 PIC18F1220/1320 16.3.6.2 Receiving a Break Sync To receive a Break Sync: 1. Configure the EUSART for asynchronous transmit and receive. TXEN should remain clear. SPBRGH:SPBRG may be left as is. 2. Enable auto-wake-up. Set WUE. 3. Enable RXIF interrupts. Set RCIE, PEIE, GIE. 4. The controller may be placed in any power managed mode. 5. An RCIF will be generated at the beginning of the Break signal. When the interrupt is received, read RCREG to clear RCIF and discard. Allow the controller to return to PRI_RUN mode. 6. Wait for the RX line to go high at the end of the Break signal. Wait for any of the following: WUE to clear automatically (poll), RB4/RX to go high (poll) or for RBIF to be set (poll or interrupt). If RBIF is used, check to be sure that RB4/RX is high before continuing. 7. Enable Auto-Baud Rate Detect. Set ABDEN. 8. Return from the interrupt. Allow the primary clock to start and stabilize (PRI_RUN or PRI_IDLE). 9. When the next RCIF interrupt occurs, the received baud rate has been measured. Read RCREG to clear RCIF and discard. Check SPBRGH:SPBRG for a valid value. The EUSART is ready for normal communications. Return from the interrupt. Allow the primary clock to run (PRI_RUN or PRI_IDLE). 10. Process subsequent RCIF interrupts normally as in asynchronous reception. TXEN should now be set if transmissions are needed. TXIF and TXIE may be set if transmit interrupts are desired. Remain in PRI_RUN or PRI_IDLE until communications are complete. Clear TXEN and return to step 2. FIGURE 16-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG BRG Output (Shift Clock) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXIF bit TX (pin) TRMT bit SENDB Dummy Write PIC18F1220/1320 DS39605F-page 148 © 2007 Microchip Technology Inc. 16.4 EUSART Synchronous Master Mode The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTA<4>). In addition, enable bit, SPEN (RCSTA<7>), is set in order to configure the RB1/AN5/ TX/CK/INT1 and RB4/AN6/RX/DT/KBI0 I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. Clock polarity is selected with the SCKP bit (BAUDCTL<5>); setting SCKP sets the Idle state on CK as high, while clearing the bit sets the Idle state as low. This option is provided to support Microwire devices with this module. 16.4.1 EUSART SYNCHRONOUS MASTER TRANSMISSION The EUSART transmitter block diagram is shown in Figure 16-2. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit, TXIF (PIR1<4>), is set. The interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless of the state of enable bit, TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit, TXIF, indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit, which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. To set up a Synchronous Master Transmission: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. If interrupts are desired, set enable bit TXIE. 4. If 9-bit transmission is desired, set bit TX9. 5. Enable the transmission by setting bit TXEN. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 16-10: SYNCHRONOUS TRANSMISSION bit 0 bit 1 bit 7 Word 1 Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 2 bit 0 bit 1 bit 7 RB4/AN6/RX/ RB1/AN5/TX/ Write to TXREG Reg TXIF bit (Interrupt Flag) TXEN bit ‘1’ ‘1’ Word 2 TRMT bit Write Word 1 Write Word 2 Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. DT/KBI0 pin CK/INT1 pin RB1/AN5/TX/ CK/INT1 pin (SCKP = 0) (SCKP = 1)© 2007 Microchip Technology Inc. DS39605F-page 149 PIC18F1220/1320 FIGURE 16-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION RB4/AN6/RX/DT/KBI0 pin RB1/AN5/TX/CK/INT1 pin Write to TXREG reg TXIF bit TRMT bit bit 0 bit 1 bit 2 bit 6 bit 7 TXEN bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x TXREG EUSART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCTL — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.PIC18F1220/1320 DS39605F-page 150 © 2007 Microchip Technology Inc. 16.4.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RB4/AN6/RX/DT/KBI0 pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, set enable bit RCIE. 5. If 9-bit reception is desired, set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCIE, was set. 8. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 16-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) CREN bit RB4/AN6/RX/ RB1/AN5/TX/ Write to bit SREN SREN bit RCIF bit (Interrupt) Read RXREG Q2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 ‘0’ bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ‘0’ Q1 Q2 Q3 Q4 Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. RB1/AN5/TX/ CK/INT1 pin CK/INT1 pin DT/KBI0 pin (SCKP = 0) (SCKP = 1)© 2007 Microchip Technology Inc. DS39605F-page 151 PIC18F1220/1320 TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x RCREG EUSART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCTL — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.PIC18F1220/1320 DS39605F-page 152 © 2007 Microchip Technology Inc. 16.5 EUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the RB1/AN5/TX/CK/INT1 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 16.5.1 EUSART SYNCHRONOUS SLAVE TRANSMIT The operation of the Synchronous Master and Slave modes are identical, except in the case of the Sleep mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in the TXREG register. c) Flag bit, TXIF, will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit, TXIF, will now be set. e) If enable bit, TXIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. 2. Clear bits CREN and SREN. 3. If interrupts are desired, set enable bit TXIE. 4. If 9-bit transmission is desired, set bit TX9. 5. Enable the transmission by setting enable bit TXEN. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x TXREG EUSART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCTL — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.© 2007 Microchip Technology Inc. DS39605F-page 153 PIC18F1220/1320 16.5.2 EUSART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode. Once the word is received, the RSR register will transfer the data to the RCREG register; if the RCIE enable bit is set, the interrupt generated will wake the chip from low-power mode. If the global interrupt is enabled, the program will branch to the interrupt vector. To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. 2. If interrupts are desired, set enable bit RCIE. 3. If 9-bit reception is desired, set bit RX9. 4. To enable reception, set enable bit CREN. 5. Flag bit, RCIF, will be set when reception is complete. An interrupt will be generated if enable bit, RCIE, was set. 6. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register. 8. If any error occurred, clear the error by clearing bit CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x RCREG EUSART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCTL — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.PIC18F1220/1320 DS39605F-page 154 © 2007 Microchip Technology Inc. NOTES:© 2007 Microchip Technology Inc. DS39605F-page 155 PIC18F1220/1320 17.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) converter module has seven inputs for the PIC18F1220/1320 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. A new feature for the A/D converter is the addition of programmable acquisition time. This feature allows the user to select a new channel for conversion and to set the GO/DONE bit immediately. When the GO/DONE bit is set, the selected channel is sampled for the programmed acquisition time before a conversion is actually started. This removes the firmware overhead that may have been required to allow for an acquisition (sampling) period (see Register 17-3 and Section 17.3 “Selecting and Configuring Automatic Acquisition Time”). The module has five registers: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) The ADCON0 register, shown in Register 17-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 17-2, configures the functions of the port pins. The ADCON2 register, shown in Register 17-3, configures the A/D clock source, programmed acquisition time and justification. REGISTER 17-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VCFG1 VCFG0 — CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 bit 7-6 VCFG<1:0>: Voltage Reference Configuration bits bit 5 Unimplemented: Read as ‘0’ bit 4-2 CHS2:CHS0: Analog Channel Select bits 000 = Channel 0 (AN0) 001 = Channel 1 (AN1) 010 = Channel 2 (AN2) 011 = Channel 3 (AN3) 100 = Channel 4 (AN4) 101 = Channel 5 (AN5) 110 = Channel 6 (AN6) 111 = Unimplemented(1) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Note 1: Performing a conversion on unimplemented channels returns full-scale results. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown A/D VREF+ A/D VREF- 00 AVDD AVSS 01 External VREF+ AVSS 10 AVDD External VREF- 11 External VREF+ External VREF-PIC18F1220/1320 DS39605F-page 156 © 2007 Microchip Technology Inc. REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 PCFG6: A/D Port Configuration bit – AN6 1 = Pin configured as a digital port 0 = Pin configured as an analog channel – digital input disabled and reads ‘0’ bit 5 PCFG5: A/D Port Configuration bit – AN5 1 = Pin configured as a digital port 0 = Pin configured as an analog channel – digital input disabled and reads ‘0’ bit 4 PCFG4: A/D Port Configuration bit – AN4 1 = Pin configured as a digital port 0 = Pin configured as an analog channel – digital input disabled and reads ‘0’ bit 3 PCFG3: A/D Port Configuration bit – AN3 1 = Pin configured as a digital port 0 = Pin configured as an analog channel – digital input disabled and reads ‘0’ bit 2 PCFG2: A/D Port Configuration bit – AN2 1 = Pin configured as a digital port 0 = Pin configured as an analog channel – digital input disabled and reads ‘0’ bit 1 PCFG1: A/D Port Configuration bit – AN1 1 = Pin configured as a digital port 0 = Pin configured as an analog channel – digital input disabled and reads ‘0’ bit 0 PCFG0: A/D Port Configuration bit – AN0 1 = Pin configured as a digital port 0 = Pin configured as an analog channel – digital input disabled and reads ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 157 PIC18F1220/1320 REGISTER 17-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 000 = 0 TAD(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12 TAD 110 = 16 TAD 111 = 20 TAD bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock derived from A/D RC oscillator)(1) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock derived from A/D RC oscillator)(1) Note: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 158 © 2007 Microchip Technology Inc. The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF- pins. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input, or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ADRESL registers, the GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 17-1. FIGURE 17-1: A/D BLOCK DIAGRAM (Input Voltage) VAIN VREFH Reference Voltage AVDD VCFG1:VCFG0 CHS2:CHS0 AN6(1) AN5 AN4 AN3/VREF+ AN2/VREFAN1 AN0 111 110 101 100 011 010 001 000 10-bit Converter VREFL AVSS A/D Note 1: I/O pins have diode protection to VDD and VSS. 0x 1x x1 x0 AVDD© 2007 Microchip Technology Inc. DS39605F-page 159 PIC18F1220/1320 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 17.1 “A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. To do an A/D Conversion: 1. Configure the A/D module: • Configure analog pins, voltage reference and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D acquisition time (ADCON2) • Select A/D conversion clock (ADCON2) • Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set GIE bit 3. Wait the required acquisition time (if required). 4. Start conversion: • Set GO/DONE bit (ADCON0 register) 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt 6. Read A/D Result registers (ADRESH:ADRESL); clear bit, ADIF, if required. 7. For the next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts. FIGURE 17-2: ANALOG INPUT MODEL VAIN CPIN Rs ANx 5 pF VDD VT = 0.6V VT = 0.6V ILEAKAGE RIC ≤ 1k Sampling Switch SS RSS CHOLD = 120 pF VSS 6V Sampling Switch 5V 4V 3V 2V 5 6 7 8 9 10 11 (kΩ) VDD ± 500 nA Legend: CPIN = input capacitance VT = threshold voltage ILEAKAGE = leakage current at the pin due to various junctions RIC = interconnect resistance SS = sampling switch CHOLD = sample/hold capacitance (from DAC) RSS = sampling switch resistancePIC18F1220/1320 DS39605F-page 160 © 2007 Microchip Technology Inc. 17.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 17-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 kΩ. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. To calculate the minimum acquisition time, Equation 17-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Example 17-1 shows the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assumptions: CHOLD = 120 pF Rs = 2.5 kΩ Conversion Error ≤ 1/2 LSb VDD = 5V → RSS = 7 kΩ Temperature = 50°C (system max.) VHOLD = 0V @ time = 0 17.2 A/D VREF+ and VREF- References If external voltage references are used instead of the internal AVDD and AVSS sources, the source impedance of the VREF+ and VREF- voltage sources must be considered. During acquisition, currents supplied by these sources are insignificant. However, during conversion, the A/D module sinks and sources current through the reference sources. In order to maintain the A/D accuracy, the voltage reference source impedances should be kept low to reduce voltage changes. These voltage changes occur as reference currents flow through the reference source impedance. The maximum recommended impedance of the VREF+ and VREF- external reference voltage sources is 250Ω. EQUATION 17-1: ACQUISITION TIME EQUATION 17-2: A/D MINIMUM CHARGING TIME EXAMPLE 17-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME Note: When the conversion is started, the holding capacitor is disconnected from the input pin. TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF VHOLD = (ΔVREF – (ΔVREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) TACQ =TAMP + TC + TCOFF TAMP = 5 μs TCOFF = (Temp – 25ºC)(0.05 μs/ºC) (50ºC – 25ºC)(0.05 μs/ºC) 1.25 μs Temperature coefficient is only required for temperatures > 25ºC. Below 25ºC, TCOFF = 0 μs. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) μs -(120 pF) (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004883) μs 9.61 μs TACQ = 5 μs + 1.25 μs + 9.61 μs 12.86 μs© 2007 Microchip Technology Inc. DS39605F-page 161 PIC18F1220/1320 17.3 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT2:ACQT0 bits (ADCON2<5:3>) remain in their Reset state (‘000’) and is compatible with devices that do not offer programmable acquisition times. If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 17.4 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: • 2 TOSC • 4 TOSC • 8 TOSC • 16 TOSC • 32 TOSC • 64 TOSC • Internal RC oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the minimum TAD (approximately 2 μs, see parameter 130 for more information). Table 17-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. TABLE 17-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS2:ADCS0 PIC18F1220/1320 PIC18LF1220/1320(4) 2 TOSC 000 1.25 MHz 666 kHz 4 TOSC 100 2.50 MHz 1.33 MHz 8 TOSC 001 5.00 MHz 2.66 MHz 16 TOSC 101 10.0 MHz 5.33 MHz 32 TOSC 010 20.0 MHz 10.65 MHz 64 TOSC 110 40.0 MHz 21.33 MHz RC(3) x11 1.00 MHz(1) 1.00 MHz(2) Note 1: The RC source has a typical TAD time of 4 μs. 2: The RC source has a typical TAD time of 6 μs. 3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. 4: Low-power devices only.PIC18F1220/1320 DS39605F-page 162 © 2007 Microchip Technology Inc. 17.5 Operation in Low-Power Modes The selection of the automatic acquisition time and the A/D conversion clock is determined, in part, by the lowpower mode clock source and frequency while in a low-power mode. If the A/D is expected to operate while the device is in a low-power mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the low-power mode clock that will be used. After the low-power mode is entered (either of the Run modes), an A/D acquisition or conversion may be started. Once an acquisition or conversion is started, the device should continue to be clocked by the same low-power mode clock source until the conversion has been completed. If desired, the device may be placed into the corresponding low-power (ANY)_IDLE mode during the conversion. If the low-power mode clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in the Low-Power Sleep mode requires the A/D RC clock to be selected. If bits, ACQT2:ACQT0, are set to ‘000’ and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Low-Power Sleep mode. The IDLEN and SCS bits in the OSCCON register must have already been cleared prior to starting the conversion. 17.6 Configuring Analog Port Pins The ADCON1, TRISA and TRISB registers all configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the Port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will be accurately converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device’s specification limits.© 2007 Microchip Technology Inc. DS39605F-page 163 PIC18F1220/1320 17.7 A/D Conversions Figure 17-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Low-Power Sleep mode before the conversion begins. Figure 17-4 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are set to ‘010’ and selecting a 4 TAD acquisition time before the conversion starts. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. FIGURE 17-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) FIGURE 17-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11 Set GO bit Holding capacitor is disconnected from analog input (typically 100 ns) TCY – TAD TAD9 TAD10 Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. Conversion Starts b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 2 3 4 5 6 7 8 11 Set GO bit (Holding capacitor is disconnected) 9 10 Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. Conversion Starts 1 2 3 4 (Holding capacitor continues acquiring input) TACQT Cycles TAD Cycles Automatic Acquisition Time b9 b8 b7 b6 b5 b4 b3 b2 b1 b0PIC18F1220/1320 DS39605F-page 164 © 2007 Microchip Technology Inc. 17.8 Use of the CCP1 Trigger An A/D conversion can be started by the “special event trigger” of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time selected before the “special event trigger” sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the “special event trigger” will be ignored by the A/D module, but will still reset the Timer1 (or Timer3) counter. TABLE 17-2: SUMMARY OF A/D REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 PIR2 OSCFIF — — EEIF — LVDIF TMR3IF — 0--0 -00- 0--0 -00- PIE2 OSCFIE — — EEIE — LVDIE TMR3IE — 0--0 -00- 0--0 -00- IPR2 OSCFIP — — EEIP — LVDIP TMR3IP — 1--1 -11- 1--1 -11- ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu ADCON0 VCFG1 VCFG0 — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000 ADCON1 — PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 0-00 0000 PORTA RA7(3) RA6(2) RA5(1) RA4 RA3 RA2 RA1 RA0 qq0x 0000 uu0u 0000 TRISA TRISA7(3) TRISA6(2) — PORTA Data Direction Register qq-1 1111 11-1 1111 PORTB Read PORTB pins, Write LATB Latch xxxx xxxx uuuu uuuu TRISB PORTB Data Direction Register 1111 1111 1111 1111 LATB PORTB Output Data Latch xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged, q = depends on CONFIG1H<3:0>, – = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: RA5 port bit is available only as an input pin when the MCLRE bit in the configuration register is ‘0’. 2: RA6 and TRISA6 are available only when the primary oscillator mode selection offers RA6 as a port pin; otherwise, RA6 always reads ‘0’, TRISA6 always reads ‘1’ and writes to both are ignored (see CONFIG1H<3:0>). 3: RA7 and TRISA7 are available only when the internal RC oscillator is configured as the primary oscillator in CONFIG1H<3:0>; otherwise, RA7 always reads ‘0’, TRISA7 always reads ‘1’ and writes to both are ignored.© 2007 Microchip Technology Inc. DS39605F-page 165 PIC18F1220/1320 18.0 LOW-VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do “housekeeping tasks”, before the device voltage exits the valid operating range. This can be done using the Low-Voltage Detect module. This module is a software programmable circuitry, where a device voltage trip point can be specified. When the voltage of the device becomes lower then the specified point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to that interrupt source. The Low-Voltage Detect circuitry is completely under software control. This allows the circuitry to be turned off by the software, which minimizes the current consumption for the device. Figure 18-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage VA, the LVD logic generates an interrupt. This occurs at time TA. The application software then has the time, until the device voltage is no longer in valid operating range, to shut down the system. Voltage point VB is the minimum valid operating voltage specification. This occurs at time TB. The difference, TB – TA, is the total time for shutdown. The block diagram for the LVD module is shown in Figure 18-2 (following page). A comparator uses an internally generated reference voltage as the set point. When the selected tap output of the device voltage crosses the set point (is lower than), the LVDIF bit is set. Each node in the resistor divider represents a “trip point” voltage. The “trip point” voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the 1.2V internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Figure 18-2). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>). FIGURE 18-1: TYPICAL LOW-VOLTAGE DETECT APPLICATION Time Voltage VA VB TA TB Legend: VA = LVD trip point VB = Minimum valid device operating voltagePIC18F1220/1320 DS39605F-page 166 © 2007 Microchip Technology Inc. FIGURE 18-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits, LVDL3:LVDL0, are set to ‘1111’. In this state, the comparator input is multiplexed from the external input pin, LVDIN (Figure 18-3). This gives users flexibility, because it allows them to configure the Low-Voltage Detect interrupt to occur at any voltage in the valid operating range. FIGURE 18-3: LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM LVDIF VDD 16-to-1 MUX LVDEN LVD Control Register Internally Generated Reference Voltage LVDIN 1.2V LVD EN LVD Control 16-to-1 MUX BGAP BODEN LVDEN VxEN LVDIN Register VDD VDD Externally Generated Trip Point© 2007 Microchip Technology Inc. DS39605F-page 167 PIC18F1220/1320 18.1 Control Register The Low-Voltage Detect Control register controls the operation of the Low-Voltage Detect circuitry. REGISTER 18-1: LVDCON REGISTER U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled bit 4 LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.04V-5.15V 1101 = 3.76V-4.79V 1100 = 3.58V-4.56V 1011 = 3.41V-4.34V 1010 = 3.23V-4.11V 1001 = 3.14V-4.00V 1000 = 2.96V-3.77V 0111 = 2.70V-3.43V 0110 = 2.53V-3.21V 0101 = 2.43V-3.10V 0100 = 2.25V-2.86V 0011 = 2.16V-2.75V 0010 = 1.99V-2.53V 0001 = Reserved 0000 = Reserved Note: LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage of the device, are not tested. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320 DS39605F-page 168 © 2007 Microchip Technology Inc. 18.2 Operation Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked. After doing the check, the LVD module may be disabled. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has stabilized, all status flags may be cleared. The module will then indicate the proper state of the system. The following steps are needed to set up the LVD module: 1. Write the value to the LVDL3:LVDL0 bits (LVDCON register), which selects the desired LVD trip point. 2. Ensure that LVD interrupts are disabled (the LVDIE bit is cleared or the GIE bit is cleared). 3. Enable the LVD module (set the LVDEN bit in the LVDCON register). 4. Wait for the LVD module to stabilize (the IRVST bit to become set). 5. Clear the LVD interrupt flag, which may have falsely become set, until the LVD module has stabilized (clear the LVDIF bit). 6. Enable the LVD interrupt (set the LVDIE and the GIE bits). Figure 18-4 shows typical waveforms that the LVD module may be used to detect. FIGURE 18-4: LOW-VOLTAGE DETECT WAVEFORMS VLVD VDD LVDIF VLVD VDD Enable LVD Internally Generated TIVRST LVDIF may not be set. Enable LVD LVDIF LVDIF cleared in software LVDIF cleared in software LVDIF cleared in software, CASE 1: CASE 2: LVDIF remains set since LVD condition still exists Reference Stable Internally Generated Reference Stable TIVRST© 2007 Microchip Technology Inc. DS39605F-page 169 PIC18F1220/1320 18.2.1 REFERENCE VOLTAGE SET POINT The internal reference voltage of the LVD module may be used by other internal circuitry (the programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter 36. The low-voltage interrupt flag will not be enabled until a stable reference voltage is reached. Refer to the waveform in Figure 18-4. 18.2.2 CURRENT CONSUMPTION When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter D022B. 18.3 Operation During Sleep When enabled, the LVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wakeup from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. 18.4 Effects of a Reset A device Reset forces all registers to their Reset state. This forces the LVD module to be turned off. PIC18F1220/1320 DS39605F-page 170 © 2007 Microchip Technology Inc. NOTES:© 2007 Microchip Technology Inc. DS39605F-page 171 PIC18F1220/1320 19.0 SPECIAL FEATURES OF THE CPU PIC18F1220/1320 devices include several features intended to maximize system reliability, minimize cost through elimination of external components and offer code protection. These are: • Oscillator Selection • Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Fail-Safe Clock Monitor • Two-Speed Start-up • Code Protection • ID Locations • In-Circuit Serial Programming Several oscillator options are available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. These are discussed in detail in Section 2.0 “Oscillator Configurations”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F1220/1320 devices have a Watchdog Timer, which is either permanently enabled via the configuration bits, or software controlled (if configured as disabled). The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate configuration register bits. 19.1 Configuration Bits The configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes. Programming the configuration registers is done in a manner similar to programming the Flash memory. The EECON1 register WR bit starts a self-timed write to the configuration register. In normal operation mode, a TBLWT instruction, with the TBLPTR pointing to the configuration register, sets up the address and the data for the configuration register write. Setting the WR bit starts a long write to the configuration register. The configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a ‘1’ or a ‘0’ into the cell. For additional details on Flash programming, refer to Section 6.5 “Writing to Flash Program Memory”. TABLE 19-1: CONFIGURATION BITS AND DEVICE IDS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value 300001h CONFIG1H IESO FSCM — — FOSC3 FOSC2 FOSC1 FOSC0 11-- 1111 300002h CONFIG2L — — — — BORV1 BORV0 BOR PWRTEN ---- 1111 300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDT ---1 1111 300005h CONFIG3H MCLRE — — — — — — — 1--- ---- 300006h CONFIG4L DEBUG — — — — LVP — STVR 1--- -1-1 300008h CONFIG5L — — — — — — CP1 CP0 ---- --11 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L — — — — — — WRT1 WRT0 ---- --11 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L — — — — — — EBTR1 EBTR0 ---- --11 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1(1) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(1) 3FFFFFh DEVID2(1) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0111 Legend: x = unknown, u = unchanged, – = unimplemented. Shaded cells are unimplemented, read as ‘0’. Note 1: See Register 19-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.PIC18F1220/1320 DS39605F-page 172 © 2007 Microchip Technology Inc. REGISTER 19-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 IESO FSCM — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled bit 6 FSCM: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 FOSC<3:0>: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 1001 = Internal RC oscillator, CLKO function on RA6 and port function on RA7 1000 = Internal RC oscillator, port function on RA6 and port function on RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state© 2007 Microchip Technology Inc. DS39605F-page 173 PIC18F1220/1320 REGISTER 19-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BORV1 BORV0 BOR PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = Reserved 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 1 BOR: Brown-out Reset Enable bit(1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 0 PWRTEN: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed statePIC18F1220/1320 DS39605F-page 174 © 2007 Microchip Technology Inc. REGISTER 19-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDT: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state© 2007 Microchip Technology Inc. DS39605F-page 175 PIC18F1220/1320 REGISTER 19-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) REGISTER 19-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 MCLRE — — — — — — — bit 7 bit 0 bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled, RA5 input pin disabled 0 = RA5 input pin enabled, MCLR disabled bit 6-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG — — — — LVP — STVR bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit (see note) 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6-3 Unimplemented: Read as ‘0’ bit 2 LVP: Low-Voltage ICSP Enable bit 1 = Low-Voltage ICSP enabled 0 = Low-Voltage ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVR: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state Note: The Timer1 oscillator shares the T1OSI and T1OSO pins with the PGD and PGC pins used for programming and debugging. When using the Timer1 oscillator, In-Circuit Serial Programming (ICSP) may not function correctly (high voltage or low voltage), or the In-Circuit Debugger (ICD) may not communicate with the controller. As a result of using either ICSP or ICD, the Timer1 crystal may be damaged. If ICSP or ICD operations are required, the crystal should be disconnected from the circuit (disconnect either lead) or installed after programming. The oscillator loading capacitors may remain in-circuit during ICSP or ICD operation. PIC18F1220/1320 DS39605F-page 176 © 2007 Microchip Technology Inc. REGISTER 19-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) REGISTER 19-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — — — CP1 CP0 bit 7 bit 0 bit 7-2 Unimplemented: Read as ‘0’ bit 1 CP1: Code Protection bit (PIC18F1320) 1 = Block 1 (001000-001FFFh) not code-protected 0 = Block 1 (001000-001FFFh) code-protected bit 0 CP0: Code Protection bit (PIC18F1320) 1 = Block 0 (00200-000FFFh) not code-protected 0 = Block 0 (00200-000FFFh) code-protected bit 1 CP1: Code Protection bit (PIC18F1220) 1 = Block 1 (000800-000FFFh) not code-protected 0 = Block 1 (000800-000FFFh) code-protected bit 0 CP0: Code Protection bit (PIC18F1220) 1 = Block 0 (000200-0007FFh) not code-protected 0 = Block 0 (000200-0007FFh) code-protected Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot Block (000000-0001FFh) not code-protected 0 = Boot Block (000000-0001FFh) code-protected bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state© 2007 Microchip Technology Inc. DS39605F-page 177 PIC18F1220/1320 REGISTER 19-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) REGISTER 19-9: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 — — — — — — WRT1 WRT0 bit 7 bit 0 bit 7-2 Unimplemented: Read as ‘0’ bit 1 WRT1: Write Protection bit (PIC18F1320) 1 = Block 1 (001000-001FFFh) not write-protected 0 = Block 1 (001000-001FFFh) write-protected bit 0 WRT0: Write Protection bit (PIC18F1320) 1 = Block 0 (00200-000FFFh) not write-protected 0 = Block 0 (00200-000FFFh) write-protected bit 1 WRT1: Write Protection bit (PIC18F1220) 1 = Block 1 (000800-000FFFh) not write-protected 0 = Block 1 (000800-000FFFh) write-protected bit 0 WRT0: Write Protection bit (PIC18F1220) 1 = Block 0 (000200-0007FFh) not write-protected 0 = Block 0 (000200-0007FFh) write-protected Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state R/P-1 R/P-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC — — — — — bit 7 bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot Block (000000-0001FFh) not write-protected 0 = Boot Block (000000-0001FFh) write-protected bit 5 WRTC: Configuration Register Write Protection bit 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected Note: This bit is read-only in normal execution mode; it can be written only in Program mode. bit 4-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed statePIC18F1220/1320 DS39605F-page 178 © 2007 Microchip Technology Inc. REGISTER 19-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) REGISTER 19-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 — — — — — — EBTR1 EBTR0 bit 7 bit 0 bit 7-2 Unimplemented: Read as ‘0’ bit 1 EBTR1: Table Read Protection bit (PIC18F1320) 1 = Block 1 (001000-001FFFh) not protected from table reads executed in other blocks 0 = Block 1 (001000-001FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit (PIC18F1320) 1 = Block 0 (00200-000FFFh) not protected from table reads executed in other blocks 0 = Block 0 (00200-000FFFh) protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit (PIC18F1220) 1 = Block 1 (000800-000FFFh) not protected from table reads executed in other blocks 0 = Block 1 (000800-000FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit (PIC18F1220) 1 = Block 0 (000200-0007FFh) not protected from table reads executed in other blocks 0 = Block 0 (000200-0007FFh) protected from table reads executed in other blocks Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state U-0 R/P-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot Block (000000-0001FFh) not protected from table reads executed in other blocks 0 = Boot Block (000000-0001FFh) protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state© 2007 Microchip Technology Inc. DS39605F-page 179 PIC18F1220/1320 REGISTER 19-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F1220/1320 DEVICES REGISTER 19-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F1220/1320 DEVICES RRRRRRRR DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits 111 = PIC18F1220 110 = PIC18F1320 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state RRRRRRRR DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number. 0000 0111 = PIC18F1220/1320 devices Note: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified by using the entire DEV10:DEV0 bit sequence. Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed statePIC18F1220/1320 DS39605F-page 180 © 2007 Microchip Technology Inc. 19.2 Watchdog Timer (WDT) For PIC18F1220/1320 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: execute a SLEEP or CLRWDT instruction, the IRCF bits (OSCCON<6:4>) are changed or a clock failure has occurred. Adjustments to the internal oscillator clock period using the OSCTUNE register also affect the period of the WDT by the same factor. For example, if the INTRC period is increased by 3%, then the WDT period is increased by 3%. 19.2.1 CONTROL REGISTER Register 19-14 shows the WDTCON register. This is a readable and writable register, which contains a control bit that allows software to override the WDT enable configuration bit, only if the configuration bit has disabled the WDT. FIGURE 19-1: WDT BLOCK DIAGRAM REGISTER 19-14: WDTCON REGISTER Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: Changing the setting of the IRCF bits (OSCCON<6:4>) clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed the postscaler count will be cleared. U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN bit 7 bit 0 bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note: This bit has no effect if the configuration bit, WDTEN (CONFIG2H<0>), is enabled. Legend: R = Readable bit W = Writable bit -n = Value at POR U = Unimplemented bit, read as ‘0’ INTRC Oscillator WDT Wake-up Reset WDT WDT Counter (31 kHz) Programmable Postscaler 1:1 to 1:32,768 Enable WDT WDTPS<3:0> SWDTEN WDTEN CLRWDT 4 from Sleep Reset All Device Sleep INTRC Control Resets ÷125© 2007 Microchip Technology Inc. DS39605F-page 181 PIC18F1220/1320 TABLE 19-2: SUMMARY OF WATCHDOG TIMER REGISTERS 19.3 Two-Speed Start-up The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO bit in Configuration Register 1H (CONFIG1H<7>). Two-Speed Start-up is available only if the primary oscillator mode is LP, XT, HS or HSPLL (crystal-based modes). Other sources do not require an OST start-up delay; for these, Two-Speed Start-up is disabled. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a Power-on Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. Because the OSCCON register is cleared on Reset events, the INTOSC (or postscaler) clock source is not initially available after a Reset event; the INTRC clock is used directly at its base frequency. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IFRC2:IFRC0, immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting IFRC2:IFRC0 prior to entering Sleep mode. In all other power managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. 19.3.1 SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP While using the INTRC oscillator in Two-Speed Startup, the device still obeys the normal command sequences for entering power managed modes, including serial SLEEP instructions (refer to Section 3.1.3 “Multiple Sleep Commands”). In practice, this means that user code can change the SCS1:SCS0 bit settings and issue SLEEP commands before the OST times out. This would allow an application to briefly wake-up, perform routine “housekeeping” tasks and return to Sleep before the device starts to operate from the primary oscillator. User code can also check if the primary clock source is currently providing the system clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the system clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode. FIGURE 19-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONFIG2H — — — WDTPS3 WDTPS2 WDTPS2 WDTPS0 WDTEN RCON IPEN — — RI TO PD POR BOR WDTCON — — — — — — — SWDTEN Legend: Shaded cells are not used by the Watchdog Timer. Q1 Q3 Q4 OSC1 Peripheral Program PC PC + 2 INTOSC PLL Clock Q1 PC + 6 Q2 Output Q3 Q4 Q1 CPU Clock PC + 4 Clock Counter Q2 Q2 Q3 Q4 Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. Wake from Interrupt Event TPLL(1) 12345678 Clock Transition OSTS bit Set Multiplexer TOST(1)PIC18F1220/1320 DS39605F-page 182 © 2007 Microchip Technology Inc. 19.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation, in the event of an external oscillator failure, by automatically switching the system clock to the internal oscillator block. The FSCM function is enabled by setting the Fail-Safe Clock Monitor Enable bit, FSCM (CONFIG1H<6>). When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide an instant backup clock in the event of a clock failure. Clock monitoring (shown in Figure 19-3) is accomplished by creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral system clock and the sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the system clock source, but cleared on the rising edge of the sample clock. FIGURE 19-3: FSCM BLOCK DIAGRAM Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 19-4). This causes the following: • the FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>); • the system clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source – this is the Fail-Safe condition); and • the WDT is reset. Since the postscaler frequency from the internal oscillator block may not be sufficiently stable, it may be desirable to select another clock configuration and enter an alternate power managed mode (see Section 19.3.1 “Special Considerations for Using Two-Speed Start-up” and Section 3.1.3 “Multiple Sleep Commands” for more details). This can be done to attempt a partial recovery, or execute a controlled shutdown. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IFRC2:IFRC0, immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting IFRC2:IFRC0 prior to entering Sleep mode. Adjustments to the internal oscillator block, using the OSCTUNE register, also affect the period of the FSCM by the same factor. This can usually be neglected, as the clock frequency being monitored is generally much higher than the sample clock frequency. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible. 19.4.1 FSCM AND THE WATCHDOG TIMER Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. Depending on the frequency selected by the IRCF2:IRCF0 bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, Fail-Safe Clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. Peripheral INTRC ÷ 64 S C Q (32 μs) 488 Hz (2.048 ms) Clock Monitor Latch (CM) (edge-triggered) Clock Failure Detected Source Clock Q© 2007 Microchip Technology Inc. DS39605F-page 183 PIC18F1220/1320 19.4.2 EXITING FAIL-SAFE OPERATION The Fail-Safe condition is terminated by either a device Reset, or by entering a power managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTOSC multiplexer provides the system clock until the primary clock source becomes ready (similar to a TwoSpeed Start-up). The clock system source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The FailSafe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTOSC multiplexer. The OSCCON register will remain in its Reset state until a power managed mode is entered. Entering a power managed mode by loading the OSCCON register and executing a SLEEP instruction will clear the Fail-Safe condition. When the Fail-Safe condition is cleared, the clock monitor will resume monitoring the peripheral clock. 19.4.3 FSCM INTERRUPTS IN POWER MANAGED MODES As previously mentioned, entering a power managed mode clears the Fail-Safe condition. By entering a power managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-Safe monitoring of the power managed clock source resumes in the power managed mode. If an oscillator failure occurs during power managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, the device will not exit the power managed mode on oscillator failure. Instead, the device will continue to operate as before, but clocked by the INTOSC multiplexer. While in Idle mode, subsequent interrupts will cause the CPU to begin executing instructions while being clocked by the INTOSC multiplexer. The device will not transition to a different clock source until the Fail-Safe condition is cleared. FIGURE 19-4: FSCM TIMING DIAGRAM OSCFIF CM Output System Clock Output Sample Clock Failure Detected Oscillator Failure Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. (Q) CM Test CM Test CM TestPIC18F1220/1320 DS39605F-page 184 © 2007 Microchip Technology Inc. 19.4.4 POR OR WAKE FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or Low-Power Sleep mode. When the primary system clock is EC, RC or INTRC modes, monitoring can begin immediately following these events. For oscillator modes involving a crystal or resonator (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FCSM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the system clock and functions until the primary clock is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source As noted in Section 19.3.1 “Special Considerations for Using Two-Speed Start-up”, it is also possible to select another clock configuration and enter an alternate power managed mode while waiting for the primary system clock to become stable. When the new powered managed mode is selected, the primary clock is disabled. Note: The same logic that prevents false oscillator failure interrupts on POR or wake from Sleep will also prevent the detection of the oscillator’s failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. © 2007 Microchip Technology Inc. DS39605F-page 185 PIC18F1220/1320 19.5 Program Verification and Code Protection The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC devices. The user program memory is divided into three blocks. One of these is a boot block of 512 bytes. The remainder of the memory is divided into two blocks on binary boundaries. Each of the three blocks has three protection bits associated with them. They are: • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) Figure 19-5 shows the program memory organization for 4 and 8-Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 19-3. FIGURE 19-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F1220/1320 TABLE 19-3: SUMMARY OF CODE PROTECTION REGISTERS Block Code Protection Controlled By: MEMORY SIZE/DEVICE Block Code Protection Controlled By: Address Range 4 Kbytes (PIC18F1220) 8 Kbytes (PIC18F1320) Address Range CPB, WRTB, EBTRB 000000h 0001FFh Boot Block Boot Block 000000h 0001FFh CPB, WRTB, EBTRB CP0, WRT0, EBTR0 000200h 0007FFh Block 0 Block 0 000200h CP0, WRT0, EBTR0 CP1, WRT1, EBTR1 000800h 000FFFh Block 1 000FFFh (Unimplemented Memory Space) 001000h Unimplemented Read ‘0’s Block 1 001000h CP1, WRT1, EBTR1 001FFFh 1FFFFFh Unimplemented Read ‘0’s 002000h 1FFFFFh (Unimplemented Memory Space) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — — — CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — — — WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — — — EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented.PIC18F1220/1320 DS39605F-page 186 © 2007 Microchip Technology Inc. 19.5.1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to, or written from, any location using the table read and table write instructions. The device ID may be read with table reads. The configuration registers may be read and written with the table read and table write instructions. In normal execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTn configuration bit is ‘0’. The EBTRn bits control table reads. For a block of user memory with the EBTRn bit set to ‘0’, a table read instruction that executes from within that block is allowed to read. A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading ‘0’s. Figures 19-6 through 19-8 illustrate table write and table read protection. FIGURE 19-6: TABLE WRITE (WRTn) DISALLOWED: PIC18F1320 Note: Code protection bits may only be written to a ‘0’ from a ‘1’ state. It is not possible to write a ‘1’ to a bit in the ‘0’ state. Code protection bits are only set to ‘1’ by a full Chip Erase or Block Erase function. The full Chip Erase and Block Erase functions can only be initiated via ICSP or an external programmer. 000000h 0001FFh 000200h 000FFFh 001000h 001FFFh WRTB, EBTRB = 11 WRT0, EBTR0 = 01 TBLWT * TBLPTR = 0002FFh PC = 0007FEh PC = 0017FEh TBLWT * Register Values Program Memory Configuration Bit Settings Results: All table writes disabled to Blockn whenever WRTn = 0. WRT1, EBTR1 = 11© 2007 Microchip Technology Inc. DS39605F-page 187 PIC18F1220/1320 FIGURE 19-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED: PIC18F1320 FIGURE 19-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED: PIC18F1320 000000h 0001FFh 000200h 000FFFh 001000h 001FFFh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 WRT1, EBTR1 = 11 TBLPTR = 0002FFh Register Values Program Memory Configuration Bit Settings PC = 001FFEh TBLRD * Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. 000000h 0001FFh 000200h 000FFFh 001000h 001FFFh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 WRT1, EBTR1 = 11 TBLRD * TBLPTR = 0002FFh PC = 0007FEh Register Values Program Memory Configuration Bit Settings Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR.PIC18F1220/1320 DS39605F-page 188 © 2007 Microchip Technology Inc. 19.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM, regardless of the protection bit settings. 19.5.3 CONFIGURATION REGISTER PROTECTION The configuration registers can be write-protected. The WRTC bit controls protection of the configuration registers. In normal execution mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer. 19.6 ID Locations Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions, or during program/verify. The ID locations can be read when the device is code-protected. 19.7 In-Circuit Serial Programming PIC18F1220/1320 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed (see Table 19-4). 19.8 In-Circuit Debugger When the DEBUG bit in configuration register, CONFIG4L, is programmed to a ‘0’, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB® IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 19-5 shows which resources are required by the background debugger. TABLE 19-5: DEBUGGER RESOURCES To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip, or one of the third party development tool companies (see the note following Section 19.7 “In-Circuit Serial Programming” for more information). Note: The Timer1 oscillator shares the T1OSI and T1OSO pins with the PGD and PGC pins used for programming and debugging. When using the Timer1 oscillator, In-Circuit Serial Programming (ICSP) may not function correctly (high voltage or low voltage), or the In-Circuit Debugger (ICD) may not communicate with the controller. As a result of using either ICSP or ICD, the Timer1 crystal may be damaged. If ICSP or ICD operations are required, the crystal should be disconnected from the circuit (disconnect either lead), or installed after programming. The oscillator loading capacitors may remain in-circuit during ICSP or ICD operation. TABLE 19-4: ICSP/ICD CONNECTIONS Signal Pin Notes PGD RB7/PGD/T1OSI/ P1D/KBI3 Shared with T1OSC – protect crystal PGC RB6/PGC/T1OSO/ T13CKI/P1C/KBI2 Shared with T1OSC – protect crystal MCLR MCLR/VPP/RA5 VDD VDD VSS VSS PGM RB5/PGM/KBI1 Optional – pull RB5 low is LVP enabled I/O pins: RB6, RB7 Stack: 2 levels Program Memory: 512 bytes Data Memory: 10 bytes© 2007 Microchip Technology Inc. DS39605F-page 189 PIC18F1220/1320 19.9 Low-Voltage ICSP Programming The LVP bit in configuration register, CONFIG4L, enables Low-Voltage Programming (LVP). When LVP is enabled, the microcontroller can be programmed without requiring high voltage being applied to the MCLR/VPP/RA5 pin, but the RB5/PGM/KBI1 pin is then dedicated to controlling Program mode entry and is not available as a general purpose I/O pin. LVP is enabled in erased devices. While programming using LVP, VDD is applied to the MCLR/VPP/RA5 pin as in normal execution mode. To enter Programming mode, VDD is applied to the PGM pin. If Low-Voltage Programming mode will not be used, the LVP bit can be cleared and RB5/PGM/KBI1 becomes available as the digital I/O pin RB5. The LVP bit may be set or cleared only when using standard high-voltage programming (VIHH applied to the MCLR/VPP/RA5 pin). Once LVP has been disabled, only the standard highvoltage programming is available and must be used to program the device. Memory that is not code-protected can be erased, using either a Block Erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be erased, a Block Erase is required. If a Block Erase is to be performed when using Low-Voltage Programming, the device must be supplied with VDD of 4.5V to 5.5V. Note 1: High-voltage programming is always available, regardless of the state of the LVP bit or the PGM pin, by applying VIHH to the MCLR pin. 2: When Low-Voltage Programming is enabled, the RB5 pin can no longer be used as a general purpose I/O pin. 3: When LVP is enabled, externally pull the PGM pin to VSS to allow normal program execution.PIC18F1220/1320 DS39605F-page 190 © 2007 Microchip Technology Inc. NOTES:© 2007 Microchip Technology Inc. DS39605F-page 191 PIC18F1220/1320 20.0 INSTRUCTION SET SUMMARY The PIC18 instruction set adds many enhancements to the previous PIC instruction sets, while maintaining an easy migration from these PIC instruction sets. Most instructions are a single program memory word (16 bits), but there are three instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • Byte-oriented operations • Bit-oriented operations • Literal operations • Control operations The PIC18 instruction set summary in Table 20-1 lists byte-oriented, bit-oriented, literal and control operations. Table 20-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. The file register (specified by ‘f’) 2. The destination of the result (specified by ‘d’) 3. The accessed memory (specified by ‘a’) The file register designator ‘f’ specifies which file register is to be used by the instruction. The destination designator ‘d’ specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is placed in the WREG register. If ‘d’ is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. The file register (specified by ‘f’) 2. The bit in the file register (specified by ‘b’) 3. The accessed memory (specified by ‘a’) The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register designator ‘f’ represents the number of the file in which the bit is located. The literal instructions may use some of the following operands: • A literal value to be loaded into a file register (specified by ‘k’) • The desired FSR register to load the literal value into (specified by ‘f’) • No operand required (specified by ‘—’) The control instructions may use some of the following operands: • A program memory address (specified by ‘n’) • The mode of the CALL or RETURN instructions (specified by ‘s’) • The mode of the table read and table write instructions (specified by ‘m’) • No operand required (specified by ‘—’) All instructions are a single word, except for three double-word instructions. These three instructions were made double-word instructions so that all the required information is available in these 32 bits. In the second word, the 4 MSbs are ‘1’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 μs. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 μs. Two-word branch instructions (if true) would take 3 μs. Figure 20-1 shows the general formats that the instructions can have. All examples use the format ‘nnh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. The Instruction Set Summary, shown in Table 20-1, lists the instructions recognized by the Microchip Assembler (MPASMTM). Section 20.2 “Instruction Set” provides a description of each instruction. 20.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified and the result is stored according to either the instruction or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. For example, a “BCF PORTB,1” instruction will read PORTB, clear bit 1 of the data, then write the result back to PORTB. The read operation would have the unintended result that any condition that sets the RBIF flag would be cleared. The R-M-W operation may also copy the level of an input pin to its corresponding output latch.PIC18F1220/1320 DS39605F-page 192 © 2007 Microchip Technology Inc. TABLE 20-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination either the WREG register or the specified register file location. f 8-bit register file address (0x00 to 0xFF). fs 12-bit register file address (0x000 to 0xFFF). This is the source address. fd 12-bit register file address (0x000 to 0xFFF). This is the destination address. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions, or the direct address for call/branch and return instructions. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) u Unused or unchanged. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. TBLPTR 21-bit Table Pointer (points to a program memory location). TABLAT 8-bit Table Latch. TOS Top-of-Stack. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. GIE Global Interrupt Enable bit. WDT Watchdog Timer. TO Time-out bit. PD Power-down bit. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. [ ] Optional. ( ) Contents. → Assigned to. < > Register bit field. ∈ In the set of. italics User defined term (font is Courier).© 2007 Microchip Technology Inc. DS39605F-page 193 PIC18F1220/1320 FIGURE 20-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be WREG register OPCODE d a f (FILE #) d = 1 for result destination to be file register (f) a = 0 to force Access Bank Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) b = 3-bit position of bit in file register (f) Literal operations 15 8 7 0 OPCODE k (literal) k = 8-bit immediate value Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) n = 20-bit immediate value a = 1 for BSR to select bank f = 8-bit file register address a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Control operations Example Instruction ADDWF MYREG, W, B MOVFF MYREG1, MYREG2 BSF MYREG, bit, B MOVLW 0x7F GOTO Label 15 8 7 0 OPCODE n<7:0> (literal) 15 12 11 0 n<19:8> (literal) CALL MYFUNC 15 11 10 0 OPCODE n<10:0> (literal) S = Fast bit BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC SPIC18F1220/1320 DS39605F-page 194 © 2007 Microchip Technology Inc. TABLE 20-1: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word Status Affected Notes MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB SUBWF SUBWFB SWAPF TSTFSZ XORWF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None None None C, DC, Z, OV, N C, Z, N Z, N C, Z, N Z, N None C, DC, Z, OV, N C, DC, Z, OV, N C, DC, Z, OV, N None None Z, N 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, d, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1, 2 1, 2 3, 4 3, 4 1, 2 Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated.© 2007 Microchip Technology Inc. DS39605F-page 195 PIC18F1220/1320 CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL CLRWDT DAW GOTO NOP NOP POP PUSH RCALL RESET RETFIE RETLW RETURN SLEEP n n n n n n n n n n, s — — n — — — — n s k s — Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device Reset Return from interrupt enable Return with literal in WREG Return from Subroutine Go into Standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 None None None None None None None None None None TO, PD C None None None None None None All GIE/GIEH, PEIE/GIEL None None TO, PD 4 TABLE 20-1: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word Status Affected Notes MSb LSb Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated.PIC18F1220/1320 DS39605F-page 196 © 2007 Microchip Technology Inc. LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k f, k k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSRx 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None None None None None C, DC, Z, OV, N Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* TBLRD*+ TBLRD*- TBLRD+* TBLWT* TBLWT*+ TBLWT*- TBLWT+* Table read Table read with post-increment Table read with post-decrement Table read with pre-increment Table write Table write with post-increment Table write with post-decrement Table write with pre-increment 2 2 (5) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 None None None None None None None None TABLE 20-1: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word Status Affected Notes MSb LSb Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated.© 2007 Microchip Technology Inc. DS39605F-page 197 PIC18F1220/1320 20.2 Instruction Set ADDLW ADD literal to W Syntax: [ label ] ADDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: ADDLW 0x15 Before Instruction W = 0x10 After Instruction W = 0x25 ADDWF ADD W to f Syntax: [ label ] ADDWF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) + (f) → dest Status Affected: N, OV, C, DC, Z Encoding: 0010 01da ffff ffff Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected. If ‘a’ is ‘1’, the BSR is used. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: ADDWF REG, W Before Instruction W = 0x17 REG = 0xC2 After Instruction W = 0xD9 REG = 0xC2PIC18F1220/1320 DS39605F-page 198 © 2007 Microchip Technology Inc. ADDWFC ADD W and Carry bit to f Syntax: [ label ] ADDWFC f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) + (f) + (C) → dest Status Affected: N, OV, C, DC, Z Encoding: 0010 00da ffff ffff Description: Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank will be selected. If ‘a’ is ‘1’, the BSR will not be overridden. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: ADDWFC REG, W Before Instruction Carry bit = 1 REG = 0x02 W = 0x4D After Instruction Carry bit = 0 REG = 0x02 W = 0x50 ANDLW AND literal with W Syntax: [ label ] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. k → W Status Affected: N, Z Encoding: 0000 1011 kkkk kkkk Description: The contents of W are AND’ed with the 8-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: ANDLW 0x5F Before Instruction W = 0xA3 After Instruction W = 0x03© 2007 Microchip Technology Inc. DS39605F-page 199 PIC18F1220/1320 ANDWF AND W with f Syntax: [ label ] ANDWF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .AND. (f) → dest Status Affected: N, Z Encoding: 0001 01da ffff ffff Description: The contents of W are AND’ed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected. If ‘a’ is ‘1’, the BSR will not be overridden (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: ANDWF REG, W Before Instruction W = 0x17 REG = 0xC2 After Instruction W = 0x02 REG = 0xC2 BC Branch if Carry Syntax: [ label ] BC n Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0010 nnnn nnnn Description: If the Carry bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BC JUMP Before Instruction PC = address (HERE) After Instruction If Carry = 1; PC = address (JUMP) If Carry = 0; PC = address (HERE + 2)PIC18F1220/1320 DS39605F-page 200 © 2007 Microchip Technology Inc. BCF Bit Clear f Syntax: [ label ] BCF f,b[,a] Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 a ∈ [0,1] Operation: 0 → f Status Affected: None Encoding: 1001 bbba ffff ffff Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: BCF FLAG_REG, 7 Before Instruction FLAG_REG = 0xC7 After Instruction FLAG_REG = 0x47 BN Branch if Negative Syntax: [ label ] BN n Operands: -128 ≤ n ≤ 127 Operation: if Negative bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0110 nnnn nnnn Description: If the Negative bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BN Jump Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2)© 2007 Microchip Technology Inc. DS39605F-page 201 PIC18F1220/1320 BNC Branch if Not Carry Syntax: [ label ] BNC n Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0011 nnnn nnnn Description: If the Carry bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BNC Jump Before Instruction PC = address (HERE) After Instruction If Carry = 0; PC = address (Jump) If Carry = 1; PC = address (HERE + 2) BNN Branch if Not Negative Syntax: [ label ] BNN n Operands: -128 ≤ n ≤ 127 Operation: if Negative bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0111 nnnn nnnn Description: If the Negative bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BNN Jump Before Instruction PC = address (HERE) After Instruction If Negative = 0; PC = address (Jump) If Negative = 1; PC = address (HERE + 2)PIC18F1220/1320 DS39605F-page 202 © 2007 Microchip Technology Inc. BNOV Branch if Not Overflow Syntax: [ label ] BNOV n Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0101 nnnn nnnn Description: If the Overflow bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BNOV Jump Before Instruction PC = address (HERE) After Instruction If Overflow = 0; PC = address (Jump) If Overflow = 1; PC = address (HERE + 2) BNZ Branch if Not Zero Syntax: [ label ] BNZ n Operands: -128 ≤ n ≤ 127 Operation: if Zero bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0001 nnnn nnnn Description: If the Zero bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BNZ Jump Before Instruction PC = address (HERE) After Instruction If Zero = 0; PC = address (Jump) If Zero = 1; PC = address (HERE + 2)© 2007 Microchip Technology Inc. DS39605F-page 203 PIC18F1220/1320 BRA Unconditional Branch Syntax: [ label ] BRA n Operands: -1024 ≤ n ≤ 1023 Operation: (PC) + 2 + 2n → PC Status Affected: None Encoding: 1101 0nnn nnnn nnnn Description: Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation Example: HERE BRA Jump Before Instruction PC = address (HERE) After Instruction PC = address (Jump) BSF Bit Set f Syntax: [ label ] BSF f,b[,a] Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 a ∈ [0,1] Operation: 1 → f Status Affected: None Encoding: 1000 bbba ffff ffff Description: Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: BSF FLAG_REG, 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8APIC18F1220/1320 DS39605F-page 204 © 2007 Microchip Technology Inc. BTFSC Bit Test File, Skip if Clear Syntax: [ label ] BTFSC f,b[,a] Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 a ∈ [0,1] Operation: skip if (f) = 0 Status Affected: None Encoding: 1011 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE FALSE TRUE BTFSC : : FLAG, 1 Before Instruction PC = address (HERE) After Instruction If FLAG<1> = 0; PC = address (TRUE) If FLAG<1> = 1; PC = address (FALSE) BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSS f,b[,a] Operands: 0 ≤ f ≤ 255 0 ≤ b < 7 a ∈ [0,1] Operation: skip if (f) = 1 Status Affected: None Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE FALSE TRUE BTFSS : : FLAG, 1 Before Instruction PC = address (HERE) After Instruction If FLAG<1> = 0; PC = address (FALSE) If FLAG<1> = 1; PC = address (TRUE)© 2007 Microchip Technology Inc. DS39605F-page 205 PIC18F1220/1320 BTG Bit Toggle f Syntax: [ label ] BTG f,b[,a] Operands: 0 ≤ f ≤ 255 0 ≤ b < 7 a ∈ [0,1] Operation: (f) → f Status Affected: None Encoding: 0111 bbba ffff ffff Description: Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: BTG PORTB, 4 Before Instruction: PORTB = 0111 0101 [0x75] After Instruction: PORTB = 0110 0101 [0x65] BOV Branch if Overflow Syntax: [ label ] BOV n Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0100 nnnn nnnn Description: If the Overflow bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BOV JUMP Before Instruction PC = address (HERE) After Instruction If Overflow = 1; PC = address (JUMP) If Overflow = 0; PC = address (HERE + 2)PIC18F1220/1320 DS39605F-page 206 © 2007 Microchip Technology Inc. BZ Branch if Zero Syntax: [ label ] BZ n Operands: -128 ≤ n ≤ 127 Operation: if Zero bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0000 nnnn nnnn Description: If the Zero bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BZ Jump Before Instruction PC = address (HERE) After Instruction If Zero = 1; PC = address (Jump) If Zero = 0; PC = address (HERE + 2) CALL Subroutine Call Syntax: [ label ] CALL k [,s] Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: (PC) + 4 → TOS, k → PC<20:1>, if s = 1 (W) → WS, (Status) → STATUSS, (BSR) → BSRS Status Affected: None Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8 Description: Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If ‘s’ = 1, the W, Status and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no update occurs (default). Then, the 20-bit value ‘k’ is loaded into PC<20:1>. CALL is a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’<7:0>, Push PC to stack Read literal ‘k’<19:8>, Write to PC No operation No operation No operation No operation Example: HERE CALL THERE, FAST Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS = Status© 2007 Microchip Technology Inc. DS39605F-page 207 PIC18F1220/1320 CLRF Clear f Syntax: [ label ] CLRF f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: 000h → f 1 → Z Status Affected: Z Encoding: 0110 101a ffff ffff Description: Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: CLRF FLAG_REG Before Instruction FLAG_REG = 0x5A After Instruction FLAG_REG = 0x00 CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h → WDT, 000h → WDT postscaler, 1 → TO, 1 → PD Status Affected: TO, PD Encoding: 0000 0000 0000 0100 Description: CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data No operation Example: CLRWDT Before Instruction WDT Counter = ? After Instruction WDT Counter = 0x00 WDT Postscaler = 0 TO = 1 PD = 1PIC18F1220/1320 DS39605F-page 208 © 2007 Microchip Technology Inc. COMF Complement f Syntax: [ label ] COMF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest Status Affected: N, Z Encoding: 0001 11da ffff ffff Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: COMF REG, W Before Instruction REG = 0x13 After Instruction REG = 0x13 W = 0xEC CPFSEQ Compare f with W, skip if f = W Syntax: [ label ] CPFSEQ f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None Encoding: 0110 001a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If ‘f’ = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE CPFSEQ REG NEQUAL : EQUAL : Before Instruction PC Address = HERE W =? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG ≠ W; PC = Address (NEQUAL)© 2007 Microchip Technology Inc. DS39605F-page 209 PIC18F1220/1320 CPFSGT Compare f with W, skip if f > W Syntax: [ label ] CPFSGT f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) > (W) (unsigned comparison) Status Affected: None Encoding: 0110 010a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE CPFSGT REG NGREATER : GREATER : Before Instruction PC = Address (HERE) W = ? After Instruction If REG > W; PC = Address (GREATER) If REG ≤ W; PC = Address (NGREATER) CPFSLT Compare f with W, skip if f < W Syntax: [ label ] CPFSLT f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected. If ‘a’ is ‘1’, the BSR will not be overridden (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE CPFSLT REG NLESS : LESS : Before Instruction PC = Address (HERE) W = ? After Instruction If REG < W; PC = Address (LESS) If REG ≥ W; PC = Address (NLESS)PIC18F1220/1320 DS39605F-page 210 © 2007 Microchip Technology Inc. DAW Decimal Adjust W Register Syntax: [ label ] DAW Operands: None Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 → W<3:0>; else (W<3:0>) → W<3:0>; If [W<7:4> > 9] or [C = 1] then (W<7:4>) + 6 → W<7:4>; else (W<7:4>) → W<7:4>; Status Affected: C, DC Encoding: 0000 0000 0000 0111 Description: DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. The Carry bit may be set by DAW regardless of its setting prior to the DAW instruction. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register W Process Data Write W Example 1: DAW Before Instruction W = 0xA5 C =0 DC = 0 After Instruction W = 0x05 C =1 DC = 0 Example 2: Before Instruction W = 0xCE C =0 DC = 0 After Instruction W = 0x34 C =1 DC = 0 DECF Decrement f Syntax: [ label ] DECF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 0000 01da ffff ffff Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: DECF CNT Before Instruction CNT = 0x01 Z =0 After Instruction CNT = 0x00 Z =1© 2007 Microchip Technology Inc. DS39605F-page 211 PIC18F1220/1320 DECFSZ Decrement f, skip if 0 Syntax: [ label ] DECFSZ f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Status Affected: None Encoding: 0010 11da ffff ffff Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE DECFSZ CNT GOTO LOOP CONTINUE Before Instruction PC = Address (HERE) After Instruction CNT = CNT – 1 If CNT = 0; PC = Address (CONTINUE) If CNT ≠ 0; PC = Address (HERE + 2) DCFSNZ Decrement f, skip if not 0 Syntax: [ label ] DCFSNZ f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is not ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a twocycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE DCFSNZ TEMP ZERO : NZERO : Before Instruction TEMP = ? After Instruction TEMP = TEMP – 1, If TEMP = 0; PC = Address (ZERO) If TEMP ≠ 0; PC = Address (NZERO)PIC18F1220/1320 DS39605F-page 212 © 2007 Microchip Technology Inc. GOTO Unconditional Branch Syntax: [ label ] GOTO k Operands: 0 ≤ k ≤ 1048575 Operation: k → PC<20:1> Status Affected: None Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within the entire 2-Mbyte memory range. The 20-bit value ‘k’ is loaded into PC<20:1>. GOTO is always a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’<7:0>, No operation Read literal ‘k’<19:8>, Write to PC No operation No operation No operation No operation Example: GOTO THERE After Instruction PC = Address (THERE) INCF Increment f Syntax: [ label ] INCF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 0010 10da ffff ffff Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: INCF CNT Before Instruction CNT = 0xFF Z =0 C =? DC = ? After Instruction CNT = 0x00 Z =1 C =1 DC = 1© 2007 Microchip Technology Inc. DS39605F-page 213 PIC18F1220/1320 INCFSZ Increment f, skip if 0 Syntax: [ label ] INCFSZ f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, skip if result = 0 Status Affected: None Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE INCFSZ CNT NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction CNT = CNT + 1 If CNT = 0; PC = Address (ZERO) If CNT ≠ 0; PC = Address (NZERO) INFSNZ Increment f, skip if not 0 Syntax: [ label ] INFSNZ f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Encoding: 0100 10da ffff ffff Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is not ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE INFSNZ REG ZERO NZERO Before Instruction PC = Address (HERE) After Instruction REG = REG + 1 If REG ≠ 0; PC = Address (NZERO) If REG = 0; PC = Address (ZERO)PIC18F1220/1320 DS39605F-page 214 © 2007 Microchip Technology Inc. IORLW Inclusive OR literal with W Syntax: [ label ] IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → W Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are OR’ed with the eight-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: IORLW 0x35 Before Instruction W = 0x9A After Instruction W = 0xBF IORWF Inclusive OR W with f Syntax: [ label ] IORWF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .OR. (f) → dest Status Affected: N, Z Encoding: 0001 00da ffff ffff Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: IORWF RESULT, W Before Instruction RESULT = 0x13 W = 0x91 After Instruction RESULT = 0x13 W = 0x93© 2007 Microchip Technology Inc. DS39605F-page 215 PIC18F1220/1320 LFSR Load FSR Syntax: [ label ] LFSR f,k Operands: 0 ≤ f ≤ 2 0 ≤ k ≤ 4095 Operation: k → FSRf Status Affected: None Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ MSB Process Data Write literal ‘k’ MSB to FSRfH Decode Read literal ‘k’ LSB Process Data Write literal ‘k’ to FSRfL Example: LFSR 2, 0x3AB After Instruction FSR2H = 0x03 FSR2L = 0xAB MOVF Move f Syntax: [ label ] MOVF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: f → dest Status Affected: N, Z Encoding: 0101 00da ffff ffff Description: The contents of register ‘f’ are moved to a destination dependent upon the status of ‘d’. If ‘d’ is ‘f’, the result is placed in W. If ‘d’ is ‘f’, the result is placed back in register ‘f’ (default). Location ‘f’ can be anywhere in the 256-byte bank. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write W Example: MOVF REG, W Before Instruction REG = 0x22 W = 0xFF After Instruction REG = 0x22 W = 0x22PIC18F1220/1320 DS39605F-page 216 © 2007 Microchip Technology Inc. MOVFF Move f to f Syntax: [ label ] MOVFF fs,fd Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operation: (fs) → fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff ffffs ffffd Description: The contents of source register ‘fs’ are moved to destination register ‘fd’. Location of source ‘fs’ can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination ‘fd’ can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. The MOVFF instruction should not be used to modify interrupt settings while any interrupt is enabled (see page 73). Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ (src) Process Data No operation Decode No operation No dummy read No operation Write register ‘f’ (dest) Example: MOVFF REG1, REG2 Before Instruction REG1 = 0x33 REG2 = 0x11 After Instruction REG1 = 0x33, REG2 = 0x33 MOVLB Move literal to low nibble in BSR Syntax: [ label ] MOVLB k Operands: 0 ≤ k ≤ 255 Operation: k → BSR Status Affected: None Encoding: 0000 0001 kkkk kkkk Description: The 8-bit literal ‘k’ is loaded into the Bank Select Register (BSR). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write literal ‘k’ to BSR Example: MOVLB 5 Before Instruction BSR register = 0x02 After Instruction BSR register = 0x05© 2007 Microchip Technology Inc. DS39605F-page 217 PIC18F1220/1320 MOVLW Move literal to W Syntax: [ label ] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → W Status Affected: None Encoding: 0000 1110 kkkk kkkk Description: The eight-bit literal ‘k’ is loaded into W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: MOVLW 0x5A After Instruction W = 0x5A MOVWF Move W to f Syntax: [ label ] MOVWF f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) → f Status Affected: None Encoding: 0110 111a ffff ffff Description: Move data from W to register ‘f’. Location ‘f’ can be anywhere in the 256-byte bank. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: MOVWF REG Before Instruction W = 0x4F REG = 0xFF After Instruction W = 0x4F REG = 0x4FPIC18F1220/1320 DS39605F-page 218 © 2007 Microchip Technology Inc. MULLW Multiply Literal with W Syntax: [ label ] MULLW k Operands: 0 ≤ k ≤ 255 Operation: (W) x k → PRODH:PRODL Status Affected: None Encoding: 0000 1101 kkkk kkkk Description: An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write registers PRODH: PRODL Example: MULLW 0xC4 Before Instruction W = 0xE2 PRODH = ? PRODL = ? After Instruction W = 0xE2 PRODH = 0xAD PRODL = 0x08 MULWF Multiply W with f Syntax: [ label ] MULWF f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the register file location ‘f’. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and ‘f’ are unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible, but not detected. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write registers PRODH: PRODL Example: MULWF REG Before Instruction W = 0xC4 REG = 0xB5 PRODH = ? PRODL = ? After Instruction W = 0xC4 REG = 0xB5 PRODH = 0x8A PRODL = 0x94© 2007 Microchip Technology Inc. DS39605F-page 219 PIC18F1220/1320 NEGF Negate f Syntax: [ label ] NEGF f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) + 1 → f Status Affected: N, OV, C, DC, Z Encoding: 0110 110a ffff ffff Description: Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [0x3A] After Instruction REG = 1100 0110 [0xC6] NOP No Operation Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None Encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx Description: No operation. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Example: None.PIC18F1220/1320 DS39605F-page 220 © 2007 Microchip Technology Inc. POP Pop Top of Return Stack Syntax: [ label ] POP Operands: None Operation: (TOS) → bit bucket Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Pop TOS value No operation Example: POP GOTO NEW Before Instruction TOS = 0x0031A2 Stack (1 level down) = 0x014332 After Instruction TOS = 0x014332 PC = NEW PUSH Push Top of Return Stack Syntax: [ label ] PUSH Operands: None Operation: (PC + 2) → TOS Status Affected: None Encoding: 0000 0000 0000 0101 Description: The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Push PC + 2 onto return stack No operation No operation Example: PUSH Before Instruction TOS = 0x00345A PC = 0x000124 After Instruction PC = 0x000126 TOS = 0x000126 Stack (1 level down) = 0x00345A© 2007 Microchip Technology Inc. DS39605F-page 221 PIC18F1220/1320 RCALL Relative Call Syntax: [ label ] RCALL n Operands: -1024 ≤ n ≤ 1023 Operation: (PC) + 2 → TOS, (PC) + 2 + 2n → PC Status Affected: None Encoding: 1101 1nnn nnnn nnnn Description: Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Push PC to stack Process Data Write to PC No operation No operation No operation No operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2) RESET Reset Syntax: [ label ] RESET Operands: None Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: All Encoding: 0000 0000 1111 1111 Description: This instruction provides a way to execute a MCLR Reset in software. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Start Reset No operation No operation Example: RESET After Instruction Registers = Reset Value Flags* = Reset ValuePIC18F1220/1320 DS39605F-page 222 © 2007 Microchip Technology Inc. RETFIE Return from Interrupt Syntax: [ label ] RETFIE [s] Operands: s ∈ [0,1] Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL, if s = 1 (WS) → W, (STATUSS) → Status, (BSRS) → BSR, PCLATU, PCLATH are unchanged. Status Affected: GIE/GIEH, PEIE/GIEL. Encoding: 0000 0000 0001 000s Description: Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If ‘s’ = 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, Status and BSR. If ‘s’ = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation Pop PC from stack Set GIEH or GIEL No operation No operation No operation No operation Example: RETFIE 1 After Interrupt PC = TOS W = WS BSR = BSRS Status = STATUSS GIE/GIEH, PEIE/GIEL = 1 RETLW Return Literal to W Syntax: [ label ] RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → W, (TOS) → PC, PCLATU, PCLATH are unchanged Status Affected: None Encoding: 0000 1100 kkkk kkkk Description: W is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Pop PC from stack, Write to W No operation No operation No operation No operation Example: CALL TABLE ; W contains table ; offset value ; W now has ; table value : TABLE ADDWF PCL ; W = offset RETLW k0 ; Begin table RETLW k1 ; : : RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of kn© 2007 Microchip Technology Inc. DS39605F-page 223 PIC18F1220/1320 RETURN Return from Subroutine Syntax: [ label ] RETURN [s] Operands: s ∈ [0,1] Operation: (TOS) → PC, if s = 1 (WS) → W, (STATUSS) → Status, (BSRS) → BSR, PCLATU, PCLATH are unchanged Status Affected: None Encoding: 0000 0000 0001 001s Description: Return from subroutine. The stack is popped and the top of the stack is loaded into the program counter. If ‘s’= 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, Status and BSR. If ‘s’ = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data Pop PC from stack No operation No operation No operation No operation Example: RETURN After Interrupt PC = TOS RLCF Rotate Left f through Carry Syntax: [ label ] RLCF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z Encoding: 0011 01da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: RLCF REG, W Before Instruction REG = 1110 0110 C =0 After Instruction REG = 1110 0110 W = 1100 1100 C =1 C register fPIC18F1220/1320 DS39605F-page 224 © 2007 Microchip Technology Inc. RLNCF Rotate Left f (no carry) Syntax: [ label ] RLNCF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → dest<0> Status Affected: N, Z Encoding: 0100 01da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: RLNCF REG Before Instruction REG = 1010 1011 After Instruction REG = 0101 0111 register f RRCF Rotate Right f through Carry Syntax: [ label ] RRCF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: RRCF REG, W Before Instruction REG = 1110 0110 C =0 After Instruction REG = 1110 0110 W = 0111 0011 C =0 C register f© 2007 Microchip Technology Inc. DS39605F-page 225 PIC18F1220/1320 RRNCF Rotate Right f (no carry) Syntax: [ label ] RRNCF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<0>) → dest<7> Status Affected: N, Z Encoding: 0100 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, W Before Instruction W =? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 register f SETF Set f Syntax: [ label ] SETF f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: FFh → f Status Affected: None Encoding: 0110 100a ffff ffff Description: The contents of the specified register are set to FFh. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: SETF REG Before Instruction REG = 0x5A After Instruction REG = 0xFFPIC18F1220/1320 DS39605F-page 226 © 2007 Microchip Technology Inc. SLEEP Enter Sleep mode Syntax: [ label ] SLEEP Operands: None Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD Status Affected: TO, PD Encoding: 0000 0000 0000 0011 Description: The Power-down status bit (PD) is cleared. The Time-out status bit (TO) is set. The Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data Go to Sleep Example: SLEEP Before Instruction TO = ? PD = ? After Instruction TO = 1 † PD = 0 † If WDT causes wake-up, this bit is cleared. SUBFWB Subtract f from W with borrow Syntax: [ label ] SUBFWB f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z Encoding: 0101 01da ffff ffff Description: Subtract register ‘f’ and Carry flag (borrow) from W (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example 1: SUBFWB REG Before Instruction REG = 0x03 W = 0x02 C = 0x01 After Instruction REG = 0xFF W = 0x02 C = 0x00 Z = 0x00 N = 0x01 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W =5 C =1 After Instruction REG = 2 W =3 C =1 Z =0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W =2 C =0 After Instruction REG = 0 W =2 C =1 Z = 1 ; result is zero N =0© 2007 Microchip Technology Inc. DS39605F-page 227 PIC18F1220/1320 SUBLW Subtract W from literal Syntax: [ label ] SUBLW k Operands: 0 ≤ k ≤ 255 Operation: k – (W) → W Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example 1: SUBLW 0x02 Before Instruction W =1 C =? After Instruction W =1 C = 1 ; result is positive Z =0 N =0 Example 2: SUBLW 0x02 Before Instruction W =2 C =? After Instruction W =0 C = 1 ; result is zero Z =1 N =0 Example 3: SUBLW 0x02 Before Instruction W =3 C =? After Instruction W = FF ; (2’s complement) C = 0 ; result is negative Z =0 N =1 SUBWF Subtract W from f Syntax: [ label ] SUBWF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: 0101 11da ffff ffff Description: Subtract W from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example 1: SUBWF REG Before Instruction REG = 3 W =2 C =? After Instruction REG = 1 W =2 C = 1 ; result is positive Z =0 N =0 Example 2: SUBWF REG, W Before Instruction REG = 2 W =2 C =? After Instruction REG = 2 W =0 C = 1 ; result is zero Z =1 N =0 Example 3: SUBWF REG Before Instruction REG = 0x01 W = 0x02 C =? After Instruction REG = 0xFFh ;(2’s complement) W = 0x02 C = 0x00 ;result is negative Z = 0x00 N = 0x01PIC18F1220/1320 DS39605F-page 228 © 2007 Microchip Technology Inc. SUBWFB Subtract W from f with Borrow Syntax: [ label ] SUBWFB f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Status Affected: N, OV, C, DC, Z Encoding: 0101 10da ffff ffff Description: Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example 1: SUBWFB REG, 1, 0 Before Instruction REG = 0x19 (0001 1001) W = 0x0D (0000 1101) C = 0x01 After Instruction REG = 0x0C (0000 1011) W = 0x0D (0000 1101) C = 0x01 Z = 0x00 N = 0x00 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 0x1B (0001 1011) W = 0x1A (0001 1010) C = 0x00 After Instruction REG = 0x1B (0001 1011) W = 0x00 C = 0x01 Z = 0x01 ; result is zero N = 0x00 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 0x03 (0000 0011) W = 0x0E (0000 1101) C = 0x01 After Instruction REG = 0xF5 (1111 0100) ; [2’s comp] W = 0x0E (0000 1101) C = 0x00 Z = 0x00 N = 0x01 ; result is negative SWAPF Swap f Syntax: [ label ] SWAPF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: None Encoding: 0011 10da ffff ffff Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: SWAPF REG Before Instruction REG = 0x53 After Instruction REG = 0x35© 2007 Microchip Technology Inc. DS39605F-page 229 PIC18F1220/1320 TBLRD Table Read Syntax: [ label ] TBLRD ( *; *+; *-; +*) Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT; TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT; (TBLPTR) + 1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT; (TBLPTR) – 1 → TBLPTR; if TBLRD +*, (TBLPTR) + 1 → TBLPTR; (Prog Mem (TBLPTR)) → TABLAT; Status Affected: None Encoding: 0000 0000 0000 10nn nn = 0* = 1*+ = 2*- = 3+* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read Program Memory) No operation No operation (Write TABLAT) TBLRD Table Read (Continued) Example 1: TBLRD *+ ; Before Instruction TABLAT = 0x55 TBLPTR = 0x00A356 MEMORY(0x00A356) = 0x34 After Instruction TABLAT = 0x34 TBLPTR = 0x00A357 Example 2: TBLRD +* ; Before Instruction TABLAT = 0xAA TBLPTR = 0x01A357 MEMORY(0x01A357) = 0x12 MEMORY(0x01A358) = 0x34 After Instruction TABLAT = 0x34 TBLPTR = 0x01A358PIC18F1220/1320 DS39605F-page 230 © 2007 Microchip Technology Inc. TBLWT Table Write Syntax: [ label ] TBLWT ( *; *+; *-; +*) Operands: None Operation: if TBLWT*, (TABLAT) → Holding Register; TBLPTR – No Change; if TBLWT*+, (TABLAT) → Holding Register; (TBLPTR) + 1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register; (TBLPTR) – 1 → TBLPTR; if TBLWT+*, (TBLPTR) + 1 → TBLPTR; (TABLAT) → Holding Register; Status Affected: None Encoding: 0000 0000 0000 11nn nn = 0* = 1*+ = 2*- = 3+* Description: This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 “Flash Program Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0:Least Significant Byte of Program Memory Word TBLPTR[0] = 1:Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment TBLWT Table Write (Continued) Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read TABLAT) No operation No operation (Write to Holding Register) Example 1: TBLWT *+; Before Instruction TABLAT = 0x55 TBLPTR = 0x00A356 HOLDING REGISTER (0x00A356) = 0xFF After Instructions (table write completion) TABLAT = 0x55 TBLPTR = 0x00A357 HOLDING REGISTER (0x00A356) = 0x55 Example 2: TBLWT +*; Before Instruction TABLAT = 0x34 TBLPTR = 0x01389A HOLDING REGISTER (0x01389A) = 0xFF HOLDING REGISTER (0x01389B) = 0xFF After Instruction (table write completion) TABLAT = 0x34 TBLPTR = 0x01389B HOLDING REGISTER (0x01389A) = 0xFF HOLDING REGISTER (0x01389B) = 0x34© 2007 Microchip Technology Inc. DS39605F-page 231 PIC18F1220/1320 TSTFSZ Test f, skip if 0 Syntax: [ label ] TSTFSZ f [,a] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: skip if f = 0 Status Affected: None Encoding: 0110 011a ffff ffff Description: If ‘f’ = 0, the next instruction, fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE TSTFSZ CNT NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 0x00, PC = Address (ZERO) If CNT ≠ 0x00, PC = Address (NZERO) XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → W Status Affected: N, Z Encoding: 0000 1010 kkkk kkkk Description: The contents of W are XOR’ed with the 8-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data Write to W Example: XORLW 0xAF Before Instruction W = 0xB5 After Instruction W = 0x1APIC18F1220/1320 DS39605F-page 232 © 2007 Microchip Technology Inc. XORWF Exclusive OR W with f Syntax: [ label ] XORWF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write to destination Example: XORWF REG Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5© 2007 Microchip Technology Inc. DS39605F-page 233 PIC18F1220/1320 21.0 DEVELOPMENT SUPPORT The PIC® microcontrollers are supported with a full range of hardware and software development tools: • Integrated Development Environment - MPLAB® IDE Software • Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debugger - MPLAB ICD 2 • Device Programmers - PICSTART® Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits 21.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Visual device initializer for easy register initialization • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.PIC18F1220/1320 DS39605F-page 234 © 2007 Microchip Technology Inc. 21.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process 21.3 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip’s PIC18 family of microcontrollers and the dsPIC30, dsPIC33 and PIC24 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 21.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 21.5 MPLAB ASM30 Assembler, Linker and Librarian MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • Support for the entire dsPIC30F instruction set • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility 21.6 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. © 2007 Microchip Technology Inc. DS39605F-page 235 PIC18F1220/1320 21.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were chosen to best make these features available in a simple, unified application. 21.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC® and MCU devices. It debugs and programs PIC® and dsPIC® Flash microcontrollers with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 21.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. 21.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.PIC18F1220/1320 DS39605F-page 236 © 2007 Microchip Technology Inc. 21.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. 21.12 PICkit 2 Development Programmer The PICkit™ 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip’s baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH’s PICC™ Lite C compiler, and is designed to help get up to speed quickly using PIC® microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip’s powerful, mid-range Flash memory family of microcontrollers. 21.13 Demonstration, Development and Evaluation Boards A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart® battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits.© 2007 Microchip Technology Inc. DS39605F-page 237 PIC18F1220/1320 22.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.PIC18F1220/1320 DS39605F-page 238 © 2007 Microchip Technology Inc. FIGURE 22-1: PIC18F1220/1320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) FIGURE 22-2: PIC18LF1220/1320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) Frequency Voltage 6.0V 5.5V 4.5V 4.0V 2.0V 40 MHz 5.0V 3.5V 3.0V 2.5V PIC18F1X20 4.2V Frequency Voltage 6.0V 5.5V 4.5V 4.0V 2.0V 40 MHz 5.0V 3.5V 3.0V 2.5V FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. 4 MHz 4.2V PIC18LF1X20© 2007 Microchip Technology Inc. DS39605F-page 239 PIC18F1220/1320 FIGURE 22-3: PIC18F1220/1320 VOLTAGE-FREQUENCY GRAPH (EXTENDED) Frequency Voltage 6.0V 5.5V 4.5V 4.0V 2.0V 25 MHz 5.0V 3.5V 3.0V 2.5V PIC18F1X20-E 4.2VPIC18F1220/1320 DS39605F-page 240 © 2007 Microchip Technology Inc. 22.1 DC Characteristics: Supply Voltage PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Symbol Characteristic Min Typ Max Units Conditions VDD Supply Voltage D001 PIC18LF1220/1320 2.0 — 5.5 V HS, XT, RC and LP Oscillator mode PIC18F1220/1320 4.2 — 5.5 V D002 VDR RAM Data Retention Voltage(1) 1.5 — — V D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal — — 0.7 V See Section 4.1 “Power-on Reset (POR)” for details. D004 SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 — — V/ms See Section 4.1 “Power-on Reset (POR)” for details. VBOR Brown-out Reset Voltage D005D PIC18LF1220/1320 Industrial Low Voltage (-10°C to +85°C) BORV1:BORV0 = 11 N/A N/A N/A V Reserved BORV1:BORV0 = 10 2.50 2.72 2.94 V BORV1:BORV0 = 01 3.88 4.22 4.56 V (Note 2) BORV1:BORV0 = 00 4.18 4.54 4.90 V (Note 2) D005F PIC18LF1220/1320 Industrial Low Voltage (-40°C to -10°C) BORV1:BORV0 = 11 N/A N/A N/A V Reserved BORV1:BORV0 = 10 2.34 2.72 3.10 V BORV1:BORV0 = 01 3.63 4.22 4.81 V (Note 2) BORV1:BORV0 = 00 3.90 4.54 5.18 V (Note 2) D005G PIC18F1220/1320 Industrial (-10°C to +85°C) BORV1:BORV0 = 1x N/A N/A N/A V Reserved BORV1:BORV0 = 01 3.88 4.22 4.56 V (Note 2) BORV1:BORV0 = 00 4.18 4.54 4.90 V (Note 2) D005H PIC18F1220/1320 Industrial (-40°C to -10°C) BORV1:BORV0 = 1x N/A N/A N/A V Reserved BORV1:BORV0 = 01 N/A N/A N/A V Reserved BORV1:BORV0 = 00 3.90 4.54 5.18 V (Note 2) D005J PIC18F1220/1320 Extended (-10°C to +85°C) BORV1:BORV0 = 1x N/A N/A N/A V Reserved BORV1:BORV0 = 01 3.88 4.22 4.56 V (Note 3) BORV1:BORV0 = 00 4.18 4.54 4.90 V (Note 3) D005K PIC18F1220/1320 Extended (-40°C to -10°C, +85°C to +125°C) BORV1:BORV0 = 1x N/A N/A N/A V Reserved BORV1:BORV0 = 01 N/A N/A N/A V Reserved BORV1:BORV0 = 00 3.90 4.54 5.18 V (Note 3) Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: When BOR is on and BORV<1:0> = 0x, the device will operate correctly at 40 MHz for any VDD at which the BOR allows execution (low-voltage and industrial devices only). 3: When BOR is on and BORV<1:0> = 0x, the device will operate correctly at 25 MHz for any VDD at which the BOR allows execution (extended devices only).© 2007 Microchip Technology Inc. DS39605F-page 241 PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Typ Max Units Conditions Power-Down Current (IPD) (1) PIC18LF1220/1320 0.1 0.5 μA -40°C VDD = 2.0V, (Sleep mode) 0.1 0.5 μA +25°C 0.2 1.9 μA +85°C PIC18LF1220/1320 0.1 0.5 μA -40°C VDD = 3.0V, (Sleep mode) 0.1 0.5 μA + 25°C 0.3 1.9 μA +85°C All devices 0.1 2.0 μA -40°C VDD = 5.0V, (Sleep mode) 0.1 2.0 μA +25°C 0.4 6.5 μA +85°C Extended devices 11.2 50 μA +125°C Supply Current (IDD) (2,3) PIC18LF1220/1320 8 40 μA -40°C FOSC = 31 kHz (RC_RUN mode, Internal oscillator source) 9 40 μA +25°C VDD = 2.0V 11 40 μA +85°C PIC18LF1220/1320 25 68 μA -40°C 25 68 μA +25°C VDD = 3.0V 20 68 μA +85°C All devices 55 80 μA -40°C VDD = 5.0V 55 80 μA +25°C 50 80 μA +85°C Extended devices 50 80 μA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.PIC18F1220/1320 DS39605F-page 242 © 2007 Microchip Technology Inc. Supply Current (IDD) (2,3) PIC18LF1220/1320 140 220 μA -40°C FOSC = 1 MHz (RC_RUN mode, Internal oscillator source) 145 220 μA +25°C VDD = 2.0V 155 220 μA +85°C PIC18LF1220/1320 215 330 μA -40°C 225 330 μA +25°C VDD = 3.0V 235 330 μA +85°C All devices 385 550 μA -40°C VDD = 5.0V 390 550 μA +25°C 405 550 μA +85°C Extended devices 410 650 μA +125°C PIC18LF1220/1320 410 600 μA -40°C FOSC = 4 MHz (RC_RUN mode, Internal oscillator source) 425 600 μA +25°C VDD = 2.0V 435 600 μA +85°C PIC18LF1220/1320 650 900 μA -40°C 670 900 μA +25°C VDD = 3.0V 680 900 μA +85°C All devices 1.2 1.8 mA -40°C VDD = 5.0V 1.2 1.8 mA +25°C 1.2 1.8 mA +85°C Extended devices 1.2 1.8 mA +125°C 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.© 2007 Microchip Technology Inc. DS39605F-page 243 PIC18F1220/1320 Supply Current (IDD) (2,3) PIC18LF1220/1320 4.7 8 μA -40°C FOSC = 31 kHz (RC_IDLE mode, Internal oscillator source) 5.0 8 μA +25°C VDD = 2.0V 5.8 11 μA +85°C PIC18LF1220/1320 7.0 11 μA -40°C 7.8 11 μA +25°C VDD = 3.0V 8.7 15 μA +85°C All devices 12 16 μA -40°C VDD = 5.0V 14 16 μA +25°C 14 22 μA +85°C Extended devices 25 75 μA +125°C PIC18LF1220/1320 75 150 μA -40°C FOSC = 1 MHz (RC_IDLE mode, Internal oscillator source) 85 150 μA +25°C VDD = 2.0V 95 150 μA +85°C PIC18LF1220/1320 110 180 μA -40°C 125 180 μA +25°C VDD = 3.0V 135 180 μA +85°C All devices 180 380 μA -40°C VDD = 5.0V 195 380 μA +25°C 200 380 μA +85°C Extended devices 350 435 μA +125°C 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.PIC18F1220/1320 DS39605F-page 244 © 2007 Microchip Technology Inc. Supply Current (IDD) (2,3) PIC18LF1220/1320 140 275 μA -40°C FOSC = 4 MHz (RC_IDLE mode, Internal oscillator source) 140 275 μA +25°C VDD = 2.0V 150 275 μA +85°C PIC18LF1220/1320 220 375 μA -40°C 220 375 μA +25°C VDD = 3.0V 220 375 μA +85°C All devices 390 800 μA -40°C VDD = 5.0V 400 800 μA +25°C 380 800 μA +85°C Extended devices 410 800 μA +125°C PIC18LF1220/1320 150 250 μA -40°C FOSC = 1 MHZ (PRI_RUN mode, EC oscillator) 150 250 μA +25°C VDD = 2.0V 160 250 μA +85°C PIC18LF1220/1320 340 350 μA -40°C 300 350 μA +25°C VDD = 3.0V 280 350 μA +85°C All devices 0.72 1.0 mA -40°C VDD = 5.0V 0.63 1.0 mA +25°C 0.58 1.0 mA +85°C Extended devices 0.53 1.0 mA +125°C 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.© 2007 Microchip Technology Inc. DS39605F-page 245 PIC18F1220/1320 Supply Current (IDD) (2,3) PIC18LF1220/1320 415 600 μA -40°C FOSC = 4 MHz (PRI_RUN mode, EC oscillator) 425 600 μA +25°C VDD = 2.0V 435 600 μA +85°C PIC18LF1220/1320 0.87 1.0 mA -40°C 0.75 1.0 mA +25°C VDD = 3.0V 0.75 1.0 mA +85°C All devices 1.6 2.0 mA -40°C VDD = 5.0V 1.6 2.0 mA +25°C 1.5 2.0 mA +85°C Extended devices 1.5 2.0 mA +125°C Extended devices 6.3 9.0 mA +125°C VDD = 4.2V FOSC = 25 MHz (PRI_RUN mode, EC oscillator) 9.7 10.0 mA +125°C VDD = 5.0V All devices 9.4 12 mA -40°C FOSC = 40 MHZ (PRI_RUN mode, EC oscillator) 9.5 12 mA +25°C VDD = 4.2V 9.6 12 mA +85°C All devices 11.9 15 mA -40°C 12.1 15 mA +25°C VDD = 5.0V 12.2 15 mA +85°C 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.PIC18F1220/1320 DS39605F-page 246 © 2007 Microchip Technology Inc. Supply Current (IDD) (2,3) PIC18LF1220/1320 35 50 μA -40°C FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) 35 50 μA +25°C VDD = 2.0V 35 60 μA +85°C PIC18LF1220/1320 55 80 μA -40°C 50 80 μA +25°C VDD = 3.0V 60 100 μA +85°C All devices 105 150 μA -40°C VDD = 5.0V 110 150 μA +25°C 115 150 μA +85°C Extended devices 125 300 μA +125°C PIC18LF1220/1320 135 180 μA -40°C FOSC = 4 MHz (PRI_IDLE mode, EC oscillator) 140 180 μA +25°C VDD = 2.0V 140 180 μA +85°C PIC18LF1220/1320 215 280 μA -40°C 225 280 μA +25°C VDD = 3.0V 230 280 μA +85°C All devices 410 525 μA -40°C VDD = 5.0V 420 525 μA +25°C 430 525 μA +85°C Extended devices 450 800 μA +125°C Extended devices 2.2 3.0 mA +125°C VDD = 4.2V FOSC = 25 MHz (PRI_IDLE mode, EC oscillator) 2.7 3.5 mA +125°C VDD = 5.0V 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.© 2007 Microchip Technology Inc. DS39605F-page 247 PIC18F1220/1320 Supply Current (IDD) (2,3) All devices 3.2 4.1 mA -40°C FOSC = 40 MHz (PRI_IDLE mode, EC oscillator) 3.2 4.1 mA +25°C VDD = 4.2 V 3.3 4.1 mA +85°C All devices 4.0 5.1 mA -40°C 4.1 5.1 mA +25°C VDD = 5.0V 4.1 5.1 mA +85°C PIC18LF1220/1320 5.1 9 μA -10°C FOSC = 32 kHz(4) (SEC_RUN mode, Timer1 as clock) 5.8 9 μA +25°C VDD = 2.0V 7.9 11 μA +70°C PIC18LF1220/1320 7.9 12 μA -10°C 8.9 12 μA +25°C VDD = 3.0V 10.5 14 μA +70°C All devices 12.5 20 μA -10°C 16.3 20 μA +25°C VDD = 5.0V 18.4 25 μA +70°C 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.PIC18F1220/1320 DS39605F-page 248 © 2007 Microchip Technology Inc. Supply Current (IDD) (2,3) PIC18LF1220/1320 9.2 15 μA -10°C FOSC = 32 kHz(4) (SEC_IDLE mode, Timer1 as clock) 9.6 15 μA +25°C VDD = 2.0V 12.7 18 μA +70°C PIC18LF1220/1320 22 30 μA -10°C 21 30 μA +25°C VDD = 3.0V 20 35 μA +70°C All devices 50 80 μA -10°C 45 80 μA +25°C VDD = 5.0V 45 80 μA +70°C 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.© 2007 Microchip Technology Inc. DS39605F-page 249 PIC18F1220/1320 Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD) D022 (ΔIWDT) Watchdog Timer 1.5 4.0 μA -40°C 2.2 4.0 μA +25°C VDD = 2.0V 3.1 5.0 μA +85°C 2.5 6.0 μA -40°C 3.3 6.0 μA +25°C VDD = 3.0V 4.7 7.0 μA +85°C 3.7 10.0 μA -40°C 4.5 10.0 μA +25°C VDD = 5.0V 6.1 13.0 μA +85°C D022A (ΔIBOR) Brown-out Reset 19 35.0 μA -40°C to +85°C VDD = 3.0V 24 45.0 μA -40°C to +85°C VDD = 5.0V D022B (ΔILVD) Low-Voltage Detect 8.5 25.0 μA -40°C to +85°C VDD = 2.0V 16 35.0 μA -40°C to +85°C VDD = 3.0V 20 45.0 μA -40°C to +85°C VDD = 5.0V D025 (ΔIOSCB) Timer1 Oscillator 1.7 3.5 μA -40°C 1.8 3.5 μA +25°C VDD = 2.0V 32 kHz on Timer1(4) 2.1 4.5 μA +85°C 2.2 4.5 μA -40°C 2.6 4.5 μA +25°C VDD = 3.0V 32 kHz on Timer1(4) 2.8 5.5 μA +85°C 3.0 6.0 μA -40°C 3.3 6.0 μA +25°C VDD = 5.0V 32 kHz on Timer1(4) 3.6 7.0 μA +85°C D026 (ΔIAD) A/D Converter 1.0 3.0 μA -40°C to +85°C VDD = 2.0V A/D on, not converting 1.0 4.0 μA -40°C to +85°C VDD = 3.0V 2.0 10.0 μA -40°C to +85°C VDD = 5.0V 1.0 8.0 μA -40°C to +125°C VDD = 5.0V 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Typ Max Units Conditions Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost.PIC18F1220/1320 DS39605F-page 250 © 2007 Microchip Technology Inc. 22.3 DC Characteristics: PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Symbol Characteristic Min Max Units Conditions VIL Input Low Voltage I/O ports: D030 with TTL buffer VSS 0.15 VDD V VDD < 4.5V D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger buffer VSS 0.2 VDD V D032 MCLR VSS 0.2 VDD V D032A OSC1 (in XT, HS and LP modes) and T1OSI VSS 0.3 VDD V D033 OSC1 (in RC and EC mode)(1) VSS 0.2 VDD V VIH Input High Voltage I/O ports: D040 with TTL buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V D041 with Schmitt Trigger buffer 0.8 VDD VDD V D042 MCLR, OSC1 (EC mode) 0.8 VDD VDD V D042A OSC1 (in XT, HS and LP modes) and T1OSI 1.6 VDD VDD V D043 OSC1 (RC mode)(1) 0.9 VDD VDD V IIL Input Leakage Current(2,3) D060 I/O ports — ±1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR — ±5 μA VSS ≤ VPIN ≤ VDD D063 OSC1 — ±5 μA VSS ≤ VPIN ≤ VDD IPU Weak Pull-up Current D070 IPURB PORTB weak pull-up current 50 400 μA VDD = 5V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested.© 2007 Microchip Technology Inc. DS39605F-page 251 PIC18F1220/1320 VOL Output Low Voltage D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D083 OSC2/CLKO (RC mode) — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C VOH Output High Voltage(3) D090 I/O ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C D092 OSC2/CLKO (RC mode) VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C D150 VOD Open-Drain High Voltage — 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 (in RC mode) — 50 pF To meet the AC timing specifications D102 CB SCL, SDA — 400 pF In I2C mode 22.3 DC Characteristics: PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Symbol Characteristic Min Max Units Conditions Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested.PIC18F1220/1320 DS39605F-page 252 © 2007 Microchip Technology Inc. TABLE 22-1: MEMORY PROGRAMMING REQUIREMENTS DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Sym Characteristic Min Typ† Max Units Conditions Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP pin 9.00 — 13.25 V (Note 2) D112 IPP Current into MCLR/VPP pin — — 5 μA D113 IDDP Supply Current during Programming — — 10 mA Data EEPROM Memory D120 ED Byte Endurance 100K 1M — E/W -40°C to +85°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write Cycles before Refresh(3) 1M 10M — E/W -40°C to +85°C Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 4.5 — 5.5 V Using ICSP port D132A VIW VDD for Externally Timed Erase or Write 4.5 — 5.5 V Using ICSP port D132B VPEW VDD for Self-Timed Write VMIN — 5.5 V VMIN = Minimum operating voltage D133 TIE ICSP™ Block Erase Cycle Time — 4 — ms VDD > 4.5V D133A TIW ICSP Erase or Write Cycle Time (externally timed) 1 — — ms VDD > 4.5V D133A TIW Self-Timed Write Cycle Time — 2 — ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: The pin may be kept in this range at times other than programming, but it is not recommended. 3: Refer to Section 7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance.© 2007 Microchip Technology Inc. DS39605F-page 253 PIC18F1220/1320 FIGURE 22-4: LOW-VOLTAGE DETECT CHARACTERISTICS VLVD LVDIF VDD (LVDIF set by hardware) (LVDIF can be cleared in software) TABLE 22-2: LOW-VOLTAGE DETECT CHARACTERISTICS PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Symbol Characteristic Min Typ† Max Units Conditions D420D LVD Voltage on VDD Transition High-to-Low Industrial Low Voltage (-10°C to +85°C) PIC18LF1220/1320 LVDL<3:0> = 0000 N/A N/A N/A V Reserved LVDL<3:0> = 0001 N/A N/A N/A V Reserved LVDL<3:0> = 0010 2.08 2.26 2.44 V LVDL<3:0> = 0011 2.26 2.45 2.65 V LVDL<3:0> = 0100 2.35 2.55 2.76 V LVDL<3:0> = 0101 2.55 2.77 2.99 V LVDL<3:0> = 0110 2.64 2.87 3.10 V LVDL<3:0> = 0111 2.82 3.07 3.31 V LVDL<3:0> = 1000 3.09 3.36 3.63 V LVDL<3:0> = 1001 3.29 3.57 3.86 V LVDL<3:0> = 1010 3.38 3.67 3.96 V LVDL<3:0> = 1011 3.56 3.87 4.18 V LVDL<3:0> = 1100 3.75 4.07 4.40 V LVDL<3:0> = 1101 3.93 4.28 4.62 V LVDL<3:0> = 1110 4.23 4.60 4.96 V Legend: Shading of rows is to assist in readability of the table. † Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.PIC18F1220/1320 DS39605F-page 254 © 2007 Microchip Technology Inc. D420F LVD Voltage on VDD Transition High-to-Low Industrial Low Voltage (-40°C to -10°C) PIC18LF1220/1320 LVDL<3:0> = 0000 N/A N/A N/A V Reserved LVDL<3:0> = 0001 N/A N/A N/A V Reserved LVDL<3:0> = 0010 1.99 2.26 2.53 V LVDL<3:0> = 0011 2.16 2.45 2.75 V LVDL<3:0> = 0100 2.25 2.55 2.86 V LVDL<3:0> = 0101 2.43 2.77 3.10 V LVDL<3:0> = 0110 2.53 2.87 3.21 V LVDL<3:0> = 0111 2.70 3.07 3.43 V LVDL<3:0> = 1000 2.96 3.36 3.77 V LVDL<3:0> = 1001 3.14 3.57 4.00 V LVDL<3:0> = 1010 3.23 3.67 4.11 V LVDL<3:0> = 1011 3.41 3.87 4.34 V LVDL<3:0> = 1100 3.58 4.07 4.56 V LVDL<3:0> = 1101 3.76 4.28 4.79 V LVDL<3:0> = 1110 4.04 4.60 5.15 V LVD Voltage on VDD Transition High-to-Low Industrial (-10°C to +85°C) D420G PIC18F1220/1320 LVDL<3:0> = 1101 3.93 4.28 4.62 V LVDL<3:0> = 1110 4.23 4.60 4.96 V LVD Voltage on VDD Transition High-to-Low Industrial (-40°C to -10°C) D420H PIC18F1220/1320 LVDL<3:0> = 1101 3.76 4.28 4.79 V LVDL<3:0> = 1110 4.04 4.60 5.15 V LVD Voltage on VDD Transition High-to-Low Extended (-10°C to +85°C) D420J PIC18F1220/1320 LVDL<3:0> = 1101 3.94 4.28 4.62 V LVDL<3:0> = 1110 4.23 4.60 4.96 V LVD Voltage on VDD Transition High-to-Low Extended (-40°C to -10°C, +85°C to +125°C) D420K PIC18F1220/1320 LVDL<3:0> = 1101 3.77 4.28 4.79 V LVDL<3:0> = 1110 4.05 4.60 5.15 V TABLE 22-2: LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Symbol Characteristic Min Typ† Max Units Conditions Legend: Shading of rows is to assist in readability of the table. † Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.© 2007 Microchip Technology Inc. DS39605F-page 255 PIC18F1220/1320 22.4 AC (Timing) Characteristics 22.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-Impedance) V Valid L Low Z High-Impedance I 2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start conditionPIC18F1220/1320 DS39605F-page 256 © 2007 Microchip Technology Inc. 22.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 22-3 apply to all timing specifications unless otherwise noted. Figure 22-5 specifies the load conditions for the timing specifications. TABLE 22-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC FIGURE 22-5: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC spec Section 22.1 and Section 22.3. LF parts operate for industrial temperatures only. VDD/2 CL RL pin Pin VSS VSS CL RL = 464Ω CL = 50 pF for all pins except OSC2/CLKO Load Condition 1 Load Condition 2© 2007 Microchip Technology Inc. DS39605F-page 257 PIC18F1220/1320 22.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 22-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) TABLE 22-4: EXTERNAL CLOCK TIMING REQUIREMENTS OSC1 CLKO Q4 Q1 Q2 Q3 Q4 Q1 1 2 3 3 4 4 Param. No. Symbol Characteristic Min Max Units Conditions 1A FOSC External CLKI Frequency(1) DC 40 MHz EC, ECIO (LF and Industrial) DC 25 MHz EC, ECIO (Extended) Oscillator Frequency(1) DC 4 MHz RC oscillator DC 1 MHz XT oscillator DC 25 MHz HS oscillator 1 10 MHz HS + PLL oscillator DC 33 kHz LP Oscillator mode 1 TOSC External CLKI Period(1) 25 — ns EC, ECIO (LF and Industrial) 40 — ns EC, ECIO (Extended) Oscillator Period(1) 250 — ns RC oscillator 1000 — ns XT oscillator 25 100 — 1000 ns ns HS oscillator HS + PLL oscillator 30 — μs LP oscillator 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC 3 TosL, TosH External Clock in (OSC1) High or Low Time 30 — ns XT oscillator 2.5 — μs LP oscillator 10 — ns HS oscillator 4 TosR, TosF External Clock in (OSC1) Rise or Fall Time — 20 ns XT oscillator — 50 ns LP oscillator — 7.5 ns HS oscillator Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.PIC18F1220/1320 DS39605F-page 258 © 2007 Microchip Technology Inc. TABLE 22-5: PLL CLOCK TIMING SPECIFICATIONS, HS/HSPLL MODE (VDD = 4.2V TO 5.5V) Param No. Sym Characteristic Min Typ† Max Units Conditions F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS and HSPLL mode only F11 FSYS On-Chip VCO System Frequency 16 — 40 MHz HSPLL mode only F12 TPLL PLL Start-up Time (Lock Time) — — 2 ms HSPLL mode only F13 ΔCLK CLKO Stability (Jitter) -2 — +2 % HSPLL mode only † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 22-6: INTERNAL RC ACCURACY: PIC18F1220/1320 (INDUSTRIAL) PIC18LF1220/1320 (INDUSTRIAL) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Min Typ Max Units Conditions INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) PIC18LF1220/1320 -2 +/-1 2 % +25°C VDD = 2.7-3.3V -5 — 5 % -10°C to +85°C VDD = 2.7-3.3V -10 — 10 % -40°C to +85°C VDD = 2.7-3.3V PIC18F1220/1320PIC18F 1220/1320 -2 +/-1 2 % +25°C VDD = 4.5-5.5V -5 — 5 % -10°C to +85°C VDD = 4.5-5.5V -10 — 10 % -40°C to +85°C VDD = 4.5-5.5V INTRC Accuracy @ Freq = 31 kHz(2) PIC18LF1220/1320 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V PIC18F1220/1320PIC18F 1220/1320 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V Legend: Shading of rows is to assist in readability of the table. Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature and VDD drift. 2: INTRC frequency after calibration. 3: Change of INTRC frequency as VDD changes.© 2007 Microchip Technology Inc. DS39605F-page 259 PIC18F1220/1320 FIGURE 22-7: CLKO AND I/O TIMING TABLE 22-7: CLKO AND I/O TIMING REQUIREMENTS Note: Refer to Figure 22-5 for load conditions. OSC1 CLKO I/O pin (Input) I/O pin (Output) Q4 Q1 Q2 Q3 10 13 14 17 20, 21 19 18 15 11 12 16 Old Value New Value Param. No. Symbol Characteristic Min Typ Max Units Conditions 10 TosH2ckL OSC1↑ to CLKO↓ — 75 200 ns (Note 1) 11 TosH2ckH OSC1↑ to CLKO↑ — 75 200 ns (Note 1) 12 TckR CLKO Rise Time — 35 100 ns (Note 1) 13 TckF CLKO Fall Time — 35 100 ns (Note 1) 14 TckL2ioV CLKO↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TioV2ckH Port In Valid before CLKO↑ 0.25 TCY + 25 — — ns (Note 1) 16 TckH2ioI Port In Hold after CLKO↑ 0 — — ns (Note 1) 17 TosH2ioV OSC1↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TosH2ioI OSC1↑ (Q2 cycle) to Port Input Invalid (I/O in hold time) PIC18F1X20 100 — — ns 18A PIC18LF1X20 200 — — ns 19 TioV2osH Port Input Valid to OSC1↑ (I/O in setup time) 0 — — ns 20 TioR Port Output Rise Time PIC18F1X20 — 10 25 ns 20A PIC18LF1X20 — — 60 ns 21 TioF Port Output Fall Time PIC18F1X20 — 10 25 ns 21A PIC18LF1X20 — — 60 ns Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.PIC18F1220/1320 DS39605F-page 260 © 2007 Microchip Technology Inc. FIGURE 22-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING FIGURE 22-9: BROWN-OUT RESET TIMING VDD MCLR Internal POR PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 33 32 30 31 34 I/O pins 34 Note: Refer to Figure 22-5 for load conditions. VDD BVDD 35 VBGAP = 1.2V VIRVST Enable Internal Internal Reference 36 Reference Voltage Voltage Stable© 2007 Microchip Technology Inc. DS39605F-page 261 PIC18F1220/1320 TABLE 22-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS FIGURE 22-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS Param. No. Symbol Characteristic Min Typ Max Units Conditions 30 TmcL MCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period (No postscaler) 3.48 4.00 4.71 ms 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period — 65.5 132 ms 34 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset —2— μs 35 TBOR Brown-out Reset Pulse Width 200 — — μs VDD ≤ BVDD (see D005) 36 TIVRST Time for Internal Reference Voltage to become stable — 20 50 μs 37 TLVD Low-Voltage Detect Pulse Width 200 — — μs VDD ≤ VLVD Note: Refer to Figure 22-5 for load conditions. 46 47 45 48 41 42 40 T0CKI T1OSO/T13CKI TMR0 or TMR1PIC18F1220/1320 DS39605F-page 262 © 2007 Microchip Technology Inc. TABLE 22-9: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS FIGURE 22-11: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) Param No. Symbol Characteristic Min Max Units Conditions 40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 Tt0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 Tt0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: 20 ns or TCY + 40 N — ns N = prescale value (1, 2, 4,..., 256) 45 Tt1H T13CKI High Time Synchronous, no prescaler 0.5 TCY + 20 — ns Synchronous, with prescaler PIC18F1X20 10 — ns PIC18LF1X20 25 — ns Asynchronous PIC18F1X20 30 — ns PIC18LF1X20 50 — ns 46 Tt1L T13CKI Low Time Synchronous, no prescaler 0.5 TCY + 5 — ns Synchronous, with prescaler PIC18F1X20 10 — ns PIC18LF1X20 25 — ns Asynchronous PIC18F1X20 30 — ns PIC18LF1X20 50 — ns 47 Tt1P T13CKI Input Period Synchronous Greater of: 20 ns or TCY + 40 N — ns N = prescale value (1, 2, 4, 8) Asynchronous 60 — ns Ft1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 Tcke2tmrI Delay from External T13CKI Clock Edge to Timer Increment 2 TOSC 7 TOSC — Note: Refer to Figure 22-5 for load conditions. CCPx (Capture Mode) 50 51 52 CCPx 53 54 (Compare or PWM Mode)© 2007 Microchip Technology Inc. DS39605F-page 263 PIC18F1220/1320 TABLE 22-10: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) FIGURE 22-12: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TABLE 22-11: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. No. Symbol Characteristic Min Max Units Conditions 50 TccL CCPx Input Low Time No prescaler 0.5 TCY + 20 — ns With prescaler PIC18F1X20 10 — ns PIC18LF1X20 20 — ns 51 TccH CCPx Input High Time No prescaler 0.5 TCY + 20 — ns With prescaler PIC18F1X20 10 — ns PIC18LF1X20 20 — ns 52 TccP CCPx Input Period 3 TCY + 40 N — ns N = prescale value (1, 4 or 16) 53 TccR CCPx Output Fall Time PIC18F1X20 — 25 ns PIC18LF1X20 — 45 ns 54 TccF CCPx Output Fall Time PIC18F1X20 — 25 ns PIC18LF1X20 — 45 ns 121 121 120 122 RB1/AN5/TX/ RB4/AN6/RX/ DT/KBI0 pin CK/INT1 pin Note: Refer to Figure 22-5 for load conditions. Param. No. Symbol Characteristic Min Max Units Conditions 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid PIC18F1X20 — 40 ns PIC18LF1X20 — 100 ns 121 Tckrf Clock Out Rise Time and Fall Time (Master mode) PIC18F1X20 — 20 ns PIC18LF1X20 — 50 ns 122 Tdtrf Data Out Rise Time and Fall Time PIC18F1X20 — 20 ns PIC18LF1X20 — 50 nsPIC18F1220/1320 DS39605F-page 264 © 2007 Microchip Technology Inc. FIGURE 22-13: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TABLE 22-12: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS TABLE 22-13: A/D CONVERTER CHARACTERISTICS: PIC18F1220/1320 (INDUSTRIAL) PIC18LF1220/1320 (INDUSTRIAL) Param. No. Symbol Characteristic Min Max Units Conditions 125 TdtV2ckl SYNC RCV (MASTER & SLAVE) Data Hold before CK↓ (DT hold time) 10 — ns 126 TckL2dtl Data Hold after CK↓ (DT hold time) 15 — ns Param No. Symbol Characteristic Min Typ Max Units Conditions A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±1 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.0V A10 — Monotonicity guaranteed(2) — A20 ΔVREF Reference Voltage Range (VREFH – VREFL) 3 — AVDD – AVSS V For 10-bit resolution A21 VREFH Reference Voltage High AVSS + 3.0V — AVDD + 0.3V V For 10-bit resolution A22 VREFL Reference Voltage Low AVSS – 0.3V — AVDD – 3.0V V For 10-bit resolution A25 VAIN Analog Input Voltage VREFL — VREFH V A28 AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V A29 AVSS Analog Supply Voltage VSS – 0.3 — VSS + 0.3 V A30 ZAIN Recommended Impedance of Analog Voltage Source — — 2.5 kΩ A40 IAD A/D Conversion Current (VDD) PIC18F1X20 — 180 — μA Average current consumption when A/D is on (Note 1) PIC18LF1X20 — 90 — μA A50 IREF VREF Input Current (Note 3) — — — — ±5 ±150 μA μA During VAIN acquisition. During A/D conversion cycle. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current specification includes any such leakage from the A/D module. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source. 125 126 Note: Refer to Figure 22-5 for load conditions. RB1/AN5/TX/ RB4/AN6/RX/ DT/KBI0 pin CK/INT1 pin© 2007 Microchip Technology Inc. DS39605F-page 265 PIC18F1220/1320 FIGURE 22-14: A/D CONVERSION TIMING TABLE 22-14: A/D CONVERSION REQUIREMENTS 131 130 132 BSF ADCON0, GO Q4 A/D CLK(1) A/D DATA ADRES ADIF GO SAMPLE OLD_DATA Sampling Stopped DONE NEW_DATA (Note 2) 9 87 2 1 0 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . TCY Param No. Symbol Characteristic Min Max Units Conditions 130 TAD A/D Clock Period PIC18F1X20 1.6 20(5) μs TOSC based, VREF ≥ 3.0V PIC18LF1X20 3.0 20(5) μs TOSC based, VREF full range PIC18F1X20 2.0 6.0 μs A/D RC mode PIC18LF1X20 3.0 9.0 μs A/D RC mode 131 TCNV Conversion Time (not including acquisition time) (Note 1) 11 12 TAD 132 TACQ Acquisition Time (Note 3) 15 10 — — μs μs -40°C ≤ Temp ≤ +125°C 0°C ≤ Temp ≤ +125°C 135 TSWC Switching Time from Convert → Sample — (Note 4) 136 TAMP Amplifier Settling Time (Note 2) 1 — μs This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 17.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input voltage has changed more than 1 LSb. 3: The time for the holding capacitor to acquire the “New” input voltage, when the voltage changes full scale after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50Ω. 4: On the next Q4 cycle of the device clock. 5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. PIC18F1220/1320 DS39605F-page 266 © 2007 Microchip Technology Inc. NOTES:© 2007 Microchip Technology Inc. DS39605F-page 267 PIC18F1220/1320 23.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean – 3σ) respectively, where σ is a standard deviation, over the whole temperature range. FIGURE 23-1: TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C FIGURE 23-2: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +85°C Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 0.0 0.1 0.2 0.3 0.4 0.5 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 FOSC (MHz) IDD (mA) 5.0V 5.5V 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 FOSC (MHz) IDD (mA) 5.0V 5.5V 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)PIC18F1220/1320 DS39605F-page 268 © 2007 Microchip Technology Inc. FIGURE 23-3: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C FIGURE 23-4: TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 FOSC (MHz) IDD (mA) 5.0V 5.5V 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) IDD (mA) 5.0V 5.5V 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)© 2007 Microchip Technology Inc. DS39605F-page 269 PIC18F1220/1320 FIGURE 23-5: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C FIGURE 23-6: TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C 0.0 0.5 1.0 1.5 2.0 2.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) IDD (mA) 5.0V 5.5V 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0 2 4 6 8 10 12 14 16 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) IDD (mA) 5.0V 5.5V 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)PIC18F1220/1320 DS39605F-page 270 © 2007 Microchip Technology Inc. FIGURE 23-7: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C FIGURE 23-8: TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C 0 2 4 6 8 10 12 14 16 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) IDD (mA) 5.0V 5.5V 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 FOSC (MHz) IDD (mA) 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V 5.0V 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)© 2007 Microchip Technology Inc. DS39605F-page 271 PIC18F1220/1320 FIGURE 23-9: MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +85°C FIGURE 23-10: MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 FOSC (MHz) IDD (mA) 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V 5.0V 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.000 0.010 0.020 0.030 0.040 0.050 0.060 0.070 0.080 0.090 0.100 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 FOSC (MHz) IDD (mA) 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V 5.0V 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)PIC18F1220/1320 DS39605F-page 272 © 2007 Microchip Technology Inc. FIGURE 23-11: TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C FIGURE 23-12: MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C Typical I vs F over V PRI_IDLE, EC mode, +25°C 0 100 200 300 400 500 600 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) IDD (μA) 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V 5.0V 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0 100 200 300 400 500 600 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) IDD (μA) 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V 5.0V 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)© 2007 Microchip Technology Inc. DS39605F-page 273 PIC18F1220/1320 FIGURE 23-13: TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C FIGURE 23-14: MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) IDD (mA) 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V 5.0V 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) IDD (mA) 4.0V 4.5V 3.0V 3.5V 2.0V 2.5V 5.0V 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)PIC18F1220/1320 DS39605F-page 274 © 2007 Microchip Technology Inc. FIGURE 23-15: TYPICAL IPD vs. VDD (+25°C), 125 kHz TO 8 MHz RC_RUN MODE, ALL PERIPHERALS DISABLED FIGURE 23-16: MAXIMUM IPD vs. VDD (-40°C TO +125°C), 125 kHz TO 8 MHz RC_RUN MODE, ALL PERIPHERALS DISABLED 0 500 1000 1500 2000 2500 3000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) 8 MHz 125 kHz 4 MHz 2 MHz 1 MHz 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves. Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0 500 1000 1500 2000 2500 3000 3500 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) 8 MHz 125 kHz 4 MHz 2 MHz 1 MHz 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves. Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)© 2007 Microchip Technology Inc. DS39605F-page 275 PIC18F1220/1320 FIGURE 23-17: TYPICAL AND MAXIMUM IPD vs. VDD (-40°C TO +125°C), 31.25 kHz RC_RUN MODE, ALL PERIPHERALS DISABLED FIGURE 23-18: TYPICAL IPD vs. VDD (+25°C), 125 kHz TO 8 MHz RC_IDLE MODE, ALL PERIPHERALS DISABLED 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Typ (+25°C) Max (+85°C) Max (+125°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) 8 MHz 125 kHz 4 MHz 2 MHz 1 MHz 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves. Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)PIC18F1220/1320 DS39605F-page 276 © 2007 Microchip Technology Inc. FIGURE 23-19: MAXIMUM IPD vs. VDD (-40°C TO +125°C), 125 kHz TO 8 MHz RC_IDLE MODE, ALL PERIPHERALS DISABLED FIGURE 23-20: TYPICAL AND MAXIMUM IPD vs. VDD (-40°C TO +125°C), 31.25 kHz RC_IDLE MODE, ALL PERIPHERALS DISABLED 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) 8 MHz 125 kHz 4 MHz 2 MHz 1 MHz 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves. Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Typ (+25°C) Max (+85°C) Max (+125°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)© 2007 Microchip Technology Inc. DS39605F-page 277 PIC18F1220/1320 FIGURE 23-21: IPD SEC_RUN MODE, -10°C TO +70°C, 32.768 kHz XTAL, 2 x 22 pF, ALL PERIPHERALS DISABLED FIGURE 23-22: IPD SEC_IDLE MODE, -10°C TO +70°C, 32.768 kHz, 2 x 22 pF, ALL PERIPHERALS DISABLED 0 10 20 30 40 50 60 70 80 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Typ (+25°C) Max (+70°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0 2 4 6 8 10 12 14 16 18 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Typ (+25°C) Max (+70°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)PIC18F1220/1320 DS39605F-page 278 © 2007 Microchip Technology Inc. FIGURE 23-23: TOTAL IPD, -40°C TO +125°C SLEEP MODE, ALL PERIPHERALS DISABLED FIGURE 23-24: VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 3.0V 0.001 0.01 0.1 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Max (+85°C) Max (+125°C) Typ (+25°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 IOH (-mA) VOH (V) Max (+125°C) Min (+125°C) Typ (+25°C)© 2007 Microchip Technology Inc. DS39605F-page 279 PIC18F1220/1320 FIGURE 23-25: VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V FIGURE 23-26: VOL vs. IOL OVER TEMPERATURE (-40°C TO +125°C), VDD = 3.0V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 5 10 15 20 25 IOH (-mA) VOH (V) Max (+125°C) Min (+125°C) Typ (+25°C) V vs I over Temp (-40°C to +125°C) V = 3.0V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 IOL (-mA) VOL (V) Max (+125°C) Max (+85°C) Typ (+25°C) Min (+125°C)PIC18F1220/1320 DS39605F-page 280 © 2007 Microchip Technology Inc. FIGURE 23-27: VOL vs. IOL OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V FIGURE 23-28: ΔIPD TIMER1 OSCILLATOR, -10°C TO +70°C SLEEP MODE, TMR1 COUNTER DISABLED 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 25 IOL (-mA) VOL (V) Max (+125°C) Max (+85°C) Typ (+25°C) Min (+125°C) IPD Timer1 Oscillator, -10°C to +70°C SLEEP mode, TMR1 counter disabled 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Typ (+25°C) Max (-10°C to +70°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)© 2007 Microchip Technology Inc. DS39605F-page 281 PIC18F1220/1320 FIGURE 23-29: ΔIPD FSCM vs. VDD OVER TEMPERATURE PRI_IDLE MODE, EC OSCILLATOR AT 32 kHz, -40°C TO +125°C FIGURE 23-30: ΔIPD WDT, -40°C TO +125°C SLEEP MODE, ALL PERIPHERALS DISABLED 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) ΔIPD (μA) Typ (+25°C) Max (-40°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0 2 4 6 8 10 12 14 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) ΔIPD (μA) Typ (+25°C) Max (+85°C) Max (+125°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)PIC18F1220/1320 DS39605F-page 282 © 2007 Microchip Technology Inc. FIGURE 23-31: ΔIPD LVD vs. VDD SLEEP MODE, LVDL3:LVDL0 = 0001 (2V) FIGURE 23-32: ΔIPD BOR vs. VDD, -40°C TO +125°C SLEEP MODE, BORV1:BORV0 = 11 (2V) 0 5 10 15 20 25 30 35 40 45 50 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Typ (+25°C) Max (+85°C) Max (+125°C) Low-Voltage Detection Range Normal Operating Range Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0 5 10 15 20 25 30 35 40 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Max (+125°C) Typ (+25°C) Device may be in Reset Device is Operating Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C)© 2007 Microchip Technology Inc. DS39605F-page 283 PIC18F1220/1320 FIGURE 23-33: ΔIPD A/D, -40°C TO +125°C SLEEP MODE, A/D ENABLED (NOT CONVERTING) FIGURE 23-34: AVERAGE FOSC vs. VDD FOR VARIOUS R’s EXTERNAL RC MODE, C = 20 pF, TEMPERATURE = +25°C 0.001 0.01 0.1 1 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Max (+125°C) Max (+85°C) Typ (+25°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Freq (MHz) 5.1K 10K 33K 100K Operation above 4 MHz is not recomendedPIC18F1220/1320 DS39605F-page 284 © 2007 Microchip Technology Inc. FIGURE 23-35: AVERAGE FOSC vs. VDD FOR VARIOUS R’s EXTERNAL RC MODE, C = 100 pF, TEMPERATURE = +25°C FIGURE 23-36: AVERAGE FOSC vs. VDD FOR VARIOUS R’s EXTERNAL RC MODE, C = 300 pF, TEMPERATURE = +25°C 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Freq (MHz) 5.1K 10K 33K 100K 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Freq (MHz) 5.1K 10K 33K 100K© 2007 Microchip Technology Inc. DS39605F-page 285 PIC18F1220/1320 24.0 PACKAGING INFORMATION 24.1 Package Marking Information 18-Lead PDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F1320-I/P 0710017 18-Lead SOIC XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Example PIC18F1220- E/SO 0710017 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example PIC18F1220- E/SS 0710017 28-Lead QFN XXXXXXXX XXXXXXXX YYWWNNN Example 18F1320 -I/ML 0710017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e3 e3 e3 e3 e3 e3PIC18F1220/1320 DS39605F-page 286 © 2007 Microchip Technology Inc. 24.2 Package Details The following sections give the technical details of the packages. 18-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 18 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .300 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .880 .900 .920 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .014 Upper Lead Width b1 .045 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 NOTE 1 N E1 D 1 2 3 A A1 A2 L E eB c e b1 b Microchip Technology Drawing C04-007B© 2007 Microchip Technology Inc. DS39605F-page 287 PIC18F1220/1320 18-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 18 Pitch e 1.27 BSC Overall Height A – – 2.65 Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 Overall Width E 10.30 BSC Molded Package Width E1 7.50 BSC Overall Length D 11.55 BSC Chamfer (optional) h 0.25 – 0.75 Foot Length L 0.40 – 1.27 Footprint L1 1.40 REF Foot Angle φ 0° – 8° Lead Thickness c 0.20 – 0.33 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° NOTE 1 D N E E1 e b 1 2 3 A A1 A2 L L1 h h c β φ α Microchip Technology Drawing C04-051BPIC18F1220/1320 DS39605F-page 288 © 2007 Microchip Technology Inc. 20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 20 Pitch e 0.65 BSC Overall Height A – – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.20 Molded Package Width E1 5.00 5.30 5.60 Overall Length D 6.90 7.20 7.50 Foot Length L 0.55 0.75 0.95 Footprint L1 1.25 REF Lead Thickness c 0.09 – 0.25 Foot Angle φ 0° 4° 8° Lead Width b 0.22 – 0.38 φ L1 L A2 c e b A1 A 1 2 NOTE 1 E1 E D N Microchip Technology Drawing C04-072B© 2007 Microchip Technology Inc. DS39605F-page 289 PIC18F1220/1320 28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN] with 0.55 mm Contact Length Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e 0.65 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E 6.00 BSC Exposed Pad Width E2 3.65 3.70 4.20 Overall Length D 6.00 BSC Exposed Pad Length D2 3.65 3.70 4.20 Contact Width b 0.23 0.30 0.35 Contact Length L 0.50 0.55 0.70 Contact-to-Exposed Pad K 0.20 – – D EXPOSED D2 e b K E2 E L N NOTE 1 1 2 2 1 N A A3 A1 TOP VIEW BOTTOM VIEW PAD Microchip Technology Drawing C04-105BPIC18F1220/1320 DS39605F-page 290 © 2007 Microchip Technology Inc. NOTES:© 2007 Microchip Technology Inc. DS39605F-page 291 PIC18F1220/1320 APPENDIX A: REVISION HISTORY Revision A (August 2002) Original data sheet for PIC18F1220/1320 devices. Revision B (November 2002) This revision includes significant changes to Section 2.0, Section 3.0 and Section 19.0, as well as updates to the Electrical Specifications in Section 22.0 and includes minor corrections to the data sheet text. Revision C (May 2004) This revision includes updates to the Electrical Specifications in Section 22.0, the DC and AC Characteristics Graphs and Tables in Section 23.0 and includes minor corrections to the data sheet text. Revision D (October 2006) This revision includes updates to the packaging diagrams. Revision E (January 2007) This revision includes updates to the packaging diagrams. Revision F (February 2007) This revision includes updates to the packaging diagrams. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES Features PIC18F1220 PIC18F1320 Program Memory (Bytes) 4096 8192 Program Memory (Instructions) 2048 4096 Interrupt Sources 15 15 I/O Ports Ports A, B Ports A, B Enhanced Capture/Compare/PWM Modules 1 1 10-bit Analog-to-Digital Module 7 input channels 7 input channels Packages 18-pin SDIP 18-pin SOIC 20-pin SSOP 28-pin QFN 18-pin SDIP 18-pin SOIC 20-pin SSOP 28-pin QFNPIC18F1220/1320 DS39605F-page 292 © 2007 Microchip Technology Inc. APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to an enhanced MCU device (i.e., PIC18FXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Not Currently Available© 2007 Microchip Technology Inc. DS39605F-page 293 PIC18F1220/1320 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442”. The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. This Application Note is available as Literature Number DS00716. APPENDIX F: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, “PIC17CXXX to PIC18CXXX Migration”. This Application Note is available as Literature Number DS00726.PIC18F1220/1320 DS39605F-page 294 © 2007 Microchip Technology Inc. NOTES:© 2007 Microchip Technology Inc. DS39605F-page 295 PIC18F1220/1320 INDEX A A/D ................................................................................... 155 A/D Converter Interrupt, Configuring ....................... 159 Acquisition Requirements ........................................ 160 ADCON0 Register .................................................... 155 ADCON1 Register .................................................... 155 ADCON2 Register .................................................... 155 ADRESH Register .................................................... 155 ADRESH/ADRESL Registers .................................. 158 ADRESL Register .................................................... 155 Analog Port Pins, Configuring .................................. 162 Associated Registers ............................................... 164 Configuring the Module ............................................ 159 Conversion Clock (Tad) ........................................... 161 Conversion Requirements ....................................... 265 Conversion Status (GO/DONE Bit) .......................... 158 Conversions ............................................................. 163 Converter Characteristics ........................................ 264 Operation in Low-Power Modes ............................... 162 Selecting, Configuring Automatic Acquisition Time ............................................... 161 Special Event Trigger (CCP) .................................... 117 Special Event Trigger (CCP1) .................................. 164 Use of the CCP1 Trigger .......................................... 164 Vref+ and Vref- References ..................................... 160 Absolute Maximum Ratings ............................................. 237 AC (Timing) Characteristics ............................................. 255 Conditions ................................................................ 256 Load Conditions for Device Timing Specifications ....................................... 256 Parameter Symbology ............................................. 255 Temperature and Voltage Specifications ................. 256 ADCON0 Register ............................................................ 155 GO/DONE Bit ........................................................... 158 ADCON1 Register ............................................................ 155 ADCON2 Register ............................................................ 155 ADDLW ............................................................................ 197 ADDWF ............................................................................ 197 ADDWFC ......................................................................... 198 ADRESH Register ............................................................ 155 ADRESH/ADRESL Registers ........................................... 158 ADRESL Register ............................................................ 155 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 198 ANDWF ............................................................................ 199 Assembler MPASM Assembler .................................................. 234 Auto-Wake-up on Sync Break Character ......................... 145 B BC .................................................................................... 199 BCF .................................................................................. 200 Block Diagrams A/D ........................................................................... 158 Analog Input Model .................................................. 159 Capture Mode Operation ......................................... 117 Compare Mode Operation ....................................... 118 Enhanced PWM ....................................................... 120 EUSART Receive .................................................... 143 EUSART Transmit ................................................... 141 Fail-Safe Clock Monitor ............................................ 182 Generic I/O Port Operation ........................................ 87 Low-Voltage Detect (LVD) ....................................... 166 Low-Voltage Detect (LVD) with External Input ........ 166 MCLR/VPP/RA5 Pin ................................................... 89 On-Chip Reset Circuit ................................................ 33 OSC1/CLKI/RA7 Pin .................................................. 88 OSC2/CLKO/RA6 Pin ................................................ 88 PIC18F1220/1320 ....................................................... 7 PLL ............................................................................ 12 RA3:RA0 Pins ............................................................ 88 RA4/T0CKI Pin .......................................................... 88 RB0/AN4/INT0 Pin ..................................................... 90 RB1/AN5/TX/CK/INT1 Pin ......................................... 91 RB2/P1B/INT2 Pin ..................................................... 92 RB3/CCP1/P1A Pin ................................................... 93 RB4/AN6/RX/DT/KBI0 Pin ......................................... 94 RB5/PGM/KBI1 Pin .................................................... 95 RB6/PGC/T1OSO/T13CKI/P1C/KBI2 Pin .................. 96 RB7/PGD/T1OSI/P1D/KBI3 Pin ................................. 97 Reads from Flash Program Memory .......................... 61 System Clock ............................................................. 16 Table Read Operation ............................................... 57 Table Write Operation ................................................ 58 Table Writes to Flash Program Memory .................... 63 Timer0 in 16-Bit Mode ............................................. 100 Timer0 in 8-Bit Mode ............................................... 100 Timer1 ..................................................................... 104 Timer1 (16-Bit Read/Write Mode) ............................ 104 Timer2 ..................................................................... 110 Timer3 ..................................................................... 112 Timer3 (16-bit Read/Write Mode) ............................ 112 WDT ........................................................................ 180 BN .................................................................................... 200 BNC ................................................................................. 201 BNN ................................................................................. 201 BNOV ............................................................................... 202 BNZ .................................................................................. 202 BOR. See Brown-out Reset. BOV ................................................................................. 205 BRA ................................................................................. 203 Break Character (12-bit) Transmit and Receive .............. 146 Brown-out Reset (BOR) ..............................................34, 171 BSF .................................................................................. 203 BTFSC ............................................................................. 204 BTFSS ............................................................................. 204 BTG ................................................................................. 205 BZ .................................................................................... 206 C C Compilers MPLAB C18 ............................................................. 234 MPLAB C30 ............................................................. 234 CALL ................................................................................ 206 Capture (CCP Module) .................................................... 116 CCP Pin Configuration ............................................. 116 CCPR1H:CCPR1L Registers ................................... 116 Software Interrupt .................................................... 116 Timer1/Timer3 Mode Selection ................................ 116 Capture, Compare, Timer1 and Timer3 Associated Registers ............................................... 118PIC18F1220/1320 DS39605F-page 296 © 2007 Microchip Technology Inc. Capture/Compare/PWM (CCP) Capture Mode. See Capture. CCP1 ........................................................................116 CCPR1H Register ............................................ 116 CCPR1L Register ............................................ 116 Compare Mode. See Compare. Timer Resources ...................................................... 116 Clock Sources .................................................................... 15 Selection Using OSCCON Register ........................... 16 Clocking Scheme ............................................................... 45 CLRF ................................................................................ 207 CLRWDT .......................................................................... 207 Code Examples 16 x 16 Signed Multiply Routine ................................. 72 16 x 16 Unsigned Multiply Routine ............................. 72 8 x 8 Signed Multiply Routine ..................................... 71 8 x 8 Unsigned Multiply Routine ................................. 71 Changing Between Capture Prescalers ................... 117 Computed GOTO Using an Offset Value ................... 47 Data EEPROM Read .................................................69 Data EEPROM Refresh Routine ................................70 Data EEPROM Write .................................................. 69 Erasing a Flash Program Memory Row ..................... 62 Fast Register Stack .................................................... 44 How to Clear RAM (Bank 1) Using Indirect Addressing ............................................ 53 Implementing a Real-Time Clock Using a Timer1 Interrupt Service .................................. 107 Initializing PORTA ...................................................... 87 Initializing PORTB ...................................................... 90 Reading a Flash Program Memory Word ................... 61 Saving Status, WREG and BSR Registers in RAM ....................................... 85 Writing to Flash Program Memory ....................... 64–65 Code Protection ............................................................... 171 COMF ............................................................................... 208 Compare (CCP Module) ...................................................117 CCP Pin Configuration ............................................. 117 CCPR1 Register ....................................................... 117 Software Interrupt ..................................................... 117 Special Event Trigger ....................................... 113, 117 Timer1/Timer3 Mode Selection ................................ 117 Compare (CCP1 Module) Special Event Trigger ...............................................164 Computed GOTO ............................................................... 47 Configuration Bits ............................................................. 171 Context Saving During Interrupts ....................................... 85 Conversion Considerations .............................................. 292 CPFSEQ .......................................................................... 208 CPFSGT ........................................................................... 209 CPFSLT ........................................................................... 209 Customer Change Notification Service ............................302 Customer Notification Service .......................................... 302 Customer Support ............................................................ 302 D Data EEPROM Memory .....................................................67 Associated Registers .................................................70 EEADR Register ........................................................ 67 EECON1 Register ...................................................... 67 EECON2 Register ...................................................... 67 Operation During Code-Protect .................................. 70 Protection Against Spurious Write ............................. 69 Reading ......................................................................69 Using ..........................................................................70 Write Verify ................................................................. 69 Writing ........................................................................69 Data Memory ..................................................................... 47 General Purpose Registers ....................................... 47 Map for PIC18F1220/1320 Devices ........................... 48 Special Function Registers ........................................ 49 DAW ................................................................................ 210 DC and AC Characteristics Graphs and Tables .................................................. 267 DC Characteristics ........................................................... 250 Power-Down and Supply Current ............................ 241 Supply Voltage ......................................................... 240 DCFSNZ .......................................................................... 211 DECF ............................................................................... 210 DECFSZ .......................................................................... 211 Details on Individual Family Members ................................. 6 Development Support ...................................................... 233 Device Differences ........................................................... 291 Direct Addressing ............................................................... 54 E Effects of Power Managed Modes on Various Clock Sources .............................................. 18 Electrical Characteristics .................................................. 237 Enhanced Capture/Compare/PWM (ECCP) .................... 115 Outputs .................................................................... 116 PWM Mode. See PWM (ECCP Module). Enhanced PWM Mode. See PWM (ECCP Module). ........ 119 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................. 131 Equations 16 x 16 Signed Multiplication Algorithm ..................... 72 16 x 16 Unsigned Multiplication Algorithm ................. 72 A/D Minimum Charging Time ................................... 160 Acquisition Time ...................................................... 160 Errata ................................................................................... 4 EUSART Asynchronous Mode ................................................ 140 12-bit Break Transmit and Receive ................. 146 Associated Registers, Receive ........................ 144 Associated Registers, Transmit ....................... 142 Auto-Wake-up on Sync Break ......................... 145 Receiver .......................................................... 143 Setting up 9-bit Mode with Address Detect ........................................ 143 Transmitter ....................................................... 140 Baud Rate Generator (BRG) ................................... 135 Associated Registers ....................................... 136 Auto-Baud Rate Detect .................................... 139 Baud Rate Error, Calculating ........................... 135 Baud Rates, Asynchronous Modes ................. 136 High Baud Rate Select (BRGH Bit) ................. 135 Power Managed Mode Operation .................... 135 Sampling .......................................................... 135 Serial Port Enable (SPEN Bit) ................................. 131 Synchronous Master Mode ...................................... 148 Associated Registers, Reception ..................... 151 Associated Registers, Transmit ....................... 149 Reception ........................................................ 150 Transmission ................................................... 148 Synchronous Slave Mode ........................................ 152 Associated Registers, Receive ........................ 153 Associated Registers, Transmit ....................... 152 Reception ........................................................ 153 Transmission ................................................... 152© 2007 Microchip Technology Inc. DS39605F-page 297 PIC18F1220/1320 F Fail-Safe Clock Monitor .................................................... 171 Exiting Operation ..................................................... 183 Interrupts in Power Managed Modes ....................... 183 POR or Wake from Sleep ........................................ 184 WDT During Oscillator Failure ................................. 182 Fail-Safe Clock Monitor (FSCM) ...................................... 182 Fast Register Stack ............................................................ 44 Firmware Instructions ....................................................... 191 Flash Program Memory ...................................................... 57 Associated Registers ................................................. 65 Control Registers ....................................................... 58 Erase Sequence ........................................................ 62 Erasing ....................................................................... 62 Operation During Code-Protect ................................. 65 Reading ...................................................................... 61 Table Latch ................................................................ 60 Table Pointer .............................................................. 60 Boundaries Based on Operation ........................ 60 Table Pointer Boundaries .......................................... 60 Table Reads and Table Writes .................................. 57 Write Sequence ......................................................... 63 Writing to .................................................................... 63 Unexpected Termination .................................... 65 Write Verify ........................................................ 65 G GOTO ............................................................................... 212 H Hardware Multiplier ............................................................ 71 Introduction ................................................................ 71 Operation ................................................................... 71 Performance Comparison .......................................... 71 I I/O Ports ............................................................................. 87 ID Locations ............................................................. 171, 188 INCF ................................................................................. 212 INCFSZ ............................................................................ 213 In-Circuit Debugger .......................................................... 188 In-Circuit Serial Programming (ICSP) ...................... 171, 188 Indirect Addressing ............................................................ 54 INDF and FSR Registers ........................................... 53 Operation ................................................................... 53 Indirect Addressing Operation ............................................ 54 Indirect File Operand .......................................................... 47 INFSNZ ............................................................................ 213 Initialization Conditions for All Registers ...................... 36–38 Instruction Cycle ................................................................. 45 Instruction Flow/Pipelining ................................................. 45 Instruction Set .................................................................. 191 ADDLW .................................................................... 197 ADDWF .................................................................... 197 ADDWFC ................................................................. 198 ANDLW .................................................................... 198 ANDWF .................................................................... 199 BC ............................................................................ 199 BCF .......................................................................... 200 BN ............................................................................ 200 BNC ......................................................................... 201 BNN ......................................................................... 201 BNOV ....................................................................... 202 BNZ .......................................................................... 202 BOV ......................................................................... 205 BRA ......................................................................... 203 BSF .......................................................................... 203 BTFSC ..................................................................... 204 BTFSS ..................................................................... 204 BTG ......................................................................... 205 BZ ............................................................................ 206 CALL ........................................................................ 206 CLRF ....................................................................... 207 CLRWDT ................................................................. 207 COMF ...................................................................... 208 CPFSEQ .................................................................. 208 CPFSGT .................................................................. 209 CPFSLT ................................................................... 209 DAW ........................................................................ 210 DCFSNZ .................................................................. 211 DECF ....................................................................... 210 DECFSZ .................................................................. 211 General Format ........................................................ 193 GOTO ...................................................................... 212 INCF ........................................................................ 212 INCFSZ .................................................................... 213 INFSNZ .................................................................... 213 IORLW ..................................................................... 214 IORWF ..................................................................... 214 LFSR ....................................................................... 215 MOVF ...................................................................... 215 MOVFF .................................................................... 216 MOVLB .................................................................... 216 MOVLW ................................................................... 217 MOVWF ................................................................... 217 MULLW .................................................................... 218 MULWF .................................................................... 218 NEGF ....................................................................... 219 NOP ......................................................................... 219 POP ......................................................................... 220 PUSH ....................................................................... 220 RCALL ..................................................................... 221 RESET ..................................................................... 221 RETFIE .................................................................... 222 RETLW .................................................................... 222 RETURN .................................................................. 223 RLCF ....................................................................... 223 RLNCF ..................................................................... 224 RRCF ....................................................................... 224 RRNCF .................................................................... 225 SETF ....................................................................... 225 SLEEP ..................................................................... 226 SUBFWB ................................................................. 226 SUBLW .................................................................... 227 SUBWF .................................................................... 227 SUBWFB ................................................................. 228 SWAPF .................................................................... 228 TBLRD ..................................................................... 229 TBLWT .................................................................... 230 TSTFSZ ................................................................... 231 XORLW ................................................................... 231 XORWF ................................................................... 232 Summary Table ....................................................... 194 INTCON Register RBIF Bit ..................................................................... 90 INTCON Registers ............................................................. 75PIC18F1220/1320 DS39605F-page 298 © 2007 Microchip Technology Inc. Internal Oscillator Block .....................................................14 Adjustment ................................................................. 14 INTIO Modes .............................................................. 14 INTRC Output Frequency .......................................... 14 OSCTUNE Register ...................................................14 Internal RC Oscillator Use with WDT .......................................................... 180 Internet Address ............................................................... 302 Interrupt Sources .............................................................. 171 A/D Conversion Complete ........................................ 159 Capture Complete (CCP) ......................................... 116 Compare Complete (CCP) ....................................... 117 Interrupt-on-Change (RB7:RB4) ................................90 INTn Pin ..................................................................... 85 PORTB, Interrupt-on-Change .................................... 85 TMR0 ......................................................................... 85 TMR0 Overflow ........................................................ 101 TMR1 Overflow ........................................................ 103 TMR2 to PR2 Match .................................................110 TMR2 to PR2 Match (PWM) ............................ 109, 119 TMR3 Overflow ................................................ 111, 113 Interrupts ............................................................................ 73 Enable Bits (CCP1IE Bit) .................................................... 116 Flag Bits CCP1 Flag (CCP1IF Bit) .................................. 116 CCP1IF Flag (CCP1IF Bit) ............................... 117 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ........................................... 90 Logic ........................................................................... 74 INTOSC Frequency Drift .................................................... 30 IORLW ............................................................................. 214 IORWF ............................................................................. 214 IPR Registers ..................................................................... 82 L LFSR ................................................................................ 215 Low-Voltage Detect .......................................................... 165 Characteristics ......................................................... 253 Effects of a Reset ..................................................... 169 Operation ................................................................. 168 Current Consumption ....................................... 169 Reference Voltage Set Point ............................169 Operation During Sleep ............................................ 169 LVD. See Low-Voltage Detect. ........................................ 165 M Memory Organization ......................................................... 41 Data Memory .............................................................. 47 Program Memory ....................................................... 41 Memory Programming Requirements ..............................252 Microchip Internet Web Site ............................................. 302 Migration from Baseline to Enhanced Devices ................ 292 Migration from High-End to Enhanced Devices ............... 293 Migration from Mid-Range to Enhanced Devices ............. 293 MOVF ............................................................................... 215 MOVFF ............................................................................. 216 MOVLB ............................................................................. 216 MOVLW ............................................................................ 217 MOVWF ........................................................................... 217 MPLAB ASM30 Assembler, Linker, Librarian .................. 234 MPLAB ICD 2 In-Circuit Debugger ................................... 235 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ................................... 235 MPLAB Integrated Development Environment Software .............................................. 233 MPLAB PM3 Device Programmer ................................... 235 MPLAB REAL ICE In-Circuit Emulator System ................ 235 MPLINK Object Linker/MPLIB Object Librarian ............... 234 MULLW ............................................................................ 218 MULWF ............................................................................ 218 N NEGF ............................................................................... 219 New Core Features Multiple Oscillator Options and Features ..................... 5 nanoWatt Technology .................................................. 5 NOP ................................................................................. 219 O Opcode Field Descriptions ............................................... 192 OPTION_REG Register PSA Bit .................................................................... 101 T0CS Bit .................................................................. 101 T0PS2:T0PS0 Bits ................................................... 101 T0SE Bit ................................................................... 101 Oscillator Configuration ...................................................... 11 Crystal/Ceramic Resonator ........................................ 11 EC .............................................................................. 11 ECIO .......................................................................... 11 External Clock Input ................................................... 13 HS .............................................................................. 11 HSPLL ..................................................................11, 12 INTIO1 ....................................................................... 11 INTIO2 ....................................................................... 11 LP .............................................................................. 11 RC .........................................................................11, 13 RCIO .......................................................................... 11 XT .............................................................................. 11 Oscillator Selection .......................................................... 171 Oscillator Start-up Timer (OST) ............................18, 34, 171 Oscillator Switching ............................................................ 15 Oscillator Transitions ......................................................... 18 Oscillator, Timer1 ......................................................103, 113 Oscillator, Timer3 ............................................................. 111 Other Special Features ........................................................ 5 P Packaging ........................................................................ 285 Details ...................................................................... 286 Marking Information ................................................. 285 PICSTART Plus Development Programmer .................... 236 PIE Registers ..................................................................... 80 Pin Functions MCLR/Vpp/RA5 ........................................................... 8 OSC1/CLKI/RA7 .......................................................... 8 OSC2/CLKO/RA6 ........................................................ 8 RA0/AN0 ...................................................................... 8 RA1/AN1/LVDIN .......................................................... 8 RA2/AN2/Vref- ............................................................. 8 RA3/AN3/VREF+ ........................................................... 8 RA4/T0CKI ................................................................... 8 RB0/AN4/INT0 ............................................................. 9 RB1/AN5/TX/CK/INT1 ................................................. 9 RB2/P1B/INT2 ............................................................. 9 RB3/CCP1/P1A ........................................................... 9 RB4/AN6/RX/DT/KBI0 ................................................. 9 RB5/PGM/KBI1 ............................................................ 9 RB6/PGC/T1OSO/T13CKI/P1C/KBI2 .......................... 9 RB7/PGD/T1OSI/P1D/KBI3 ......................................... 9 Vdd .............................................................................. 9 Vss ............................................................................... 9© 2007 Microchip Technology Inc. DS39605F-page 299 PIC18F1220/1320 Pinout I/O Descriptions PIC18F1220/1320 ........................................................ 8 PIR Registers ..................................................................... 78 PLL Lock Time-out ............................................................. 34 Pointer, FSR ....................................................................... 53 POP .................................................................................. 220 POR. See Power-on Reset. PORTA Associated Registers ................................................. 89 Functions ................................................................... 89 LATA Register ............................................................ 87 PORTA Register ........................................................ 87 TRISA Register .......................................................... 87 PORTB Associated Registers ................................................. 98 Functions ................................................................... 98 LATB Register ............................................................ 90 PORTB Register ........................................................ 90 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........................................................... 90 TRISB Register .......................................................... 90 Postscaler Timer2 ...................................................................... 109 WDT Assignment (PSA Bit) ...................................... 101 Rate Select (T0PS2:T0PS0 Bits) ..................... 101 Power Managed Modes ..................................................... 19 Comparison between Run and Idle Modes ................ 20 Entering ...................................................................... 20 Idle Modes ................................................................. 21 Multiple Sleep Commands ......................................... 20 Run Modes ................................................................. 26 Selecting .................................................................... 19 Sleep Mode ................................................................ 21 Summary (table) ........................................................ 19 Wake from .................................................................. 28 Power-on Reset (POR) .............................................. 34, 171 Power-up Delays ................................................................ 18 Power-up Timer (PWRT) .......................................18, 34, 171 Prescaler Capture .................................................................... 117 Timer0 ...................................................................... 101 Assignment (PSA Bit) ...................................... 101 Rate Select (T0PS2:T0PS0 Bits) ..................... 101 Timer2 ...................................................................... 119 Product Identification System ........................................... 304 Program Counter PCL Register .............................................................. 44 PCLATH Register ...................................................... 44 PCLATU Register ...................................................... 44 Program Memory Instructions in ............................................................. 46 Interrupt Vector .......................................................... 41 Map and Stack for PIC18F1220 ................................. 41 Map and Stack for PIC18F1320 ................................. 41 Reset Vector .............................................................. 41 Program Verification and Code Protection ....................... 185 Associated Registers ............................................... 185 Configuration Register ............................................. 188 Data EEPROM ......................................................... 188 Program Memory ..................................................... 186 Programming, Device Instructions ................................... 191 PUSH ............................................................................... 220 PUSH and POP Instructions .............................................. 43 PWM (CCP Module) CCPR1H:CCPR1L Registers ................................... 119 Duty Cycle ............................................................... 119 Example Frequencies/Resolutions .......................... 119 Period ...................................................................... 119 TMR2 to PR2 Match .........................................109, 119 PWM (ECCP Module) ...................................................... 119 Associated Registers ............................................... 130 Direction Change in Full-Bridge Output Mode ......... 124 Effects of a Reset .................................................... 129 Enhanced PWM Auto-Shutdown ............................. 126 Full-Bridge Application Example .............................. 124 Full-Bridge PWM Output (Active-High) Diagram ..... 123 Half-Bridge Output (Active-High) Diagram ............... 122 Half-Bridge Output Mode Applications Example ...... 122 Operation in Low-Power Modes .............................. 129 Output Configurations .............................................. 119 Output Relationships (Active-High) .......................... 120 Output Relationships (Active-Low) .......................... 121 Programmable Dead-Band Delay ............................ 126 PWM Direction Change (Active-High) Diagram ....... 125 PWM Direction Change at Near 100% Duty Cycle (Active-High) Diagram ......... 125 Setup for PWM Operation ........................................ 129 Start-up Considerations ........................................... 128 Q Q Clock ............................................................................ 119 R RAM. See Data Memory. RCALL ............................................................................. 221 RCIO Oscillator .................................................................. 13 RCON Register Bit Status During Initialization .................................... 35 RCSTA Register SPEN Bit .................................................................. 131 Reader Response ............................................................ 303 Register File ....................................................................... 47 Register File Summary .................................................50–51 Registers ADCON0 (A/D Control 0) ......................................... 155 ADCON1 (A/D Control 1) ......................................... 156 ADCON2 (A/D Control 2) ......................................... 157 BAUDCTL (Baud Rate Control) ............................... 134 CCP1CON (Enhanced CCP1 Control) .................... 115 CONFIG1H (Configuration 1 High) .......................... 172 CONFIG2H (Configuration 2 High) .......................... 174 CONFIG2L (Configuration 2 Low) ........................... 173 CONFIG3H (Configuration 3 High) .......................... 175 CONFIG4L (Configuration 4 Low) ........................... 175 CONFIG5H (Configuration 5 High) .......................... 176 CONFIG5L (Configuration 5 Low) ........................... 176 CONFIG6H (Configuration 6 High) .......................... 177 CONFIG6L (Configuration 6 Low) ........................... 177 CONFIG7H (Configuration 7 High) .......................... 178 CONFIG7L (Configuration 7 Low) ........................... 178 DEVID1 (Device ID 1) .............................................. 179 DEVID2 (Device ID 2) .............................................. 179 ECCPAS (ECCP Auto-Shutdown Control) .............. 127 EECON1 (Data EEPROM Control 1) ....................59, 68 INTCON (Interrupt Control) ........................................ 75 INTCON2 (Interrupt Control 2) ................................... 76 INTCON3 (Interrupt Control 3) ................................... 77 IPR1 (Peripheral Interrupt Priority 1) ......................... 82 IPR2 (Peripheral Interrupt Priority 2) ......................... 83 LVDCON (LVD Control) ........................................... 167 OSCCON (Oscillator Control) .................................... 17PIC18F1220/1320 DS39605F-page 300 © 2007 Microchip Technology Inc. OSCTUNE (Oscillator Tuning) ................................... 15 PIE1 (Peripheral Interrupt Enable 1) .......................... 80 PIE2 (Peripheral Interrupt Enable 2) .......................... 81 PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 78 PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 79 PWM1CON (PWM Configuration) ............................126 RCON (Reset Control) ......................................... 56, 84 RCSTA (Receive Status and Control) ...................... 133 Status ......................................................................... 55 STKPTR (Stack Pointer) ............................................ 43 T0CON (Timer0 Control) ............................................ 99 T1CON (Timer 1 Control) ......................................... 103 T2CON (Timer 2 Control) ......................................... 109 T3CON (Timer3 Control) .......................................... 111 TXSTA (Transmit Status and Control) ..................... 132 WDTCON (Watchdog Timer Control) ....................... 180 RESET ............................................................................. 221 Reset .......................................................................... 33, 171 RETFIE ............................................................................ 222 RETLW ............................................................................. 222 RETURN .......................................................................... 223 Return Address Stack ........................................................ 42 and Associated Registers .......................................... 42 Return Stack Pointer (STKPTR) ........................................ 42 Revision History ............................................................... 291 RLCF ................................................................................ 223 RLNCF ............................................................................. 224 RRCF ............................................................................... 224 RRNCF ............................................................................. 225 S SETF ................................................................................ 225 SLEEP .............................................................................. 226 Sleep OSC1 and OSC2 Pin States ...................................... 18 Software Simulator (MPLAB SIM) .................................... 234 Special Event Trigger. See Compare Special Features of the CPU ............................................ 171 Configuration Registers .................................... 172–178 Special Function Registers ................................................ 49 Map ............................................................................ 49 Stack Full/Underflow Resets .............................................. 43 SUBFWB .......................................................................... 226 SUBLW ............................................................................ 227 SUBWF ............................................................................ 227 SUBWFB .......................................................................... 228 SWAPF ............................................................................ 228 T TABLAT Register ............................................................... 60 Table Pointer Operations (table) ........................................ 60 TBLPTR Register ............................................................... 60 TBLRD ............................................................................. 229 TBLWT ............................................................................. 230 Time-out Sequence ............................................................ 34 Timer0 ................................................................................ 99 16-Bit Mode Timer Reads and Writes ...................... 101 Associated Registers ...............................................101 Clock Source Edge Select (T0SE Bit) ...................... 101 Clock Source Select (T0CS Bit) ............................... 101 Operation ................................................................. 101 Overflow Interrupt ..................................................... 101 Prescaler. See Prescaler, Timer0. Switching Prescaler Assignment ..............................101 Timer1 .............................................................................. 103 16-Bit Read/Write Mode .......................................... 106 Associated Registers ............................................... 108 Interrupt ................................................................... 106 Operation ................................................................. 104 Oscillator ...........................................................103, 105 Layout Considerations ..................................... 106 Overflow Interrupt .................................................... 103 Resetting, Using a Special Event Trigger Output (CCP) ................................................... 106 Special Event Trigger (CCP) ................................... 117 TMR1H Register ...................................................... 103 TMR1L Register ....................................................... 103 Use as a Real-Time Clock ....................................... 107 Timer2 .............................................................................. 109 Associated Registers ............................................... 110 Operation ................................................................. 109 Output ...................................................................... 110 Postscaler. See Postscaler, Timer2. PR2 Register ....................................................109, 119 Prescaler. See Prescaler, Timer2. TMR2 Register ......................................................... 109 TMR2 to PR2 Match Interrupt ...................109, 110, 119 Timer3 .............................................................................. 111 Associated Registers ............................................... 113 Operation ................................................................. 112 Oscillator ...........................................................111, 113 Overflow Interrupt .............................................111, 113 Special Event Trigger (CCP) ................................... 113 TMR3H Register ...................................................... 111 TMR3L Register ....................................................... 111 Timing Diagrams A/D Conversion ........................................................ 265 Asynchronous Reception ......................................... 144 Asynchronous Transmission .................................... 141 Asynchronous Transmission (Back to Back) ........... 142 Auto-Wake-up Bit (WUE) During Normal Operation ............................................ 145 Auto-Wake-up Bit (WUE) During Sleep ................... 145 Brown-out Reset (BOR) ........................................... 260 Capture/Compare/PWM (All CCP Modules) ............ 262 CLKO and I/O .......................................................... 259 Clock/Instruction Cycle .............................................. 45 EUSART Synchronous Receive (Master/Slave) ................................................. 264 EUSART SynchronousTransmission (Master/Slave) ................................................. 263 External Clock (All Modes Except PLL) ................... 257 Fail-Safe Clock Monitor ........................................... 183 Low-Voltage Detect ................................................. 168 Low-Voltage Detect Characteristics ......................... 253 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) .................................... 128 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ..................................... 128 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ..... 260 Send Break Character Sequence ............................ 147 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 40 Synchronous Reception (Master Mode, SREN) ..................................... 150 Synchronous Transmission ..................................... 148 Synchronous Transmission (Through TXEN) .......... 149© 2007 Microchip Technology Inc. DS39605F-page 301 PIC18F1220/1320 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) ........................................... 40 Time-out Sequence on Power-up (MCLR Not Tied to Vdd), Case 1 ....................... 39 Time-out Sequence on Power-up (MCLR Not Tied to Vdd), Case 2 ....................... 39 Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise pwrt) ................... 39 Timer0 and Timer1 External Clock .......................... 261 Transition for Entry to SEC_IDLE Mode .................... 24 Transition for Entry to SEC_RUN Mode .................... 26 Transition for Entry to Sleep Mode ............................ 22 Transition for Two-Speed Start-up (INTOSC to HSPLL) ......................................... 181 Transition for Wake from PRI_IDLE Mode ................. 23 Transition for Wake from RC_RUN Mode (RC_RUN to PRI_RUN) ..................................... 25 Transition for Wake from SEC_RUN Mode (HSPLL) ............................................................. 24 Transition for Wake from Sleep (HSPLL) ................... 22 Transition to PRI_IDLE Mode .................................... 23 Transition to RC_IDLE Mode ..................................... 25 Transition to RC_RUN Mode ..................................... 27 Timing Diagrams and Specifications ................................ 257 Capture/Compare/PWM Requirements (All CCP Modules) ........................................... 263 CLKO and I/O Requirements ................................... 259 EUSART Synchronous Receive Requirements ....... 264 EUSART Synchronous Transmission Requirements ............................ 263 External Clock Requirements .................................. 257 Internal RC Accuracy ............................................... 258 PLL Clock, HS/HSPLL Mode (VDD = 4.2V to 5.5V) ........................................ 258 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ....................... 261 Timer0 and Timer1 External Clock Requirements ................................................... 262 Top-of-Stack Access .......................................................... 42 TSTFSZ ........................................................................... 231 Two-Speed Start-up ..................................................171, 181 Two-Word Instructions ....................................................... 46 Example Cases .......................................................... 46 TXSTA Register BRGH Bit ................................................................. 135 W Watchdog Timer (WDT) ............................................171, 180 Associated Registers ............................................... 181 Control Register ....................................................... 180 During Oscillator Failure .......................................... 182 Programming Considerations .................................. 180 WWW Address ................................................................ 302 WWW, On-Line Support ...................................................... 4 X XORLW ............................................................................ 231 XORWF ........................................................................... 232PIC18F1220/1320 DS39605F-page 302 © 2007 Microchip Technology Inc. NOTES:© 2007 Microchip Technology Inc. DS39605F-page 303 PIC18F1220/1320 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support • Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.comPIC18F1220/1320 DS39605F-page 304 © 2007 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Device: Literature Number: Questions: FAX: (______) _________ - _________ PIC18F1220/1320 DS39605F 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document?© 2007 Microchip Technology Inc. DS39605F-page 305 PIC18F1220/1320 PIC18F1220/1320 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. − X /XX XXX Temperature Package Pattern Range Device Device PIC18F1220/1320(1), PIC18F1220/1320T(2); VDD range 4.2V to 5.5V PIC18LF1220/1320(1), PIC18LF1220/1320T(2); VDD range 2.5V to 5.5V Temperature Range I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package SO = SOIC SS = SSOP P = PDIP ML = QFN Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) Examples: a) PIC18LF1320-I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. b) PIC18LF1220-I/SO = Industrial temp., SOIC package, Extended VDD limits. Note 1: F = Standard Voltage range LF = Wide Voltage Range 2: T = in tape and reel – SOIC package onlyDS39605F-page 306 © 2007 Microchip Technology Inc. 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Pin Configurations Figure 1-1. Pinout ATtiny25/45/85 1.1 Pin Descriptions 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB5:PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. 1 2 3 4 8 7 6 5 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 GND VCC PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2) PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0) PDIP/SOIC/TSSOP 1 2 3 4 5 QFN/MLF 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 DNC DNC GND DNC DNC DNC DNC DNC DNC DNC NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect NOTE: TSSOP only for ATtiny45/V (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 DNC DNC (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 VCC PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2) DNC PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)ATtiny25/45/85 [DATASHEET] 3 2586QS–AVR–08/2013 Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in “Alternate Functions of Port B” on page 60. On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in ATtiny15 Compatibility Mode for supporting the backward compatibility with ATtiny15. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 21-4 on page 165. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin.ATtiny25/45/85 [DATASHEET] 4 2586QS–AVR–08/2013 2. Overview The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. PROGRAM COUNTER CALIBRATED INTERNAL OSCILLATOR WATCHDOG TIMER STACK POINTER PROGRAM FLASH SRAM MCU CONTROL REGISTER GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER/ COUNTER0 SERIAL UNIVERSAL INTERFACE TIMER/ COUNTER1 INSTRUCTION DECODER DATA DIR. REG.PORT B DATA REGISTER PORT B PROGRAMMING LOGIC TIMING AND CONTROL MCU STATUS REGISTER STATUS REGISTER ALU PORT B DRIVERS PB[0:5] VCC GND CONTROL LINES 8-BIT DATABUS Z ADC / ANALOG COMPARATOR INTERRUPT UNIT DATA EEPROM OSCILLATORS Y X RESETATtiny25/45/85 [DATASHEET] 5 2586QS–AVR–08/2013 The ATtiny25/45/85 provides the following features: 2/4/8K bytes of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.ATtiny25/45/85 [DATASHEET] 6 2586QS–AVR–08/2013 3. About 3.1 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map. 3.3 Capacitive Touch Sensing Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition methods. Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to retrieve channel information and determine the state of the touch sensor. The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of implementation, refer to the QTouch Library User Guide – also available from the Atmel website. 3.4 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.ATtiny25/45/85 [DATASHEET] 7 2586QS–AVR–08/2013 4. Register Summary Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F SREG I T H S V N Z C page 8 0x3E SPH – – – – – – SP9 SP8 page 11 0x3D SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 11 0x3C Reserved – 0x3B GIMSK – INT0 PCIE – – – – – page 51 0x3A GIFR – INTF0 PCIF – – – – – page 52 0x39 TIMSK – OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – pages 81, 102 0x38 TIFR – OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 – page 81 0x37 SPMCSR – – RSIG CTPB RFLB PGWRT PGERS SPMEN page 145 0x36 Reserved – 0x35 MCUCR BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 pages 37, 51, 64 0x34 MCUSR – – – – WDRF BORF EXTRF PORF page 44, 0x33 TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 page 79 0x32 TCNT0 Timer/Counter0 page 80 0x31 OSCCAL Oscillator Calibration Register page 31 0x30 TCCR1 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 pages 89, 100 0x2F TCNT1 Timer/Counter1 pages 91, 102 0x2E OCR1A Timer/Counter1 Output Compare Register A pages 91, 102 0x2D OCR1C Timer/Counter1 Output Compare Register C pages 91, 102 0x2C GTCCR TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 pages 77, 90, 101 0x2B OCR1B Timer/Counter1 Output Compare Register B page 92 0x2A TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – WGM01 WGM00 page 77 0x29 OCR0A Timer/Counter0 – Output Compare Register A page 80 0x28 OCR0B Timer/Counter0 – Output Compare Register B page 81 0x27 PLLCSR LSM – – – – PCKE PLLE PLOCK pages 94, 103 0x26 CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 32 0x25 DT1A DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 page 107 0x24 DT1B DT1BH3 DT1BH2 DT1BH1 DT1BH0 DT1BL3 DT1BL2 DT1BL1 DT1BL0 page 107 0x23 DTPS1 - - - - - - DTPS11 DTPS10 page 106 0x22 DWDR DWDR[7:0] page 140 0x21 WDTCR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 page 45 0x20 PRR – PRTIM1 PRTIM0 PRUSI PRADC page 36 0x1F EEARH EEAR8 page 20 0x1E EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 page 21 0x1D EEDR EEPROM Data Register page 21 0x1C EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE page 21 0x1B Reserved – 0x1A Reserved – 0x19 Reserved – 0x18 PORTB – – PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 64 0x17 DDRB – – DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 64 0x16 PINB – – PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 64 0x15 PCMSK – – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 page 52 0x14 DIDR0 – – ADC0D ADC2D ADC3D ADC1D AIN1D AIN0D pages 121, 138 0x13 GPIOR2 General Purpose I/O Register 2 page 10 0x12 GPIOR1 General Purpose I/O Register 1 page 10 0x11 GPIOR0 General Purpose I/O Register 0 page 10 0x10 USIBR USI Buffer Register page 115 0x0F USIDR USI Data Register page 115 0x0E USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 page 115 0x0D USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC page 116 0x0C Reserved – 0x0B Reserved – 0x0A Reserved – 0x09 Reserved – 0x08 ACSR ACD ACBG ACO ACI ACIE – ACIS1 ACIS0 page 120 0x07 ADMUX REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0 page 134 0x06 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 136 0x05 ADCH ADC Data Register High Byte page 137 0x04 ADCL ADC Data Register Low Byte page 137 0x03 ADCSRB BIN ACME IPR – – ADTS2 ADTS1 ADTS0 pages 120, 137 0x02 Reserved – 0x01 Reserved – 0x00 Reserved –ATtiny25/45/85 [DATASHEET] 8 2586QS–AVR–08/2013 should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.ATtiny25/45/85 [DATASHEET] 9 2586QS–AVR–08/2013 5. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd  Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd  Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl  Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd  Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd  Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd  Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd  Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl  Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd Rd  Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd  Rd K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd  Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd  Rd  Rr Z,N,V 1 COM Rd One’s Complement Rd  0xFF  Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd  0x00  Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd  Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd  Rd  (0xFF - K) Z,N,V 1 INC Rd Increment Rd  Rd + 1 Z,N,V 1 DEC Rd Decrement Rd  Rd  1 Z,N,V 1 TST Rd Test for Zero or Minus Rd  Rd  Rd Z,N,V 1 CLR Rd Clear Register Rd  Rd  Rd Z,N,V 1 SER Rd Set Register Rd  0xFF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC  Z None 2 RCALL k Relative Subroutine Call PC  PC + k + 1 None 3 ICALL Indirect Call to (Z) PC  Z None 3 RET Subroutine Return PC  STACK None 4 RETI Interrupt Return PC  STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd  Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd  Rr  C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd  K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC  PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC  PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC  PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC  PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC  PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC  PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC  PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC  PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC  PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC  PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC  PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC  PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N  V= 0) then PC  PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N  V= 1) then PC  PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC  PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC  PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC  PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC  PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC  PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC  PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC  PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC  PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b)  1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b)  0 None 2 LSL Rd Logical Shift Left Rd(n+1)  Rd(n), Rd(0)  0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n)  Rd(n+1), Rd(7)  0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n)  Rd(n+1), n=0..6 Z,C,N,V 1ATtiny25/45/85 [DATASHEET] 10 2586QS–AVR–08/2013 SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1 BSET s Flag Set SREG(s)  1 SREG(s) 1 BCLR s Flag Clear SREG(s)  0 SREG(s) 1 BST Rr, b Bit Store from Register to T T  Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b)  T None 1 SEC Set Carry C  1 C1 CLC Clear Carry C  0 C 1 SEN Set Negative Flag N  1 N1 CLN Clear Negative Flag N  0 N 1 SEZ Set Zero Flag Z  1 Z1 CLZ Clear Zero Flag Z  0 Z 1 SEI Global Interrupt Enable I  1 I1 CLI Global Interrupt Disable I 0 I 1 SES Set Signed Test Flag S  1 S1 CLS Clear Signed Test Flag S  0 S 1 SEV Set Twos Complement Overflow. V  1 V1 CLV Clear Twos Complement Overflow V  0 V 1 SET Set T in SREG T  1 T1 CLT Clear T in SREG T  0 T 1 SEH Set Half Carry Flag in SREG H  1 H1 CLH Clear Half Carry Flag in SREG H  0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd  Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd  Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd  K None 1 LD Rd, X Load Indirect Rd  (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd  (X), X  X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X  X - 1, Rd  (X) None 2 LD Rd, Y Load Indirect Rd  (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd  (Y), Y  Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y  Y - 1, Rd  (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd  (Y + q) None 2 LD Rd, Z Load Indirect Rd  (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd  (Z), Z  Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z  Z - 1, Rd  (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd  (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd  (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X  X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X  X - 1, (X)  Rr None 2 ST Y, Rr Store Indirect (Y)  Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y)  Rr, Y  Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y  Y - 1, (Y)  Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q)  Rr None 2 ST Z, Rr Store Indirect (Z)  Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z)  Rr, Z  Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z  Z - 1, (Z)  Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q)  Rr None 2 STS k, Rr Store Direct to SRAM (k)  Rr None 2 LPM Load Program Memory R0  (Z) None 3 LPM Rd, Z Load Program Memory Rd  (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd  (Z), Z  Z+1 None 3 SPM Store Program Memory (z)  R1:R0 None IN Rd, P In Port Rd  P None 1 OUT P, Rr Out Port P  Rr None 1 PUSH Rr Push Register on Stack STACK  Rr None 2 POP Rd Pop Register from Stack Rd  STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1 BREAK Break For On-chip Debug Only None N/A Mnemonics Operands Description Operation Flags #ClocksATtiny25/45/85 [DATASHEET] 11 2586QS–AVR–08/2013 6. Ordering Information Notes: 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 163. 2. All Pb-free, halide-free, fully green, and comply with European directive for Restriction of Hazardous Substances (RoHS). 3. Code indicators: H = NiPdAu lead finish, U/N = matte tin, R = tape & reel. 4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities. 5. For characteristics, see “Appendix A – Specification at 105C”. 6. For characteristics, see “Appendix B – Specification at 125C”. 6.1 ATtiny25 Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3) 10 1.8 – 5.5 Industrial (-40C to +85C) (4) 8P3 ATtiny25V-10PU 8S2 ATtiny25V-10SU ATtiny25V-10SUR ATtiny25V-10SH ATtiny25V-10SHR S8S1 ATtiny25V-10SSU ATtiny25V-10SSUR ATtiny25V-10SSH ATtiny25V-10SSHR 20M1 ATtiny25V-10MU ATtiny25V-10MUR Industrial (-40C to +105C) (5) 8S2 ATtiny25V-10SN ATtiny25V-10SNR S8S1 ATtiny25V-10SSN ATtiny25V-10SSNR Industrial (-40C to +125C) (6) 20M1 ATtiny25V-10MF ATtiny25V-10MFR 20 2.7 – 5.5 Industrial (-40C to +85C) (4) 8P3 ATtiny25-20PU 8S2 ATtiny25-20SU ATtiny25-20SUR ATtiny25-20SH ATtiny25-20SHR S8S1 ATtiny25-20SSU ATtiny25-20SSUR ATtiny25-20SSH ATtiny25-20SSHR 20M1 ATtiny25-20MU ATtiny25-20MUR Industrial (-40C to +105C) (5) 8S2 ATtiny25-20SN ATtiny25-20SNR S8S1 ATtiny25-20SSN ATtiny25-20SSNR Industrial (-40C to +125C) (6) 20M1 ATtiny25-20MF ATtiny25-20MFR Package Types 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) S8S1 8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC) 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)ATtiny25/45/85 [DATASHEET] 12 2586QS–AVR–08/2013 Notes: 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 163. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). 3. Code indicators: – H: NiPdAu lead finish – U: matte tin – R: tape & reel 4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 6.2 ATtiny45 Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3) 10 1.8 – 5.5 Industrial (-40C to +85C) (4) 8P3 ATtiny45V-10PU 8S2 ATtiny45V-10SU ATtiny45V-10SUR ATtiny45V-10SH ATtiny45V-10SHR 8X ATtiny45V-10XU ATtiny45V-10XUR 20M1 ATtiny45V-10MU ATtiny45V-10MUR 20 2.7 – 5.5 Industrial (-40C to +85C) (4) 8P3 ATtiny45-20PU 8S2 ATtiny45-20SU ATtiny45-20SUR ATtiny45-20SH ATtiny45-20SHR 8X ATtiny45-20XU ATtiny45-20XUR 20M1 ATtiny45-20MU ATtiny45-20MUR Package Types 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 8X 8-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline Package (TSSOP) 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)ATtiny25/45/85 [DATASHEET] 13 2586QS–AVR–08/2013 Notes: 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 163. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). 3. Code indicators: – H: NiPdAu lead finish – U: matte tin – R: tape & reel 4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 6.3 ATtiny85 Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3) 10 1.8 – 5.5 Industrial (-40C to +85C) (4) 8P3 ATtiny85V-10PU 8S2 ATtiny85V-10SU ATtiny85V-10SUR ATtiny85V-10SH ATtiny85V-10SHR 20M1 ATtiny85V-10MU ATtiny85V-10MUR 20 2.7 – 5.5 Industrial (-40C to +85C) (4) 8P3 ATtiny85-20PU 8S2 ATtiny85-20SU ATtiny85-20SUR ATtiny85-20SH ATtiny85-20SHR 20M1 ATtiny85-20MU ATtiny85-20MUR Package Types 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)ATtiny25/45/85 [DATASHEET] 14 2586QS–AVR–08/2013 7. Packaging Information 7.1 8P3 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B D D1 E E1 e b2 L b A2 A 1 N eA c b3 4 PLCS Top View Side View End View COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). A 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC 4 L 0.115 0.130 0.150 2ATtiny25/45/85 [DATASHEET] 15 2586QS–AVR–08/2013 7.2 8S2 TITLE GPC DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com STN F 8S2 8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ) 4/15/08 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 2 E 7.70 8.26 L 0.51 0.85 θ 0° 8° e 1.27 BSC 3 θ 1 N E TOP VIEW TOP VIEW C E1 END VIEW END VIEW A b L A1 e D SIDE VIEW SIDE VIEWATtiny25/45/85 [DATASHEET] 16 2586QS–AVR–08/2013 7.3 S8S1 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline (JEDEC SOIC) 7/28/03 S8S1 A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. E 5.79 6.20 E1 3.81 3.99 A 1.35 1.75 A1 0.1 0.25 D 4.80 4.98 C 0.17 0.25 b 0.31 0.51 L 0.4 1.27 e 1.27 BSC 0o 8o Top View Side View End View 1 N C A A1 b L e D E1 EATtiny25/45/85 [DATASHEET] 17 2586QS–AVR–08/2013 7.4 8X TITLE DRAWING NO. R REV. Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153AC. 2325 Orchard Parkway San Jose, CA 95131 4/14/05 8X, 8-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) 8X A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 1.05 1.10 1.20 A1 0.05 0.10 0.15 b 0.25 – 0.30 C – 0.127 – D 2.90 3.05 3.10 E1 4.30 4.40 4.50 E 6.20 6.40 6.60 e 0.65 TYP L 0.50 0.60 0.70 Ø 0o – 8o C A b L A1 D Side View Top View End View E 1 E1 e ØATtiny25/45/85 [DATASHEET] 18 2586QS–AVR–08/2013 7.5 20M1 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 20M1 B 10/27/04 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 0.20 REF b 0.18 0.23 0.30 D 4.00 BSC D2 2.45 2.60 2.75 E 4.00 BSC E2 2.45 2.60 2.75 e 0.50 BSC L 0.35 0.40 0.55 SIDE VIEW Pin 1 ID Pin #1 Notch (0.20 R) BOTTOM VIEW TOP VIEW Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D E e A2 A1 A D2 E2 0.08 C L 1 2 3 b 1 2 3ATtiny25/45/85 [DATASHEET] 19 2586QS–AVR–08/2013 8. Errata 8.1 Errata ATtiny25 The revision letter in this section refers to the revision of the ATtiny25 device. 8.1.1 Rev D – F No known errata. 8.1.2 Rev B – C • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data. Problem Fix/Workaround Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage can not be raised above 2V then operating frequency should be more than 1MHz. This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for room temperature, only. 8.1.3 Rev A Not sampled. 8.2 Errata ATtiny45 The revision letter in this section refers to the revision of the ATtiny45 device. 8.2.1 Rev F – G No known errata 8.2.2 Rev D – E • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data. Problem Fix/Workaround Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage can not be raised above 2V then operating frequency should be more than 1MHz. This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for room temperature, only.ATtiny25/45/85 [DATASHEET] 20 2586QS–AVR–08/2013 8.2.3 Rev B – C • PLL not locking • EEPROM read from application code does not work in Lock Bit Mode 3 • EEPROM read may fail at low supply voltage / low clock frequency • Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly 1. PLL not locking When at frequencies below 6.0 MHz, the PLL will not lock Problem fix / Workaround When using the PLL, run at 6.0 MHz or higher. 2. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Work around Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 3. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data. Problem Fix/Workaround Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage can not be raised above 2V then operating frequency should be more than 1MHz. This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for room temperature, only. 4. Timer Counter 1 PWM output generation on OC1B – XOC1B does not work correctly Timer Counter1 PWM output OC1B-XOC1B does not work correctly. Only in the case when the control bits, COM1B1 and COM1B0 are in the same mode as COM1A1 and COM1A0, respectively, the OC1B-XOC1B output works correctly. Problem Fix/Work around The only workaround is to use same control setting on COM1A[1:0] and COM1B[1:0] control bits, see table 14- 4 in the data sheet. The problem has been fixed for Tiny45 rev D. 8.2.4 Rev A • Too high power down power consumption • DebugWIRE looses communication when single stepping into interrupts • PLL not locking • EEPROM read from application code does not work in Lock Bit Mode 3 • EEPROM read may fail at low supply voltage / low clock frequency 1. Too high power down power consumption Three situations will lead to a too high power down power consumption. These are: – An external clock is selected by fuses, but the I/O PORT is still enabled as an output. – The EEPROM is read before entering power down. – VCC is 4.5 volts or higher. Problem fix / WorkaroundATtiny25/45/85 [DATASHEET] 21 2586QS–AVR–08/2013 – When using external clock, avoid setting the clock pin as Output. – Do not read the EEPROM if power down power consumption is important. – Use VCC lower than 4.5 Volts. 2. DebugWIRE looses communication when single stepping into interrupts When receiving an interrupt during single stepping, debugwire will loose communication. Problem fix / Workaround – When singlestepping, disable interrupts. – When debugging interrupts, use breakpoints within the interrupt routine, and run into the interrupt. 3. PLL not locking When at frequencies below 6.0 MHz, the PLL will not lock Problem fix / Workaround When using the PLL, run at 6.0 MHz or higher. 4. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Work around Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 5. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data. Problem Fix/Workaround Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage can not be raised above 2V then operating frequency should be more than 1MHz. This feature is known to be temperature dependent but it has not been characterized. Guidelines are given for room temperature, only.ATtiny25/45/85 [DATASHEET] 22 2586QS–AVR–08/2013 8.3 Errata ATtiny85 The revision letter in this section refers to the revision of the ATtiny85 device. 8.3.1 Rev B – C No known errata. 8.3.2 Rev A • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data. Problem Fix/Workaround Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage can not be raised above 2V then operating frequency should be more than 1MHz. This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for room temperature, only.ATtiny25/45/85 [DATASHEET] 23 2586QS–AVR–08/2013 9. Datasheet Revision History 9.1 Rev. 2586Q-08/13 9.2 Rev. 2586P-06/13 9.3 Rev. 2586O-02/13 Updated ordering codes on page 11, page 12, and page 13. 9.4 Rev. 2586N-04/11 1. Added: – Section “Capacitive Touch Sensing” on page 6. 2. Updated: – Document template. – Removed “Preliminary” on front page. All devices now final and in production. – Section “Limitations” on page 36. – Program example on page 49. – Section “Overview” on page 122. – Table 17-4 on page 135. – Section “Limitations of debugWIRE” on page 140. – Section “Serial Programming Algorithm” on page 151. – Table 21-7 on page 166. – EEPROM errata on pages 19, 19, 20, 21, and 22 – Ordering information on pages 11, 12, and 13. 9.5 Rev. 2586M-07/10 1. Clarified Section 6.4 “Clock Output Buffer” on page 31. 2. Added Ordering Codes -SN and -SNR for ATtiny25 extended temperature. 9.6 Rev. 2586L-06/10 1. Added: – TSSOP for ATtiny45 in “Features” on page 1, Pinout Figure 1-1 on page 2, Ordering Information in Section 6.2 “ATtiny45” on page 12, and Packaging Information in Section 7.4 “8X” on page 17 – Table 6-11, “Capacitance of Low-Frequency Crystal Oscillator,” on page 29 – Figure 22-36 on page 191 and Figure 22-37 on page 191, Typical Characteristics plots for Bandgap Voltage vs. VCC and Temperature – Extended temperature in Section 6.1 “ATtiny25” on page 11, Ordering Information 1. “Bit 3 – FOC1B: Force Output Compare Match 1B” description in “GTCCR – General Timer/Counter1 Control Register” on page 90 updated: PB3 in “compare match output pin PB3 (OC1B)” corrected to PB4. 1. Updated description of “EEARH – EEPROM Address Register” and “EEARL – EEPROM Address Register” on page 20.ATtiny25/45/85 [DATASHEET] 24 2586QS–AVR–08/2013 – Tape & reel part numbers in Ordering Information, in Section 6.1 “ATtiny25” on page 11 and Section 6.2 “ATtiny45” on page 12 2. Updated: – “Features” on page 1, removed Preliminary from ATtiny25 – Section 8.4.2 “Code Example” on page 44 – “PCMSK – Pin Change Mask Register” on page 52, Bit Descriptions – “TCCR1 – Timer/Counter1 Control Register” on page 89 and “GTCCR – General Timer/Counter1 Control Register” on page 90, COM bit descriptions clarified – Section 20.3.2 “Calibration Bytes” on page 150, frequencies (8 MHz, 6.4 MHz) – Table 20-11, “Minimum Wait Delay Before Writing the Next Flash or EEPROM Location,” on page 153, value for tWD_ERASE – Table 20-16, “High-voltage Serial Programming Instruction Set for ATtiny25/45/85,” on page 158 – Table 21-1, “DC Characteristics. TA = -40C to +85C,” on page 161, notes adjusted – Table 21-11, “Serial Programming Characteristics, TA = -40C to +85C, VCC = 1.8 - 5.5V (Unless Otherwise Noted),” on page 170, added tSLIV – Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0]. 9.7 Rev. 2586K-01/08 1. Updated Document Template. 2. Added Sections: – “Data Retention” on page 6 – “Low Level Interrupt” on page 49 – “Device Signature Imprint Table” on page 149 3. Updated Sections: – “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24 – “System Clock and Clock Options” on page 23 – “Internal PLL in ATtiny15 Compatibility Mode” on page 24 – “Sleep Modes” on page 34 – “Software BOD Disable” on page 35 – “External Interrupts” on page 49 – “Timer/Counter1 in PWM Mode” on page 97 – “USI – Universal Serial Interface” on page 108 – “Temperature Measurement” on page 133 – “Reading Lock, Fuse and Signature Data from Software” on page 143 – “Program And Data Memory Lock Bits” on page 147 – “Fuse Bytes” on page 148 – “Signature Bytes” on page 150 – “Calibration Bytes” on page 150 – “System and Reset Characteristics” on page 165 4. Added Figures: – “Reset Pin Output Voltage vs. Sink Current (VCC = 3V)” on page 184 – “Reset Pin Output Voltage vs. Sink Current (VCC = 5V)” on page 185 – “Reset Pin Output Voltage vs. Source Current (VCC = 3V)” on page 185ATtiny25/45/85 [DATASHEET] 25 2586QS–AVR–08/2013 – “Reset Pin Output Voltage vs. Source Current (VCC = 5V)” on page 186 5. Updated Figure: – “Reset Logic” on page 39 6. Updated Tables: – “Start-up Times for Internal Calibrated RC Oscillator Clock” on page 28 – “Start-up Times for Internal Calibrated RC Oscillator Clock (in ATtiny15 Mode)” on page 28 – “Start-up Times for the 128 kHz Internal Oscillator” on page 28 – “Compare Mode Select in PWM Mode” on page 86 – “Compare Mode Select in PWM Mode” on page 98 – “DC Characteristics. TA = -40C to +85C” on page 161 – “Calibration Accuracy of Internal RC Oscillator” on page 164 – “ADC Characteristics” on page 167 7. Updated Code Example in Section: – “Write” on page 17 8. Updated Bit Descriptions in: – “MCUCR – MCU Control Register” on page 37 – “Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode” on page 77 – “Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode” on page 77 – “Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source” on page 138 – “SPMCSR – Store Program Memory Control and Status Register” on page 145. 9. Updated description of feature “EEPROM read may fail at low supply voltage / low clock frequency” in Sections: – “Errata ATtiny25” on page 19 – “Errata ATtiny45” on page 19 – “Errata ATtiny85” on page 22 10. Updated Package Description in Sections: – “ATtiny25” on page 11 – “ATtiny45” on page 12 – “ATtiny85” on page 13 11. Updated Package Drawing: – “S8S1” on page 16 12. Updated Order Codes for: – “ATtiny25” on page 11 9.8 Rev. 2586J-12/06 1. Updated “Low Power Consumption” on page 1. 2. Updated description of instruction length in “Architectural Overview” . 3. Updated Flash size in “In-System Re-programmable Flash Program Memory” on page 15. 4. Updated cross-references in sections “Atomic Byte Programming” , “Erase” and “Write” , starting on page 17. 5. Updated “Atomic Byte Programming” on page 17.ATtiny25/45/85 [DATASHEET] 26 2586QS–AVR–08/2013 6. Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24. 7. Replaced single clocking system figure with two: Figure 6-2 and Figure 6-3. 8. Updated Table 6-1 on page 25, Table 6-13 on page 30 and Table 6-6 on page 27. 9. Updated “Calibrated Internal Oscillator” on page 27. 10. Updated Table 6-5 on page 26. 11. Updated “OSCCAL – Oscillator Calibration Register” on page 31. 12. Updated “CLKPR – Clock Prescale Register” on page 32. 13. Updated “Power-down Mode” on page 35. 14. Updated “Bit 0” in “PRR – Power Reduction Register” on page 38. 15. Added footnote to Table 8-3 on page 46. 16. Updated Table 10-5 on page 63. 17. Deleted “Bits 7, 2” in “MCUCR – MCU Control Register” on page 64. 18. Updated and moved section “Timer/Counter0 Prescaler and Clock Sources”, now located on page 66. 19. Updated “Timer/Counter1 Initialization for Asynchronous Mode” on page 86. 20. Updated bit description in “PLLCSR – PLL Control and Status Register” on page 94 and “PLLCSR – PLL Control and Status Register” on page 103. 21. Added recommended maximum frequency in“Prescaling and Conversion Timing” on page 125. 22. Updated Figure 17-8 on page 129 . 23. Updated “Temperature Measurement” on page 133. 24. Updated Table 17-3 on page 134. 25. Updated bit R/W descriptions in: “TIMSK – Timer/Counter Interrupt Mask Register” on page 81, “TIFR – Timer/Counter Interrupt Flag Register” on page 81, “TIMSK – Timer/Counter Interrupt Mask Register” on page 92, “TIFR – Timer/Counter Interrupt Flag Register” on page 93, “PLLCSR – PLL Control and Status Register” on page 94, “TIMSK – Timer/Counter Interrupt Mask Register” on page 102, “TIFR – Timer/Counter Interrupt Flag Register” on page 103, “PLLCSR – PLL Control and Status Register” on page 103 and “DIDR0 – Digital Input Disable Register 0” on page 138. 26. Added limitation to “Limitations of debugWIRE” on page 140. 27. Updated “DC Characteristics” on page 161. 28. Updated Table 21-7 on page 166. 29. Updated Figure 21-6 on page 171. 30. Updated Table 21-12 on page 171. 31. Updated Table 22-1 on page 177. 32. Updated Table 22-2 on page 177. 33. Updated Table 22-30, Table 22-31 and Table 22-32, starting on page 188. 34. Updated Table 22-33, Table 22-34 and Table 22-35, starting on page 189. 35. Updated Table 22-39 on page 192. 36. Updated Table 22-46, Table 22-47, Table 22-48 and Table 22-49.ATtiny25/45/85 [DATASHEET] 27 2586QS–AVR–08/2013 9.9 Rev. 2586I-09/06 9.10 Rev. 2586H-06/06 9.11 Rev. 2586G-05/06 9.12 Rev. 2586F-04/06 1. All Characterization data moved to “Electrical Characteristics” on page 161. 2. All Register Descriptions are gathered up in seperate sections in the end of each chapter. 3. Updated Table 11-3 on page 78, Table 11-5 on page 79, Table 11-6 on page 80 and Table 20-4 on page 148. 4. Updated “Calibrated Internal Oscillator” on page 27. 5. Updated Note in Table 7-1 on page 34. 6. Updated “System Control and Reset” on page 39. 7. Updated Register Description in “I/O Ports” on page 53. 8. Updated Features in “USI – Universal Serial Interface” on page 108. 9. Updated Code Example in “SPI Master Operation Example” on page 110 and “SPI Slave Operation Example” on page 111. 10. Updated “Analog Comparator Multiplexed Input” on page 119. 11. Updated Figure 17-1 on page 123. 12. Updated “Signature Bytes” on page 150. 13. Updated “Electrical Characteristics” on page 161. 1. Updated “Calibrated Internal Oscillator” on page 27. 2. Updated Table 6.5.1 on page 31. 3. Added Table 21-2 on page 164. 1. Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24. 2. Updated “Default Clock Source” on page 30. 3. Updated “Low-Frequency Crystal Oscillator” on page 29. 4. Updated “Calibrated Internal Oscillator” on page 27. 5. Updated “Clock Output Buffer” on page 31. 6. Updated “Power Management and Sleep Modes” on page 34. 7. Added “Software BOD Disable” on page 35. 8. Updated Figure 16-1 on page 119. 9. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 120. 10. Added note for Table 17-2 on page 125. 11. Updated “Register Summary” on page 7. 1. Updated “Digital Input Enable and Sleep Modes” on page 57. 2. Updated Table 20-16 on page 158. 3. Updated “Ordering Information” on page 11.ATtiny25/45/85 [DATASHEET] 28 2586QS–AVR–08/2013 9.13 Rev. 2586E-03/06 9.14 Rev. 2586D-02/06 9.15 Rev. 2586C-06/05 9.16 Rev. 2586B-05/05 9.17 Rev. 2586A-02/05 Initial revision. 1. Updated Features in “Analog to Digital Converter” on page 122. 2. Updated Operation in “Analog to Digital Converter” on page 122. 3. Updated Table 17-2 on page 133. 4. Updated Table 17-3 on page 134. 5. Updated “Errata” on page 19. 1. Updated Table 6-13 on page 30, Table 6-10 on page 29, Table 6-3 on page 26, Table 6-9 on page 28, Table 6-5 on page 26, Table 9-1 on page 48,Table 17-4 on page 135, Table 20-16 on page 158, Table 21-8 on page 167. 2. Updated “Timer/Counter1 in PWM Mode” on page 86. 3. Updated text “Bit 2 – TOV1: Timer/Counter1 Overflow Flag” on page 93. 4. Updated values in “DC Characteristics” on page 161. 5. Updated “Register Summary” on page 7. 6. Updated “Ordering Information” on page 11. 7. Updated Rev B and C in “Errata ATtiny45” on page 19. 8. All references to power-save mode are removed. 9. Updated Register Adresses. 1. Updated “Features” on page 1. 2. Updated Figure 1-1 on page 2. 3. Updated Code Examples on page 18 and page 19. 4. Moved “Temperature Measurement” to Section 17.12 page 133. 5. Updated “Register Summary” on page 7. 6. Updated “Ordering Information” on page 11. 1. CLKI added, instances of EEMWE/EEWE renamed EEMPE/EEPE, removed some TBD. Removed “Preliminary Description” from “Temperature Measurement” on page 133. 2. Updated “Features” on page 1. 3. Updated Figure 1-1 on page 2 and Figure 8-1 on page 39. 4. Updated Table 7-2 on page 38, Table 10-4 on page 63, Table 10-5 on page 63 5. Updated “Serial Programming Instruction set” on page 153. 6. Updated SPH register in “Instruction Set Summary” on page 9. 7. Updated “DC Characteristics” on page 161. 8. Updated “Ordering Information” on page 11. 9. Updated “Errata” on page 19.ATtiny25/45/85 [DATASHEET] 29 2586QS–AVR–08/2013Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 www.atmel.com Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Roa Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg 1-6-4 Osaki, Shinagawa-ku Tokyo 141-0032 JAPAN Tel: (+81) (3) 6417-0300 Fax: (+81) (3) 6417-0370 © 2013 Atmel Corporation. All rights reserved. / Rev.: 2586QS–AVR–08/2013 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. 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SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. 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The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.© 2008 Microchip Technology Inc. DS39631E-page 1 PIC18F2420/2520/4420/4520 Power Management Features: • Run: CPU on, Peripherals on • Idle: CPU off, Peripherals on • Sleep: CPU off, Peripherals off • Ultra Low 50nA Input Leakage • Run mode Currents Down to 11 μA Typical • Idle mode Currents Down to 2.5 μA Typical • Sleep mode Current Down to 100 nA Typical • Timer1 Oscillator: 900 nA, 32 kHz, 2V • Watchdog Timer: 1.4 μA, 2V Typical • Two-Speed Oscillator Start-up Flexible Oscillator Structure: • Four Crystal modes, up to 40 MHz • 4x Phase Lock Loop (PLL) – Available for Crystal and Internal Oscillators • Two External RC modes, up to 4 MHz • Two External Clock modes, up to 40 MHz • Internal Oscillator Block: - Fast wake from Sleep and Idle, 1 μs typical - 8 use-selectable frequencies, from 31 kHz to 8 MHz - Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL - User-tunable to compensate for frequency drift • Secondary Oscillator using Timer1 @ 32 kHz • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops Peripheral Highlights: • High-Current Sink/Source 25 mA/25 mA • Three Programmable External Interrupts • Four Input Change Interrupts • Up to 2 Capture/Compare/PWM (CCP) modules, one with Auto-Shutdown (28-pin devices) • Enhanced Capture/Compare/PWM (ECCP) module (40/44-pin devices only): - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart Peripheral Highlights (Continued): • Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I2C™ Master and Slave modes • Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN/J2602 - RS-232 operation using internal oscillator block (no external crystal required) - Auto-wake-up on Start bit - Auto-Baud Detect • 10-Bit, up to 13-Channel Analog-to-Digital (A/D) Converter module: - Auto-acquisition capability - Conversion available during Sleep • Dual Analog Comparators with Input Multiplexing • Programmable 16-Level High/Low-Voltage Detection (HLVD) module: - Supports interrupt on High/Low-Voltage Detection Special Microcontroller Features: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • 100,000 Erase/Write Cycle Enhanced Flash Program Memory Typical • 1,000,000 Erase/Write Cycle Data EEPROM Memory Typical • Flash/Data EEPROM Retention: 100 Years Typical • Self-Programmable under Software Control • Priority Levels for Interrupts • 8 x 8 Single-Cycle Hardware Multiplier • Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s • Single-Supply 5V In-Circuit Serial Programming™ (ICSP™) via Two Pins • In-Circuit Debug (ICD) via Two Pins • Wide Operating Voltage Range: 2.0V to 5.5V • Programmable Brown-out Reset (BOR) with Software Enable Option - Device Program Memory Data Memory I/O 10-Bit A/D (ch) CCP/ ECCP (PWM) MSSP EUSART Comp. Timers 8/16-Bit Flash (bytes) # Single-Word Instructions SRAM (bytes) EEPROM (bytes) SPI Master I 2C™ PIC18F2420 16K 8192 768 256 25 10 2/0 Y Y 1 2 1/3 PIC18F2520 32K 16384 1536 256 25 10 2/0 Y Y 1 2 1/3 PIC18F4420 16K 8192 768 256 36 13 1/1 Y Y 1 2 1/3 PIC18F4520 32K 16384 1536 256 36 13 1/1 Y Y 1 2 1/3 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt TechnologyPIC18F2420/2520/4420/4520 DS39631E-page 2 © 2008 Microchip Technology Inc. Pin Diagrams PIC18F2520 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3/AN9/CCP2(1) RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA 28-Pin SPDIP, SOIC PIC18F2420 Note 1: RB3 is the alternate pin for CCP2 multiplexing. 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 2827 2625 2423 9 PIC18F2420 RC0/T1OSO/T13CKI 5 4 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4KBI0/AN11 RB3/AN9/CCP2(1) RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA MCLR/VPP/RE3 RA1/AN1 RA0/AN0 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL PIC18F2520 28-Pin QFN RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 RB3/AN9/CCP2(1) RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 VDD VSS RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PIC18F4520 40-Pin PDIP PIC18F4420© 2008 Microchip Technology Inc. DS39631E-page 3 PIC18F2420/2520/4420/4520 Pin Diagrams (Cont.’d) Note 1: RB3 is the alternate pin for CCP2 multiplexing. 10 11 2 3 4 5 6 1 12 13 14 15 18 19 20 21 22 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 35 34 9 PIC18F442037 RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA0/AN0 RA1/AN1 MCLR/VPP/RE3 RB3/AN9/CCP2(1) RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD NC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2(1) RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS VSS VDD VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD VDD RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 44-pin QFN PIC18F4520 10 11 2 3 4 5 6 1 12 13 14 15 18 19 20 21 22 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 35 34 9 PIC18F442037 RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA0/AN0 RA1/AN1 MCLR/VPP/RE3 NC RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD NC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2(1) NC NC RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2(1) 44-pin TQFP PIC18F4520PIC18F2420/2520/4420/4520 DS39631E-page 4 © 2008 Microchip Technology Inc. Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 23 3.0 Power-Managed Modes ............................................................................................................................................................. 33 4.0 Reset .......................................................................................................................................................................................... 41 5.0 Memory Organization ................................................................................................................................................................. 53 6.0 Flash Program Memory.............................................................................................................................................................. 73 7.0 Data EEPROM Memory ............................................................................................................................................................. 83 8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 89 9.0 Interrupts .................................................................................................................................................................................... 91 10.0 I/O Ports ................................................................................................................................................................................... 105 11.0 Timer0 Module ......................................................................................................................................................................... 123 12.0 Timer1 Module ......................................................................................................................................................................... 127 13.0 Timer2 Module ......................................................................................................................................................................... 133 14.0 Timer3 Module ......................................................................................................................................................................... 135 15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 139 16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 147 17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 161 18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 201 19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 223 20.0 Comparator Module.................................................................................................................................................................. 233 21.0 Comparator Voltage Reference Module................................................................................................................................... 239 22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 243 23.0 Special Features of the CPU.................................................................................................................................................... 249 24.0 Instruction Set Summary .......................................................................................................................................................... 267 25.0 Development Support............................................................................................................................................................... 317 26.0 Electrical Characteristics .......................................................................................................................................................... 321 27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 361 28.0 Packaging Information.............................................................................................................................................................. 383 Appendix A: Revision History............................................................................................................................................................. 395 Appendix B: Device Differences......................................................................................................................................................... 395 Appendix C: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 396 Appendix D: Migration from High-End to Enhanced Devices............................................................................................................. 396 Index .................................................................................................................................................................................................. 397 The Microchip Web Site ..................................................................................................................................................................... 407 Customer Change Notification Service .............................................................................................................................................. 407 Customer Support.............................................................................................................................................................................. 407 Reader Response .............................................................................................................................................................................. 408 PIC18F2420/2520/4420/4520 Product Identification System ............................................................................................................ 409© 2008 Microchip Technology Inc. DS39631E-page 5 PIC18F2420/2520/4420/4520 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.PIC18F2420/2520/4420/4520 DS39631E-page 6 © 2008 Microchip Technology Inc. NOTES:© 2008 Microchip Technology Inc. DS39631E-page 7 PIC18F2420/2520/4420/4520 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Enhanced Flash program memory. On top of these features, the PIC18F2420/2520/4420/ 4520 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 New Core Features 1.1.1 nanoWatt TECHNOLOGY All of the devices in the PIC18F2420/2520/4420/4520 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. • Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. • On-the-Fly Mode Switching: The powermanaged modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design. • Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 26.0 “Electrical Characteristics” for values. 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2420/2520/4420/4520 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators • Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O) • Two External RC Oscillator modes with the same pin options as the External Clock modes • An internal oscillator block which provides an 8 MHz clock and an INTRC source (approximately 31 kHz), as well as a range of 6 user-selectable clock frequencies, between 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O. • A Phase Lock Loop (PLL) frequency multiplier, available to both the High-Speed Crystal and Internal Oscillator modes, which allows clock speeds of up to 40 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz – all without using an external crystal or clock circuit. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: • Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown. • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. • PIC18F2420 • PIC18LF2420 • PIC18F2520 • PIC18LF2520 • PIC18F4420 • PIC18LF4420 • PIC18F4520 • PIC18LF4520PIC18F2420/2520/4420/4520 DS39631E-page 8 © 2008 Microchip Technology Inc. 1.2 Other Special Features • Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. • Extended Instruction Set: The PIC18F2420/ 2520/4420/4520 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. • Enhanced CCP Module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown, for disabling PWM outputs on interrupt, or other select conditions, and auto-restart to reactivate outputs once the condition has cleared. • Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 26.0 “Electrical Characteristics” for time-out periods. 1.3 Details on Individual Family Members Devices in the PIC18F2420/2520/4420/4520 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1. Flash program memory (16 Kbytes for PIC18F2420/4420 devices and 32 Kbytes for PIC18F2520/4520 devices). 2. A/D channels (10 for 28-pin devices, 13 for 40/44-pin devices). 3. I/O ports (3 bidirectional ports on 28-pin devices, 5 bidirectional ports on 40/44-pin devices). 4. CCP and Enhanced CCP implementation (28-pin devices have 2 standard CCP modules, 40/44-pin devices have one standard CCP module and one ECCP module). 5. Parallel Slave Port (present only on 40/44-pin devices). All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-2 and Table 1-3. Like all Microchip PIC18 devices, members of the PIC18F2420/2520/4420/4520 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2420), accommodate an operating VDD range of 4.2V to 5.5V. Low-voltage parts, designated by “LF” (such as PIC18LF2420), function over an extended VDD range of 2.0V to 5.5V. © 2008 Microchip Technology Inc. DS39631E-page 9 PIC18F2420/2520/4420/4520 TABLE 1-1: DEVICE FEATURES Features PIC18F2420 PIC18F2520 PIC18F4420 PIC18F4520 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 16384 32768 16384 32768 Program Memory (Instructions) 8192 16384 8192 16384 Data Memory (Bytes) 768 1536 768 1536 Data EEPROM Memory (Bytes) 256 256 256 256 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Timers 4 4 4 4 Capture/Compare/PWM Modules 2 2 1 1 Enhanced Capture/Compare/PWM Modules 0011 Serial Communications MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART Parallel Communications (PSP) No No Yes Yes 10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Programmable High/Low-Voltage Detect Yes Yes Yes Yes Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions; 83 with Extended Instruction Set Enabled 75 Instructions; 83 with Extended Instruction Set Enabled 75 Instructions; 83 with Extended Instruction Set Enabled 75 Instructions; 83 with Extended Instruction Set Enabled Packages 28-Pin SPDIP 28-Pin SOIC 28-Pin QFN 28-Pin SPDIP 28-Pin SOIC 28-Pin QFN 40-Pin PDIP 44-Pin QFN 44-Pin TQFP 40-Pin PDIP 44-Pin QFN 44-Pin TQFPPIC18F2420/2520/4420/4520 DS39631E-page 10 © 2008 Microchip Technology Inc. FIGURE 1-1: PIC18F2420/2520 (28-PIN) BLOCK DIAGRAM Instruction Decode and Control PORTA PORTB PORTC RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT RB0/INT0/FLT0/AN12 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA1/AN1 RA0/AN0 RB1/INT1/AN10 Data Latch Data Memory ( 3.9 Kbytes ) Address Latch Data Address<12> 12 BSR Access FSR0 FSR1 FSR2 inc/dec logic Address 4 12 4 PCH PCL PCLATH 8 31-Level Stack Program Counter PRODH PRODL 8 x 8 Multiply 8 BITOP 8 8 ALU<8> Address Latch Program Memory (16/32 Kbytes) Data Latch 20 8 8 Table Pointer<21> inc/dec logic 21 8 Data Bus<8> Table Latch 8 IR 12 3 ROM Latch RB2/INT2/AN8 RB3/AN9/CCP2(1) PCLATU PCU OSC2/CLKO(3)/RA6 Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD Comparator MSSP EUSART 10-Bit ADC Timer0 Timer1 Timer2 Timer3 CCP2 HLVD CCP1 BOR Data EEPROM W Instruction Bus <16> STKPTR Bank 8 State Machine Control Signals Decode 8 8 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer OSC1(3) OSC2(3) VDD, Brown-out Reset Internal Oscillator Fail-Safe Clock Monitor Precision Reference Band Gap VSS MCLR(2) Block INTRC Oscillator 8 MHz Oscillator Single-Supply Programming In-Circuit Debugger T1OSO OSC1/CLKI(3)/RA7 T1OSI PORTE MCLR/VPP/RE3(2)© 2008 Microchip Technology Inc. DS39631E-page 11 PIC18F2420/2520/4420/4520 FIGURE 1-2: PIC18F4420/4520 (40/44-PIN) BLOCK DIAGRAM Instruction Decode and Control Data Latch Data Memory ( 3.9 Kbytes ) Address Latch Data Address<12> 12 BSR Access FSR0 FSR1 FSR2 inc/dec logic Address 4 12 4 PCH PCL PCLATH 8 31-Level Stack Program Counter PRODH PRODL 8 x 8 Multiply 8 BITOP 8 8 ALU<8> Address Latch Program Memory (16/32 Kbytes) Data Latch 20 8 8 Table Pointer<21> inc/dec logic 21 8 Data Bus<8> Table Latch 8 IR 12 3 ROM Latch PORTD RD0/PSP0 PCLATU PCU PORTE MCLR/VPP/RE3(2) RE2/CS/AN7 RE0/RD/AN5 RE1/WR/AN6 Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. :RD4/PSP4 Comparator MSSP EUSART 10-Bit ADC Timer0 Timer1 Timer2 Timer3 CCP2 HLVD ECCP1 BOR Data EEPROM W Instruction Bus <16> STKPTR Bank 8 State Machine Control Signals Decode 8 8 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer OSC1(3) OSC2(3) VDD, Brown-out Reset Internal Oscillator Fail-Safe Clock Monitor Precision Reference Band Gap VSS MCLR(2) Block INTRC Oscillator 8 MHz Oscillator Single-Supply Programming In-Circuit Debugger T1OSI T1OSO RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D PORTA PORTB PORTC RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT RB0/INT0/FLT0/AN12 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA1/AN1 RA0/AN0 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2(1) OSC2/CLKO(3)/RA6 RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD OSC1/CLKI(3)/RA7PIC18F2420/2520/4420/4520 DS39631E-page 12 © 2008 Microchip Technology Inc. TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type SPDIP, Description SOIC QFN MCLR/VPP/RE3 MCLR VPP RE3 1 26 I P I ST ST Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. OSC1/CLKI/RA7 OSC1 CLKI RA7 9 6 I I I/O ST CMOS TTL Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. OSC2/CLKO/RA6 OSC2 CLKO RA6 10 7 O O I/O — — TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. DS39631E-page 13 PIC18F2420/2520/4420/4520 PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 27 I/O I TTL Analog Digital I/O. Analog input 0. RA1/AN1 RA1 AN1 3 28 I/O I TTL Analog Digital I/O. Analog input 1. RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF 4 1 I/O I I O TTL Analog Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. Comparator reference voltage output. RA3/AN3/VREF+ RA3 AN3 VREF+ 5 2 I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. RA4/T0CKI/C1OUT RA4 T0CKI C1OUT 6 3 I/O I O ST ST — Digital I/O. Timer0 external clock input. Comparator 1 output. RA5/AN4/SS/HLVDIN/ C2OUT RA5 AN4 SS HLVDIN C2OUT 7 4 I/O I I I O TTL Analog TTL Analog — Digital I/O. Analog input 4. SPI slave select input. High/Low-Voltage Detect input. Comparator 2 output. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type SPDIP, Description SOIC QFN Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. PIC18F2420/2520/4420/4520 DS39631E-page 14 © 2008 Microchip Technology Inc. PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 RB0 INT0 FLT0 AN12 21 18 I/O I I I TTL ST ST Analog Digital I/O. External interrupt 0. PWM Fault input for CCP1. Analog input 12. RB1/INT1/AN10 RB1 INT1 AN10 22 19 I/O I I TTL ST Analog Digital I/O. External interrupt 1. Analog input 10. RB2/INT2/AN8 RB2 INT2 AN8 23 20 I/O I I TTL ST Analog Digital I/O. External interrupt 2. Analog input 8. RB3/AN9/CCP2 RB3 AN9 CCP2(1) 24 21 I/O I I/O TTL Analog ST Digital I/O. Analog input 9. Capture 2 input/Compare 2 output/PWM2 output. RB4/KBI0/AN11 RB4 KBI0 AN11 25 22 I/O I I TTL TTL Analog Digital I/O. Interrupt-on-change pin. Analog input 11. RB5/KBI1/PGM RB5 KBI1 PGM 26 23 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC RB6 KBI2 PGC 27 24 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD RB7 KBI3 PGD 28 25 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type SPDIP, Description SOIC QFN Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. DS39631E-page 15 PIC18F2420/2520/4420/4520 PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 11 8 I/O O I ST — ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) 12 9 I/O I I/O ST Analog ST Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. RC2/CCP1 RC2 CCP1 13 10 I/O I/O ST ST Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. RC3/SCK/SCL RC3 SCK SCL 14 11 I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA RC4 SDI SDA 15 12 I/O I I/O ST ST ST Digital I/O. SPI data in. I 2C data I/O. RC5/SDO RC5 SDO 16 13 I/O O ST — Digital I/O. SPI data out. RC6/TX/CK RC6 TX CK 17 14 I/O O I/O ST — ST Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). RC7/RX/DT RC7 RX DT 18 15 I/O I I/O ST ST ST Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). RE3 — — — — See MCLR/VPP/RE3 pin. VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins. VDD 20 17 P — Positive supply for logic and I/O pins. TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type SPDIP, Description SOIC QFN Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. PIC18F2420/2520/4420/4520 DS39631E-page 16 © 2008 Microchip Technology Inc. TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP MCLR/VPP/RE3 MCLR VPP RE3 1 18 18 I P I ST ST Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. OSC1/CLKI/RA7 OSC1 CLKI RA7 13 32 30 I I I/O ST CMOS TTL Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; analog otherwise. External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. OSC2/CLKO/RA6 OSC2 CLKO RA6 14 33 31 O O I/O — — TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. DS39631E-page 17 PIC18F2420/2520/4420/4520 PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 19 19 I/O I TTL Analog Digital I/O. Analog input 0. RA1/AN1 RA1 AN1 3 20 20 I/O I TTL Analog Digital I/O. Analog input 1. RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF 4 21 21 I/O I I O TTL Analog Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. Comparator reference voltage output. RA3/AN3/VREF+ RA3 AN3 VREF+ 5 22 22 I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. RA4/T0CKI/C1OUT RA4 T0CKI C1OUT 6 23 23 I/O I O ST ST — Digital I/O. Timer0 external clock input. Comparator 1 output. RA5/AN4/SS/HLVDIN/ C2OUT RA5 AN4 SS HLVDIN C2OUT 7 24 24 I/O I I I O TTL Analog TTL Analog — Digital I/O. Analog input 4. SPI slave select input. High/Low-Voltage Detect input. Comparator 2 output. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. PIC18F2420/2520/4420/4520 DS39631E-page 18 © 2008 Microchip Technology Inc. PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 RB0 INT0 FLT0 AN12 33 9 8 I/O I I I TTL ST ST Analog Digital I/O. External interrupt 0. PWM Fault input for Enhanced CCP1. Analog input 12. RB1/INT1/AN10 RB1 INT1 AN10 34 10 9 I/O I I TTL ST Analog Digital I/O. External interrupt 1. Analog input 10. RB2/INT2/AN8 RB2 INT2 AN8 35 11 10 I/O I I TTL ST Analog Digital I/O. External interrupt 2. Analog input 8. RB3/AN9/CCP2 RB3 AN9 CCP2(1) 36 12 11 I/O I I/O TTL Analog ST Digital I/O. Analog input 9. Capture 2 input/Compare 2 output/PWM2 output. RB4/KBI0/AN11 RB4 KBI0 AN11 37 14 14 I/O I I TTL TTL Analog Digital I/O. Interrupt-on-change pin. Analog input 11. RB5/KBI1/PGM RB5 KBI1 PGM 38 15 15 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC RB6 KBI2 PGC 39 16 16 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD RB7 KBI3 PGD 40 17 17 I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. DS39631E-page 19 PIC18F2420/2520/4420/4520 PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 15 34 32 I/O O I ST — ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) 16 35 35 I/O I I/O ST CMOS ST Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. RC2/CCP1/P1A RC2 CCP1 P1A 17 36 36 I/O I/O O ST ST — Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. Enhanced CCP1 output. RC3/SCK/SCL RC3 SCK SCL 18 37 37 I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA RC4 SDI SDA 23 42 42 I/O I I/O ST ST ST Digital I/O. SPI data in. I 2C data I/O. RC5/SDO RC5 SDO 24 43 43 I/O O ST — Digital I/O. SPI data out. RC6/TX/CK RC6 TX CK 25 44 44 I/O O I/O ST — ST Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). RC7/RX/DT RC7 RX DT 26 1 1 I/O I I/O ST ST ST Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. PIC18F2420/2520/4420/4520 DS39631E-page 20 © 2008 Microchip Technology Inc. PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled. RD0/PSP0 RD0 PSP0 19 38 38 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. RD1/PSP1 RD1 PSP1 20 39 39 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. RD2/PSP2 RD2 PSP2 21 40 40 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. RD3/PSP3 RD3 PSP3 22 41 41 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. RD4/PSP4 RD4 PSP4 27 2 2 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. RD5/PSP5/P1B RD5 PSP5 P1B 28 3 3 I/O I/O O ST TTL — Digital I/O. Parallel Slave Port data. Enhanced CCP1 output. RD6/PSP6/P1C RD6 PSP6 P1C 29 4 4 I/O I/O O ST TTL — Digital I/O. Parallel Slave Port data. Enhanced CCP1 output. RD7/PSP7/P1D RD7 PSP7 P1D 30 5 5 I/O I/O O ST TTL — Digital I/O. Parallel Slave Port data. Enhanced CCP1 output. TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. DS39631E-page 21 PIC18F2420/2520/4420/4520 PORTE is a bidirectional I/O port. RE0/RD/AN5 RE0 RD AN5 8 25 25 I/O I I ST TTL Analog Digital I/O. Read control for Parallel Slave Port (see also WR and CS pins). Analog input 5. RE1/WR/AN6 RE1 WR AN6 9 26 26 I/O I I ST TTL Analog Digital I/O. Write control for Parallel Slave Port (see CS and RD pins). Analog input 6. RE2/CS/AN7 RE2 CS AN7 10 27 27 I/O I I ST TTL Analog Digital I/O. Chip Select control for Parallel Slave Port (see related RD and WR). Analog input 7. RE3 — — — — — See MCLR/VPP/RE3 pin. VSS 12, 31 6, 30, 31 6, 29 P — Ground reference for logic and I/O pins. VDD 11, 32 7, 8, 28, 29 7, 28 P — Positive supply for logic and I/O pins. NC — 13 12, 13, 33, 34 — — No Connect. TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. PIC18F2420/2520/4420/4520 DS39631E-page 22 © 2008 Microchip Technology Inc. NOTES:© 2008 Microchip Technology Inc. DS39631E-page 23 PIC18F2420/2520/4420/4520 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types PIC18F2420/2520/4420/4520 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC<3:0>, in Configuration Register 1H to select one of these ten modes: 1. LP Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL Enabled 5. RC External Resistor/Capacitor with FOSC/4 Output on RA6 6. RCIO External Resistor/Capacitor with I/O on RA6 7. INTIO1 Internal Oscillator with FOSC/4 Output on RA6 and I/O on RA7 8. INTIO2 Internal Oscillator with I/O on RA6 and RA7 9. EC External Clock with FOSC/4 Output 10. ECIO External Clock with I/O on RA6 2.2 Crystal Oscillator/Ceramic Resonators In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION) TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. Typical Capacitor Values Used: Mode Freq OSC1 OSC2 XT 3.58 MHz 4.19 MHz 4 MHz 4 MHz 15 pF 15 pF 30 pF 50 pF 15 pF 15 pF 30 pF 50 pF Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table 2-2 for additional information. Note: When using resonators with frequencies above 3.5 MHz, the use of HS mode, rather than XT mode, is recommended. HS mode may be used at any VDD for which the controller is rated. If HS is selected, it is possible that the gain of the oscillator will overdrive the resonator. Therefore, a series resistor should be placed between the OSC2 pin and the resonator. As a good starting point, the recommended value of RS is 330Ω. Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the oscillator mode chosen. C1(1) C2(1) XTAL OSC2 OSC1 RF(3) Sleep To Logic PIC18FXXXX RS(2) InternalPIC18F2420/2520/4420/4520 DS39631E-page 24 © 2008 Microchip Technology Inc. TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2. FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) 2.3 External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 shows the pin connections for the EC Oscillator mode. FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-4 shows the pin connections for the ECIO Oscillator mode. FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) Osc Type Crystal Freq Typical Capacitor Values Tested: C1 C2 LP 32 kHz 30 pF 30 pF XT 1 MHz 4 MHz 15 pF 15 pF 15 pF 15 pF HS 4 MHz 10 MHz 20 MHz 25 MHz 25 MHz 15 pF 15 pF 15 pF 0 pF 15 pF 15 pF 15 pF 15 pF 5 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 32 kHz 4 MHz 25 MHz 10 MHz 1 MHz 20 MHz Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required to avoid overdriving crystals with low drive level specification. 5: Always verify oscillator performance over the VDD and temperature range that is expected for the application. OSC1 Open OSC2 Clock from Ext. System PIC18FXXXX (HS Mode) OSC1/CLKI FOSC/4 OSC2/CLKO Clock from Ext. System PIC18FXXXX OSC1/CLKI RA6 I/O (OSC2) Clock from Ext. System PIC18FXXXX© 2008 Microchip Technology Inc. DS39631E-page 25 PIC18F2420/2520/4420/4520 2.4 RC Oscillator For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The actual oscillator frequency is a function of several factors: • supply voltage • values of the external resistor (REXT) and capacitor (CEXT) • operating temperature Given the same device, operating voltage and temperature and component values, there will also be unit-to-unit frequency variations. These are due to factors such as: • normal manufacturing variation • difference in lead frame capacitance between package types (especially for low CEXT values) • variations within the tolerance of limits of REXT and CEXT In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-5 shows how the R/C combination is connected. FIGURE 2-5: RC OSCILLATOR MODE The RCIO Oscillator mode (Figure 2-6) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). FIGURE 2-6: RCIO OSCILLATOR MODE 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. 2.5.1 HSPLL OSCILLATOR MODE The HSPLL mode makes use of the HS Oscillator mode for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLLEN bit is not available in this oscillator mode. The PLL is only available to the crystal oscillator when the FOSC<3:0> Configuration bits are programmed for HSPLL mode (= 0110). FIGURE 2-7: PLL BLOCK DIAGRAM (HS MODE) 2.5.2 PLL AND INTOSC The PLL is also available to the internal oscillator block in selected oscillator modes. In this configuration, the PLL is enabled in software and generates a clock output of up to 32 MHz. The operation of INTOSC with the PLL is described in Section 2.6.4 “PLL in INTOSC Modes”. OSC2/CLKO CEXT REXT PIC18FXXXX OSC1 FOSC/4 Internal Clock VDD VSS Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ CEXT > 20 pF CEXT REXT PIC18FXXXX OSC1 Internal Clock VDD VSS Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ CEXT > 20 pF RA6 I/O (OSC2) MUX VCO Loop Filter Crystal Osc OSC2 OSC1 PLL Enable FIN FOUT SYSCLK Phase Comparator HS Oscillator Enable ÷4 (from Configuration Register 1H) HS ModePIC18F2420/2520/4420/4520 DS39631E-page 26 © 2008 Microchip Technology Inc. 2.6 Internal Oscillator Block The PIC18F2420/2520/4420/4520 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source which can be used to directly drive the device clock. It also drives a postscaler which can provide a range of clock frequencies from 31 kHz to 4 MHz. The INTOSC output is enabled when a clock frequency from 125 kHz to 8 MHz is selected. The other clock source is the internal RC oscillator (INTRC), which provides a nominal 31 kHz output. INTRC is enabled if it is selected as the device clock source; it is also enabled automatically when any of the following are enabled: • Power-up Timer • Fail-Safe Clock Monitor • Watchdog Timer • Two-Speed Start-up These features are discussed in greater detail in Section 23.0 “Special Features of the CPU”. The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 30). 2.6.1 INTIO MODES Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available: • In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. 2.6.2 INTOSC OUTPUT FREQUENCY The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz. The INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. 2.6.3 OSCTUNE REGISTER The internal oscillator’s output has been calibrated at the factory but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register (Register 2-1). When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. The INTRC clock will reach the new frequency within 8 clock cycles (approximately 8 * 32 μs = 256 μs). The INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. The OSCTUNE register also implements the INTSRC and PLLEN bits, which control certain features of the internal oscillator block. The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31 kHz frequency option is selected. This is covered in greater detail in Section 2.7.1 “Oscillator Control Register”. The PLLEN bit controls the operation of the frequency multiplier, PLL, in internal oscillator modes. 2.6.4 PLL IN INTOSC MODES The 4x frequency multiplier can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with an internal oscillator. When enabled, the PLL produces a clock speed of up to 32 MHz. Unlike HSPLL mode, the PLL is controlled through software. The control bit, PLLEN (OSCTUNE<6>), is used to enable or disable its operation. The PLL is available when the device is configured to use the internal oscillator block as its primary clock source (FOSC<3:0> = 1001 or 1000). Additionally, the PLL will only function when the selected output frequency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111 or 110). If both of these conditions are not met, the PLL is disabled. The PLLEN control bit is only functional in those internal oscillator modes where the PLL is available. In all other modes, it is forced to ‘0’ and is effectively unavailable. 2.6.5 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift as VDD or temperature changes, which can affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency. Tuning the INTOSC source requires knowing when to make the adjustment, in which direction it should be made, and in some cases, how large a change is needed. Three compensation techniques are discussed in Section 2.6.5.1 “Compensating with the EUSART”, Section 2.6.5.2 “Compensating with the Timers” and Section 2.6.5.3 “Compensating with the CCP Module in Capture Mode”, but other techniques may be used.© 2008 Microchip Technology Inc. DS39631E-page 27 PIC18F2420/2520/4420/4520 2.6.5.1 Compensating with the EUSART An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high. To adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low. To compensate, increment OSCTUNE to increase the clock frequency. 2.6.5.2 Compensating with the Timers This technique compares device clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 2.6.5.3 Compensating with the CCP Module in Capture Mode A CCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast; to compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow; to compensate, increment the OSCTUNE register. REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled) 0 = 31 kHz device clock derived directly from INTRC internal oscillator bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1) 1 = PLL enabled for INTOSC (4 MHz and 8 MHz only) 0 = PLL disabled bit 5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 011111 = Maximum frequency • • • • 000001 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111 • • • • 100000 = Minimum frequency Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes” for details.PIC18F2420/2520/4420/4520 DS39631E-page 28 © 2008 Microchip Technology Inc. 2.7 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F2420/2520/ 4420/4520 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F2420/2520/4420/4520 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available. Essentially, there are three clock sources for these devices: • Primary oscillators • Secondary oscillators • Internal oscillator block The primary oscillators include the External Crystal and Resonator modes, the External RC modes, the External Clock modes and the internal oscillator block. The particular mode is defined by the FOSC<3:0> Configuration bits. The details of these modes are covered earlier in this chapter. The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. PIC18F2420/2520/4420/4520 devices offer the Timer1 oscillator as a secondary oscillator. This oscillator, in all power-managed modes, is often the time base for functions such as a Real-Time Clock (RTC). Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO/T13CKI and RC1/T1OSI pins. Like the LP Oscillator mode circuit, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 12.3 “Timer1 Oscillator”. In addition to being a primary clock source, the internal oscillator block is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F2420/2520/4420/4520 devices are shown in Figure 2-8. See Section 23.0 “Special Features of the CPU” for Configuration register details. FIGURE 2-8: PIC18F2420/2520/4420/4520 CLOCK DIAGRAM 4 x PLL FOSC<3:0> Secondary Oscillator T1OSCEN Enable Oscillator T1OSO T1OSI Clock Source Option for Other Modules OSC1 OSC2 Sleep HSPLL, INTOSC/PLL LP, XT, HS, RC, EC T1OSC CPU Peripherals IDLEN Postscaler MUX MUX 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 250 kHz OSCCON<6:4> 111 110 101 100 011 010 001 000 31 kHz INTRC Source Internal Oscillator Block WDT, PWRT, FSCM 8 MHz Internal Oscillator (INTOSC) OSCCON<6:4> Clock Control OSCCON<1:0> Source 8 MHz 31 kHz (INTRC) OSCTUNE<6> 0 1 OSCTUNE<7> and Two-Speed Start-up Primary Oscillator PIC18F2420/2520/4420/4520© 2008 Microchip Technology Inc. DS39631E-page 29 PIC18F2420/2520/4420/4520 2.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 2-2) controls several aspects of the device clock’s operation, both in full-power operation and in power-managed modes. The System Clock Select bits, SCS<1:0>, select the clock source. The available clock sources are the primary clock (defined by the FOSC<3:0> Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared on all forms of Reset. The Internal Oscillator Frequency Select bits (IRCF<2:0>) select the frequency output of the internal oscillator block to drive the device clock. The choices are the INTRC source, the INTOSC source (8 MHz) or one of the frequencies derived from the INTOSC postscaler (31.25 kHz to 4 MHz). If the internal oscillator block is supplying the device clock, changing the states of these bits will have an immediate change on the internal oscillator’s output. On device Resets, the default output frequency of the internal oscillator block is set at 1 MHz. When a nominal output frequency of 31 kHz is selected (IRCF<2:0> = 000), users may choose which internal oscillator acts as the source. This is done with the INTSRC bit in the OSCTUNE register (OSCTUNE<7>). Setting this bit selects INTOSC as a 31.25 kHz clock source by enabling the divide-by-256 output of the INTOSC postscaler. Clearing INTSRC selects INTRC (nominally 31 kHz) as the clock source. This option allows users to select the tunable and more precise INTOSC as a clock source, while maintaining power savings with a very low clock speed. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer (OST) has timed out and the primary clock is providing the device clock in primary clock modes. The IOFS bit indicates when the internal oscillator block has stabilized and is providing the device clock in RC Clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 3.0 “Power-Managed Modes”. 2.7.2 OSCILLATOR TRANSITIONS PIC18F2420/2520/4420/4520 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power-Managed Modes”. Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before selecting the secondary clock source or a very long delay may occur while the Timer1 oscillator starts. PIC18F2420/2520/4420/4520 DS39631E-page 30 © 2008 Microchip Technology Inc. REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters an Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8 MHz (INTOSC drives clock directly) 110 = 4 MHz 101 = 2 MHz 100 = 1 MHz(3) 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2) bit 3 OSTS: Oscillator Start-up Timer Time-out Status bit(1) 1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Secondary (Timer1) oscillator 00 = Primary oscillator Note 1: Reset state depends on state of the IESO Configuration bit. 2: Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset.© 2008 Microchip Technology Inc. DS39631E-page 31 PIC18F2420/2520/4420/4520 2.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1 or Timer3. In internal oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the device clock source. The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the powermanaged mode (see Section 23.2 “Watchdog Timer (WDT)”, Section 23.3 “Two-Speed Start-up” and Section 23.4 “Fail-Safe Clock Monitor” for more information on WDT, Fail-Safe Clock Monitor and TwoSpeed Start-up). The INTOSC output at 8 MHz may be used directly to clock the device or may be divided down by the postscaler. The INTOSC output is disabled if the clock is provided directly from the INTRC output. If Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a RealTime Clock. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others). Peripherals that may add significant current consumption are listed in Section 26.2 “DC Characteristics”. 2.9 Power-up Delays Power-up delays are controlled by two timers so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 4.5 “Device Reset Timers”. The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 26-10). It is enabled by clearing (= 0) the PWRTEN Configuration bit. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the HSPLL Oscillator mode is selected, the device is kept in Reset for an additional 2 ms, following the HS mode OST delay, so the PLL can lock to the incoming clock frequency. There is a delay of interval, TCSD (parameter 38, Table 26-10), following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIO modes are used as the primary clock source. TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output) RCIO Floating, external resistor should pull high Configured as PORTA, bit 6 INTIO2 Configured as PORTA, bit 7 Configured as PORTA, bit 6 ECIO Floating, pulled by external clock Configured as PORTA, bit 6 EC Floating, pulled by external clock At logic low (clock/4 output) LP, XT and HS Feedback inverter disabled at quiescent voltage level Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.PIC18F2420/2520/4420/4520 DS39631E-page 32 © 2008 Microchip Technology Inc. NOTES:© 2008 Microchip Technology Inc. Advance Information DS39631E-page 33 PIC18F2420/2520/4420/4520 3.0 POWER-MANAGED MODES PIC18F2420/2520/4420/4520 devices offer a total of seven operating modes for more efficient powermanagement. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • Run modes • Idle modes • Sleep mode These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the Sleep mode does not use a clock source. The power-managed modes include several powersaving features offered on previous PIC® devices. One is the clock switching feature, offered in other PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PIC devices, where all device clocks are stopped. 3.1 Selecting Power-Managed Modes Selecting a power-managed mode requires two decisions: if the CPU is to be clocked or not and the selection of a clock source. The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1. 3.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • the primary clock, as defined by the FOSC<3:0> Configuration bits • the secondary clock (the Timer1 oscillator) • the internal oscillator block (for RC modes) 3.1.2 ENTERING POWER-MANAGED MODES Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS<1:0> bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in Section 3.1.3 “Clock Transitions and Status Indicators” and subsequent sections. Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. TABLE 3-1: POWER-MANAGED MODES Mode OSCCON<7,1:0> Bits Module Clocking Available Clock and Oscillator Source IDLEN(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC and Internal Oscillator Block(2). This is the normal full-power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.PIC18F2420/2520/4420/4520 DS39631E-page 34 Advance Information © 2008 Microchip Technology Inc. 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • OSTS (OSCCON<3>) • IOFS (OSCCON<2>) • T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode. When the OSTS bit is set, the primary clock is providing the device clock. When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source to a divider that actually drives the device clock. When the T1RUN bit is set, the Timer1 oscillator is providing the clock. If none of these bits are set, then either the INTRC clock source is clocking the device or the INTOSC source is not yet stable. If the internal oscillator block is configured as the primary clock source by the FOSC<3:0> Configuration bits, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable 8 MHz output. Entering another power-managed RC mode at the same frequency would clear the OSTS bit. 3.1.4 MULTIPLE SLEEP COMMANDS The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting. 3.2 Run Modes In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. 3.2.1 PRI_RUN MODE The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up is enabled (see Section 23.3 “Two-Speed Start-up” for details). In this mode, the OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 2.7.1 “Oscillator Control Register”). 3.2.2 SEC_RUN MODE The SEC_RUN mode is the compatible mode to the “clock switching” feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high-accuracy clock source. SEC_RUN mode is entered by setting the SCS<1:0> bits to ‘01’. The device clock source is switched to the Timer1 oscillator (see Figure 3-1), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Note 1: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. 2: Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep mode or one of the Idle modes, depending on the setting of the IDLEN bit. Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS<1:0> bits are set to ‘01’, entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result.© 2008 Microchip Technology Inc. Advance Information DS39631E-page 35 PIC18F2420/2520/4420/4520 FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator block (either INTRC or INTOSC), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. This mode is entered by setting the SCS1 bit to ‘1’. Although it is ignored, it is recommended that the SCS0 bit also be cleared; this is to maintain software compatibility with future devices. When the clock source is switched to the INTOSC multiplexer (see Figure 3-3), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to immediately change the clock speed. Q2 Q3 Q4 OSC1 Peripheral Program Q1 T1OSI Q1 Counter Clock CPU Clock PC PC + 2 1 2 3 n-1 n Clock Transition(1) Q2 Q3 Q4 Q1 Q2 Q3 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. Q1 Q3 Q4 OSC1 Peripheral Program PC T1OSI PLL Clock Q1 PC + 4 Q2 Output Q3 Q4 Q1 CPU Clock PC + 2 Clock Counter Q2 Q2 Q3 Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. SCS<1:0> bits Changed TPLL(1) 1 2 n-1 n Clock OSTS bit Set Transition(2) TOST(1) Note: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated.PIC18F2420/2520/4420/4520 DS39631E-page 36 Advance Information © 2008 Microchip Technology Inc. If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, enabling the INTOSC output), or if INTSRC is set, the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the device continue while the INTOSC source stabilizes after an interval of TIOBST. If the IRCF bits were previously at a non-zero value, or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-4). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q2 Q3 Q4 OSC1 Peripheral Program Q1 INTRC Q1 Counter Clock CPU Clock PC PC + 2 1 2 3 n-1 n Clock Transition(1) Q2 Q3 Q4 Q1 Q2 Q3 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. Q1 Q3 Q4 OSC1 Peripheral Program PC INTOSC PLL Clock Q1 PC + 4 Q2 Output Q3 Q4 Q1 CPU Clock PC + 2 Clock Counter Q2 Q2 Q3 Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. SCS<1:0> bits Changed TPLL(1) 1 2 n-1 n Clock OSTS bit Set Transition(2) Multiplexer TOST(1)© 2008 Microchip Technology Inc. Advance Information DS39631E-page 37 PIC18F2420/2520/4420/4520 3.3 Sleep Mode The power-managed Sleep mode in the PIC18F2420/ 2520/4420/4520 devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 3-6), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 23.0 “Special Features of the CPU”). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS<1:0> bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (parameter 38, Table 26-10) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits. FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q2 Q3 Q4 OSC1 Peripheral Sleep Program Q1 Q1 Counter Clock CPU Clock PC PC + 2 Q3 Q4 Q1 Q2 OSC1 Peripheral Program PC PLL Clock Q3 Q4 Output CPU Clock Q1 Q2 Q3 Q4 Q1 Q2 Clock Counter PC + 4 PC + 6 Q1 Q2 Q3 Q4 Wake Event Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. TOST(1) TPLL(1) OSTS bit Set PC + 2PIC18F2420/2520/4420/4520 DS39631E-page 38 Advance Information © 2008 Microchip Technology Inc. 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm-up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC<3:0> Configuration bits. The OSTS bit remains set (see Figure 3-7). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval TCSD is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-8). 3.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS<1:0> bits to ‘01’ and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After an interval of TCSD, following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run (see Figure 3-8). FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. Q1 Peripheral Program PC PC + 2 OSC1 Q3 Q4 Q1 CPU Clock Clock Counter Q2 OSC1 Peripheral Program PC CPU Clock Q1 Q3 Q4 Clock Counter Q2 Wake Event TCSD© 2008 Microchip Technology Inc. Advance Information DS39631E-page 39 PIC18F2420/2520/4420/4520 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP. Although its value is ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future devices. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer, the primary oscillator is shut down and the OSTS bit is cleared. If the IRCF bits are set to any non-zero value, or the INTSRC bit is set, the INTOSC output is enabled. The IOFS bit becomes set, after the INTOSC output becomes stable, after an interval of TIOBST (parameter 39, Table 26-10). Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were previously at a non-zero value, or INTSRC was set before the SLEEP instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits and INTSRC are all clear, the INTOSC output will not be enabled, the IOFS bit will remain clear and there will be no indication of the current clock source. When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a delay of TCSD following the wake event, the CPU begins executing code being clocked by the INTOSC multiplexer. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. 3.5 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 3.2 “Run Modes”, Section 3.3 “Sleep Mode” and Section 3.4 “Idle Modes”). 3.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode or the Sleep mode to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “Interrupts”). A fixed delay of interval TCSD following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 3.2 “Run Modes” and Section 3.3 “Sleep Mode”). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 23.2 “Watchdog Timer (WDT)”). The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the device clock source. 3.5.3 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready. At that time, the OSTS bit is set and the device begins executing code. If the internal oscillator block is the new clock source, the IOFS bit is set instead. The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator if the new clock source is the primary clock. Exit delays are summarized in Table 3-2. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 23.3 “Two-Speed Start-up”) or Fail-Safe Clock Monitor (see Section 23.4 “Fail-Safe Clock Monitor”) is enabled, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the internal oscillator block until either the primary clock becomes ready or a power-managed mode is entered before the primary clock becomes ready; the primary clock is then shut down.PIC18F2420/2520/4420/4520 DS39631E-page 40 Advance Information © 2008 Microchip Technology Inc. 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped and • the primary clock source is not any of the LP, XT, HS or HSPLL modes. In these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay of interval TCSD following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source Before Wake-up Clock Source After Wake-up Exit Delay Clock Ready Status Bit (OSCCON) Primary Device Clock (PRI_IDLE mode) LP, XT, HS TCSD HSPLL (1) OSTS EC, RC INTOSC(2) IOFS T1OSC or INTRC(1) LP, XT, HS TOST(3) HSPLL TOST + trc OSTS (3) EC, RC TCSD(1) INTOSC(2) TCSD(1) IOFS INTOSC(2) LP, XT, HS TOST(3) HSPLL TOST + trc OSTS (3) EC, RC TCSD(1) INTOSC(2) TCSD(1) IOFS None (Sleep mode) LP, XT, HS TOST(3) HSPLL TOST + trc OSTS (3) EC, RC TCSD(1) INTOSC(2) TCSD(1) IOFS Note 1: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section 3.4 “Idle Modes”). On Reset, INTOSC defaults to 1 MHz. 2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies. 3: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL lock-out timer (parameter F12); it is also designated as TPLL.© 2008 Microchip Technology Inc. DS39631E-page 41 PIC18F2420/2520/4420/4520 4.0 RESET The PIC18F2420/2520/4420/4520 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 5.1.2.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section 23.2 “Watchdog Timer (WDT)”. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 4.6 “Reset State of Registers”. The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in Section 9.0 “Interrupts”. BOR is covered in Section 4.4 “Brown-out Reset (BOR)”. FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR VDD OSC1 WDT Time-out VDD Rise Detect OST/PWRT INTRC(1) POR Pulse OST 10-Bit Ripple Counter PWRT 11-Bit Ripple Counter Enable OST(2) Enable PWRT Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. Brown-out Reset BOREN RESET Instruction Stack Pointer Stack Full/Underflow Reset Sleep ( )_IDLE 1024 Cycles 65.5 ms 32 μs MCLRE S R Q Chip_ResetPIC18F2420/2520/4420/4520 DS39631E-page 42 © 2008 Microchip Technology Inc. REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN1:BOREN0 = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN1:BOREN0 = 00, 10 or 11: Bit is disabled and read as ‘0’. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section 4.6 “Reset State of Registers” for additional information. Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset).© 2008 Microchip Technology Inc. DS39631E-page 43 PIC18F2420/2520/4420/4520 4.2 Master Clear (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F2420/2520/4420/4520 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.5 “PORTE, TRISE and LATE Registers” for more information. 4.3 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. FIGURE 4-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 kΩ is recommended to make sure that the voltage drop across R does not violate the device’s electrical specification. 3: R1 ≥ 1 kΩ will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). C R1 D R VDD MCLR PIC18FXXXX VDDPIC18F2420/2520/4420/4520 DS39631E-page 44 © 2008 Microchip Technology Inc. 4.4 Brown-out Reset (BOR) PIC18F2420/2520/4420/4520 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV<1:0> and BOREN<1:0> Configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV<1:0> bits. If BOR is enabled (any values of BOREN<1:0>, except ‘00’), any drop of VDD below VBOR (parameter D005) for greater than TBOR (parameter 35) will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT (parameter 33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. BOR and the Power-up Timer (PWRT) are independently configured. Enabling the Brown-out Reset does not automatically enable the PWRT. 4.4.1 SOFTWARE ENABLED BOR When BOREN<1:0> = 01, the BOR can be enabled or disabled by the user in software. This is done with the control bit, SBOREN (RCON<6>). Setting SBOREN enables the BOR to function as previously described. Clearing SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise it is read as ‘0’. Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change BOR configuration. It also allows the user to tailor device power consumption in software by eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, it may have some impact in low-power applications. 4.4.2 DETECTING BOR When BOR is enabled, the BOR bit always resets to ‘0’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR bit is reset to ‘1’ in software immediately after any POR event. If BOR is ‘0’ while POR is ‘1’, it can be reliably assumed that a BOR event has occurred. 4.4.3 DISABLING BOR IN SLEEP MODE When BOREN<1:0> = 10, the BOR remains under hardware control and operates as previously described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the device returns to any other operating mode, BOR is automatically re-enabled. This mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. TABLE 4-1: BOR CONFIGURATIONS Note: Even when BOR is under software control, the Brown-out Reset voltage level is still set by the BORV<1:0> Configuration bits; it cannot be changed in software. BOR Configuration Status of SBOREN (RCON<6>) BOR Operation BOREN1 BOREN0 0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR enabled in software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled in hardware; must be disabled by reprogramming the Configuration bits.© 2008 Microchip Technology Inc. DS39631E-page 45 PIC18F2420/2520/4420/4520 4.5 Device Reset Timers PIC18F2420/2520/4420/4520 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of PIC18F2420/2520/ 4420/4520 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μs = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip to chip due to temperature and process variation. See DC parameter 33 for details. The PWRT is enabled by clearing the PWRTEN Configuration bit. 4.5.2 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter 33). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset, or on exit from most power-managed modes. 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out. 4.5.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: 1. After the POR pulse has cleared, PWRT time-out is invoked (if enabled). 2. Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in HS Oscillator mode. Figure 4-3 through Figure 4-6 also apply to devices operating in XT or LP modes. For devices in RC mode and with the PWRT disabled, on the other hand, there will be no time-out at all. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel. TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration Power-up(2) and Brown-out Exit from Power-Managed Mode PWRTEN = 0 PWRTEN = 1 HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) — — RC, RCIO 66 ms(1) — — INTIO1, INTIO2 66 ms(1) — — Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock.PIC18F2420/2520/4420/4520 DS39631E-page 46 © 2008 Microchip Technology Inc. FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 TPWRT TOST VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TPWRT TOST VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TPWRT TOST© 2008 Microchip Technology Inc. DS39631E-page 47 PIC18F2420/2520/4420/4520 FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 0V 5V TPWRT TOST TPWRT TOST VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET PLL TIME-OUT TPLL Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer.PIC18F2420/2520/4420/4520 DS39631E-page 48 © 2008 Microchip Technology Inc. 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 4-3. These bits are used in software to determine the nature of the Reset. Table 4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Condition Program Counter RCON Register STKPTR Register RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 11100 0 0 RESET Instruction 0000h 0uuuu u u Brown-out Reset 0000h 111u0 u u MCLR Reset during Power-Managed Run Modes 0000h u1uuu u u MCLR Reset during Power-Managed Idle Modes and Sleep Mode 0000h u10uu u u WDT Time-out during Full Power or Power-Managed Run Mode 0000h u0uuu u u MCLR Reset during Full-Power Execution 0000h uuuuu u u Stack Full Reset (STVREN = 1) 0000h uuuuu 1 u Stack Underflow Reset (STVREN = 1) 0000h uuuuu u 1 Stack Underflow Error (not an actual Reset, STVREN = 0) 0000h uuuuu u 1 WDT Time-out during Power-Managed Idle or Sleep Modes PC + 2 u00uu u u Interrupt Exit from Power-Managed Modes PC + 2(1) uu0uu u u Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h).© 2008 Microchip Technology Inc. DS39631E-page 49 PIC18F2420/2520/4420/4520 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TOSU 2420 2520 4420 4520 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2420 2520 4420 4520 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 2420 2520 4420 4520 ---0 0000 ---0 0000 ---u uuuu PCLATH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu PCL 2420 2520 4420 4520 0000 0000 0000 0000 PC + 2(2) TBLPTRU 2420 2520 4420 4520 --00 0000 --00 0000 --uu uuuu TBLPTRH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TBLPTRL 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TABLAT 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu PRODH 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 2420 2520 4420 4520 0000 000x 0000 000u uuuu uuuu(1) INTCON2 2420 2520 4420 4520 1111 -1-1 1111 -1-1 uuuu -u-u(1) INTCON3 2420 2520 4420 4520 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 2420 2520 4420 4520 N/A N/A N/A POSTINC0 2420 2520 4420 4520 N/A N/A N/A POSTDEC0 2420 2520 4420 4520 N/A N/A N/A PREINC0 2420 2520 4420 4520 N/A N/A N/A PLUSW0 2420 2520 4420 4520 N/A N/A N/A FSR0H 2420 2520 4420 4520 ---- 0000 ---- 0000 ---- uuuu FSR0L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu WREG 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 2420 2520 4420 4520 N/A N/A N/A POSTINC1 2420 2520 4420 4520 N/A N/A N/A POSTDEC1 2420 2520 4420 4520 N/A N/A N/A PREINC1 2420 2520 4420 4520 N/A N/A N/A PLUSW1 2420 2520 4420 4520 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111.PIC18F2420/2520/4420/4520 DS39631E-page 50 © 2008 Microchip Technology Inc. FSR1H 2420 2520 4420 4520 ---- 0000 ---- 0000 ---- uuuu FSR1L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu BSR 2420 2520 4420 4520 ---- 0000 ---- 0000 ---- uuuu INDF2 2420 2520 4420 4520 N/A N/A N/A POSTINC2 2420 2520 4420 4520 N/A N/A N/A POSTDEC2 2420 2520 4420 4520 N/A N/A N/A PREINC2 2420 2520 4420 4520 N/A N/A N/A PLUSW2 2420 2520 4420 4520 N/A N/A N/A FSR2H 2420 2520 4420 4520 ---- 0000 ---- 0000 ---- uuuu FSR2L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 2420 2520 4420 4520 ---x xxxx ---u uuuu ---u uuuu TMR0H 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TMR0L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu OSCCON 2420 2520 4420 4520 0100 q000 0100 q000 uuuu quuu HLVDCON 2420 2520 4420 4520 0-00 0101 0-00 0101 u-uu uuuu WDTCON 2420 2520 4420 4520 ---- ---0 ---- ---0 ---- ---u RCON(4) 2420 2520 4420 4520 0q-1 11q0 0q-q qquu uq-u qquu TMR1H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 2420 2520 4420 4520 0000 0000 u0uu uuuu uuuu uuuu TMR2 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu PR2 2420 2520 4420 4520 1111 1111 1111 1111 1111 1111 T2CON 2420 2520 4420 4520 -000 0000 -000 0000 -uuu uuuu SSPBUF 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu SSPSTAT 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu SSPCON1 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu SSPCON2 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111.© 2008 Microchip Technology Inc. DS39631E-page 51 PIC18F2420/2520/4420/4520 ADRESH 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2420 2520 4420 4520 --00 0000 --00 0000 --uu uuuu ADCON1 2420 2520 4420 4520 --00 0qqq(6) --00 0qqq(6) --uu uuuu ADCON2 2420 2520 4420 4520 0-00 0000 0-00 0000 u-uu uuuu CCPR1H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu 2420 2520 4420 4520 --00 0000 --00 0000 --uu uuuu CCPR2H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 2420 2520 4420 4520 --00 0000 --00 0000 --uu uuuu BAUDCON 2420 2520 4420 4520 0100 0-00 0100 0-00 uuuu u-uu PWM1CON 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu ECCP1AS 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu 2420 2520 4420 4520 0000 00-- 0000 00-- uuuu uu-- CVRCON 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu CMCON 2420 2520 4420 4520 0000 0111 0000 0111 uuuu uuuu TMR3H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 2420 2520 4420 4520 0000 0000 uuuu uuuu uuuu uuuu SPBRGH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu SPBRG 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu RCREG 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TXREG 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu TXSTA 2420 2520 4420 4520 0000 0010 0000 0010 uuuu uuuu RCSTA 2420 2520 4420 4520 0000 000x 0000 000x uuuu uuuu EEADR 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu EEDATA 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu EECON2 2420 2520 4420 4520 0000 0000 0000 0000 0000 0000 EECON1 2420 2520 4420 4520 xx-0 x000 uu-0 u000 uu-0 u000 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111.PIC18F2420/2520/4420/4520 DS39631E-page 52 © 2008 Microchip Technology Inc. IPR2 2420 2520 4420 4520 11-1 1111 11-1 1111 uu-u uuuu PIR2 2420 2520 4420 4520 00-0 0000 00-0 0000 uu-u uuuu(1) PIE2 2420 2520 4420 4520 00-0 0000 00-0 0000 uu-u uuuu IPR1 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu 2420 2520 4420 4520 -111 1111 -111 1111 -uuu uuuu PIR1 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu(1) 2420 2520 4420 4520 -000 0000 -000 0000 -uuu uuuu(1) PIE1 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu 2420 2520 4420 4520 -000 0000 -000 0000 -uuu uuuu OSCTUNE 2420 2520 4420 4520 00-0 0000 00-0 0000 uu-u uuuu TRISE 2420 2520 4420 4520 0000 -111 0000 -111 uuuu -uuu TRISD 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu TRISC 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu TRISB 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu TRISA(5) 2420 2520 4420 4520 1111 1111(5) 1111 1111(5) uuuu uuuu(5) LATE 2420 2520 4420 4520 ---- -xxx ---- -uuu ---- -uuu LATD 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu LATC 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu LATB 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 2420 2520 4420 4520 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5) PORTE 2420 2520 4420 4520 ---- xxxx ---- uuuu ---- uuuu PORTD 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5) 2420 2520 4420 4520 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111.© 2008 Microchip Technology Inc. DS39631E-page 53 PIC18F2420/2520/4420/4520 5.0 MEMORY ORGANIZATION There are three types of memory in PIC18 enhanced microcontroller devices: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Flash Program Memory”. Data EEPROM is discussed separately in Section 7.0 “Data EEPROM Memory”. 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The PIC18F2420 and PIC18F4420 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions. The PIC18F2520 and PIC18F4520 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory map for PIC18F2420/2520/ 4420/4520 devices is shown in Figure 5-1. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2420/2520/4420/4520 DEVICES PC<20:0> Stack Level 1 • Stack Level 31 Reset Vector Low-Priority Interrupt Vector • • CALL,RCALL,RETURN RETFIE,RETLW 21 0000h 0018h On-Chip Program Memory High-Priority Interrupt Vector 0008h User Memory Space 1FFFFFh 4000h 3FFFh Read ‘0’ 200000h 8000h 7FFFh On-Chip Program Memory Read ‘0’ PIC18F2420/4420 PIC18F2520/4520PIC18F2420/2520/4420/4520 DS39631E-page 54 © 2008 Microchip Technology Inc. 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.1.4.1 “Computed GOTO”). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. 5.1.2 RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-ofStack (TOS) Special Function Registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack; the Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack; the contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to ‘00000’ after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is full, or has overflowed or underflowed. 5.1.2.1 Top-of-Stack Access Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 5-2). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user-defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS 00011 001A34h 11111 11110 11101 00010 00001 00000 00010 Return Address Stack <20:0> Top-of-Stack 000D58h TOSU TOSH TOSL 00h 1Ah 34h STKPTR<4:0> Top-of-Stack Registers Stack Pointer© 2008 Microchip Technology Inc. DS39631E-page 55 PIC18F2420/2520/4420/4520 5.1.2.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 23.1 “Configuration Bits” for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. 5.1.2.3 PUSH and POP Instructions Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. REGISTER 5-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.PIC18F2420/2520/4420/4520 DS39631E-page 56 © 2008 Microchip Technology Inc. 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 5.1.3 FAST REGISTER STACK A Fast Register Stack is provided for the STATUS, WREG and BSR registers, to provide a “fast return” option for interrupts. The stack for each register is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt. If both low and high-priority interrupts are enabled, the stack registers cannot be used reliably to return from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the stack register values stored by the low-priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt. If no interrupts are used, the Fast Register Stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast Register Stack. Example 5-1 shows a source code example that uses the Fast Register Stack during a subroutine call and return. EXAMPLE 5-1: FAST REGISTER STACK CODE EXAMPLE 5.1.4 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • Computed GOTO • Table Reads 5.1.4.1 Computed GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 5-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value ‘nn’ to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. EXAMPLE 5-2: COMPUTED GOTO USING AN OFFSET VALUE 5.1.4.2 Table Reads and Table Writes A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK • • SUB1 • • RETURN, FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK MOVF OFFSET, W CALL TABLE ORG nn00h TABLE ADDWF PCL RETLW nnh RETLW nnh RETLW nnh . . .© 2008 Microchip Technology Inc. DS39631E-page 57 PIC18F2420/2520/4420/4520 5.2 PIC18 Instruction Cycle 5.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the instruction register during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-3. 5.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-3). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 5-3: CLOCK/INSTRUCTION CYCLE EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC mode) PC PC + 2 PC + 4 Fetch INST (PC) Execute INST (PC – 2) Fetch INST (PC + 2) Execute INST (PC) Fetch INST (PC + 4) Execute INST (PC + 2) Internal Phase Clock All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1PIC18F2420/2520/4420/4520 DS39631E-page 58 © 2008 Microchip Technology Inc. 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘0’ (see Section 5.1.1 “Program Counter”). Figure 5-4 shows an example of how instruction words are stored in the program memory. The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-4 shows how the instruction GOTO 0006h is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 24.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY 5.2.4 TWO-WORD INSTRUCTIONS The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instructions always has ‘1111’ as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of ‘1111’ in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence – immediately after the first word – the data in the second word is accessed and used by the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 5-4 shows how this works. EXAMPLE 5-4: TWO-WORD INSTRUCTIONS Word Address LSB = 1 LSB = 0 ↓ Program Memory Byte Locations → 000000h 000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h Note: See Section 5.6 “PIC18 Instruction Execution and the Extended Instruction Set” for information on two-word instructions in the extended instruction set. CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code© 2008 Microchip Technology Inc. DS39631E-page 59 PIC18F2420/2520/4420/4520 5.3 Data Memory Organization The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; PIC18F2420/ 2520/4420/4520 devices implement all 16 banks. Figure 5-5 shows the data memory organization for the PIC18F2420/2520/4420/4520 devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’s application. Any read of an unimplemented location will read as ‘0’s. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the 4 Most Significant bits of a location’s address; the instruction itself includes the 8 Least Significant bits. Only the four lower bits of the BSR are implemented (BSR<3:0>). The upper four bits are unused; they will always read ‘0’ and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory; the 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank’s lower boundary. The relationship between the BSR’s value and the bank division in data memory is shown in Figure 5-7. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h while the BSR is 0Fh will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure 5-5 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. Note: The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.5 “Data Memory and the Extended Instruction Set” for more information.PIC18F2420/2520/4420/4520 DS39631E-page 60 © 2008 Microchip Technology Inc. FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2420/4420 DEVICES Bank 0 Bank 1 Bank 14 Bank 15 BSR<3:0> Data Memory Map = 0000 = 0001 = 1111 080h 07Fh F80h FFFh 00h 7Fh 80h FFh Access Bank When ‘a’ = 0: The BSR is ignored and the Access Bank is used. The first 128 bytes are general purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When ‘a’ = 1: The BSR specifies the Bank used by the instruction. F7Fh F00h EFFh 1FFh 100h 0FFh 000h Access RAM FFh 00h FFh 00h FFh 00h GPR GPR SFR Access RAM High Access RAM Low Bank 2 = 0110 = 0010 (SFRs) 2FFh 200h 3FFh 300h 4FFh 400h 5FFh 500h 6FFh 600h 7FFh 700h 8FFh 800h 9FFh 900h AFFh A00h BFFh B00h CFFh C00h DFFh D00h E00h Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 Bank 13 FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h GPR FFh 00h = 0011 = 0100 = 0101 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 Unused Read 00h Unused© 2008 Microchip Technology Inc. DS39631E-page 61 PIC18F2420/2520/4420/4520 FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2520/4520 DEVICES Bank 0 Bank 1 Bank 14 Bank 15 BSR<3:0> Data Memory Map = 0000 = 0001 = 1111 080h 07Fh F80h FFFh 00h 7Fh 80h FFh Access Bank When ‘a’ = 0: The BSR is ignored and the Access Bank is used. The first 128 bytes are general purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When ‘a’ = 1: The BSR specifies the Bank used by the instruction. F7Fh F00h EFFh 1FFh 100h 0FFh 000h Access RAM FFh 00h FFh 00h FFh 00h GPR GPR SFR Access RAM High Access RAM Low Bank 2 = 0110 = 0010 (SFRs) 2FFh 200h 3FFh 300h 4FFh 400h 5FFh 500h 6FFh 600h 7FFh 700h 8FFh 800h 9FFh 900h AFFh A00h BFFh B00h CFFh C00h DFFh D00h E00h Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 Bank 13 FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h GPR FFh 00h = 0011 = 0100 = 0101 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 Unused Read 00h Unused GPR GPR GPRPIC18F2420/2520/4420/4520 DS39631E-page 62 © 2008 Microchip Technology Inc. FIGURE 5-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 5.3.2 ACCESS BANK While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 128 bytes of memory (00h-7Fh) in Bank 0 and the last 128 bytes of memory (80h-FFh) in Block 15. The lower half is known as the “Access RAM” and is composed of GPRs. This upper half is also where the device’s SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 5-5). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. Using this “forced” addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 80h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 80h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 5.5.3 “Mapping the Access Bank in Indexed Literal Offset Mode”. 5.3.3 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area. This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. Data Memory Bank Select(2) 7 0 From Opcode(2) 0000 000h 100h 200h 300h F00h E00h FFFh Bank 0 Bank 1 Bank 2 Bank 14 Bank 15 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh Bank 3 through Bank 13 0011 11111111 7 0 BSR(1)© 2008 Microchip Technology Inc. DS39631E-page 63 PIC18F2420/2520/4420/4520 5.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these registers is given in Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and Interrupt registers are described in their respective chapters, while the ALU’s STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s. TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2420/2520/4420/4520 DEVICES Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch —(2) FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —(2) FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2) FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2) FF7h TBLPTRH FD7h TMR0H FB7h PWM1CON(3) F97h —(2) FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS(3) F96h TRISE(3) FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(3) FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —(2) FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2) FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2) FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh —(2) FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3) FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3) FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA FE8h WREG FC8h SSPADD FA8h EEDATA F88h —(2) FE7h INDF1(1) FC7h SSPSTAT FA7h EECON2(1) F87h —(2) FE6h POSTINC1(1) FC6h SSPCON1 FA6h EECON1 F86h —(2) FE5h POSTDEC1(1) FC5h SSPCON2 FA5h —(2) F85h —(2) FE4h PREINC1(1) FC4h ADRESH FA4h —(2) F84h PORTE(3) FE3h PLUSW1(1) FC3h ADRESL FA3h —(2) F83h PORTD(3) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is not available on 28-pin devices.PIC18F2420/2520/4420/4520 DS39631E-page 64 © 2008 Microchip Technology Inc. TABLE 5-2: PIC18F2420/2520/4420/4520 REGISTER FILE SUMMARY File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 49, 54 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 49, 54 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 49, 54 STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 49, 55 PCLATU — — — Holding Register for PC<20:16> ---0 0000 49, 54 PCLATH Holding Register for PC<15:8> 0000 0000 49, 54 PCL PC Low Byte (PC<7:0>) 0000 0000 49, 54 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 49, 76 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 49, 76 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 49, 76 TABLAT Program Memory Table Latch 0000 0000 49, 76 PRODH Product Register High Byte xxxx xxxx 49, 89 PRODL Product Register Low Byte xxxx xxxx 49, 89 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 49, 93 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 49, 94 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 49, 95 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 49, 69 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 49, 69 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 49, 69 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 49, 69 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of FSR0 offset by W N/A 49, 69 FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 49, 69 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 49, 69 WREG Working Register xxxx xxxx 49 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 49, 69 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 49, 69 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 49, 69 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 49, 69 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value of FSR1 offset by W N/A 49, 69 FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 50, 69 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 50, 69 BSR — — — — Bank Select Register ---- 0000 50, 59 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 50, 69 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 50, 69 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 50, 69 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 50, 69 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of FSR2 offset by W N/A 50, 69 FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 50, 69 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 50, 69 STATUS — — — N OV Z DC C ---x xxxx 50, 67 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’.© 2008 Microchip Technology Inc. DS39631E-page 65 PIC18F2420/2520/4420/4520 TMR0H Timer0 Register High Byte 0000 0000 50, 125 TMR0L Timer0 Register Low Byte xxxx xxxx 50, 125 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 50, 123 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 30, 50 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 50, 245 WDTCON — — — — — — — SWDTEN --- ---0 50, 259 RCON IPEN SBOREN(1) — RI TO PD POR BOR 0q-1 11q0 42, 48, 102 TMR1H Timer1 Register High Byte xxxx xxxx 50, 132 TMR1L Timer1 Register Low Bytes xxxx xxxx 50, 132 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 50, 127 TMR2 Timer2 Register 0000 0000 50, 134 PR2 Timer2 Period Register 1111 1111 50, 134 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 133 SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 50, 169, 170 SSPADD MSSP Address Register in I2C™ Slave Mode. MSSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 50, 170 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 50, 162, 171 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 50, 163, 172 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 50, 173 ADRESH A/D Result Register High Byte xxxx xxxx 51, 232 ADRESL A/D Result Register Low Byte xxxx xxxx 51, 232 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 51, 223 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 51, 224 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 51, 225 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 51, 140 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 51, 140 CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 51, 139, 147 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 51, 140 CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 51, 140 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 51, 139 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 51, 204 PWM1CON PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 0000 0000 51, 156 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 0000 0000 51, 157 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 51, 239 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 51, 233 TMR3H Timer3 Register High Byte xxxx xxxx 51, 137 TMR3L Timer3 Register Low Byte xxxx xxxx 51, 137 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 51, 135 TABLE 5-2: PIC18F2420/2520/4420/4520 REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’.PIC18F2420/2520/4420/4520 DS39631E-page 66 © 2008 Microchip Technology Inc. SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 51, 206 SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 51, 206 RCREG EUSART Receive Register 0000 0000 51, 213 TXREG EUSART Transmit Register 0000 0000 51, 211 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 51, 202 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 51, 203 EEADR EEPROM Address Register 0000 0000 51, 74, 83 EEDATA EEPROM Data Register 0000 0000 51, 74, 83 EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 51, 74, 83 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 51, 75, 84 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 11-1 1111 52, 101 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 00-0 0000 52, 97 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 00-0 0000 52, 99 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 52, 100 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 52, 96 PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 52, 98 OSCTUNE INTSRC PLLEN(3) — TUN4 TUN3 TUN2 TUN1 TUN0 0q-0 0000 27, 52 TRISE(2) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 52, 118 TRISD(2) PORTD Data Direction Register 1111 1111 52, 114 TRISC PORTC Data Direction Register 1111 1111 52, 111 TRISB PORTB Data Direction Register 1111 1111 52, 108 TRISA TRISA7(5) TRISA6(5) PORTA Data Direction Register 1111 1111 52, 105 LATE(2) — — — — — PORTE Data Latch Register (Read and Write to Data Latch) ---- -xxx 52, 117 LATD(2) PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 114 LATC PORTC Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 111 LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 108 LATA LATA7(5) LATA6(5) PORTA Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 105 PORTE — — — — RE3(4) RE2(2) RE1(2) RE0(2) ---- xxxx 52, 117 PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 52, 114 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 52, 111 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 52, 108 PORTA RA7(5) RA6(5) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 52, 105 TABLE 5-2: PIC18F2420/2520/4420/4520 REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’.© 2008 Microchip Technology Inc. DS39631E-page 67 PIC18F2420/2520/4420/4520 5.3.5 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that do not affect Status bits, see the instruction set summaries in Table 24-2 and Table 24-3. Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. REGISTER 5-2: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. 2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register.PIC18F2420/2520/4420/4520 DS39631E-page 68 © 2008 Microchip Technology Inc. 5.4 Data Addressing Modes While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: • Inherent • Literal • Direct • Indirect An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section 5.5.1 “Indexed Addressing with Literal Offset”. 5.4.1 INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. 5.4.2 DIRECT ADDRESSING Direct Addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.3 “General Purpose Register File”) or a location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “Bank Select Register (BSR)”) are used with the address to determine the complete 12-bit address of the register. When ‘a’ is ‘0’, the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation’s results is determined by the destination bit ‘d’. When ‘d’ is ‘1’, the results are stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in the W register. Instructions without the ‘d’ argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register. 5.4.3 INDIRECT ADDRESSING Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as Special Function Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the example of clearing an entire RAM bank in Example 5-5. EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.5 “Data Memory and the Extended Instruction Set” for more information. LFSR FSR0, 100h; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H, 1; All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue © 2008 Microchip Technology Inc. DS39631E-page 69 PIC18F2420/2520/4420/4520 5.4.3.1 FSR Registers and the INDF Operand At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as “virtual” registers: they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target. The INDF operand is just a convenient way of using the pointer. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on it stored value. They are: • POSTDEC: accesses the FSR value, then automatically decrements it by 1 afterwards • POSTINC: accesses the FSR value, then automatically increments it by 1 afterwards • PREINC: increments the FSR value by 1, then uses it in the operation • PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the new value in the operation. In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value offset by that in the W register; neither value is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers. Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). FIGURE 5-8: INDIRECT ADDRESSING FSR1H:FSR1L 7 0 Data Memory 000h 100h 200h 300h F00h E00h FFFh Bank 0 Bank 1 Bank 2 Bank 14 Bank 15 Bank 3 through Bank 13 ADDWF, INDF1, 1 7 0 Using an instruction with one of the Indirect Addressing registers as the operand.... ...uses the 12-bit address stored in the FSR pair associated with that register.... ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. xxxx 1110 11001100PIC18F2420/2520/4420/4520 DS39631E-page 70 © 2008 Microchip Technology Inc. The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 5.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses indirect addressing. Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 5.5 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged. 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair within Access RAM. Under the proper conditions, instructions that use the Access Bank – that is, most bit-oriented and byte-oriented instructions – can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. When using the extended instruction set, this addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0) and • The file address argument is less than or equal to 5Fh.