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• Title: Une approche interdisciplinaire des grandes masses de données (Défi Mastodons)

• Speaker: Mokrane Bouzeghoub

• Abstract: De nombreux domaines scientifiques (ex : cartographie du génome, observatoire virtuel en astronomie, simulation en physique et énergie), économiques (ex : e-commerce, systèmes décisionnels), ou sociétaux (ex : réseaux sociaux, bibliothèques numériques, distribution de contenus multimédia) produisent et consomment des volumes de données considérables. Le CNRS, à travers ses unités de recherche et ses grands instruments, capitalise plusieurs centaines, voire milliers, de bases de données et de corpus d'informations dont les volumes croissent de façon exponentielle. Le but du défi MASTODONS est d'identifier et de soutenir des actions de recherche dont les résultats ne pourraient être obtenus sans une fertilisation croisée et sans une synergie effective entre chercheurs de différentes disciplines. Ces actions de recherche doivent couvrir aussi bien les verrous scientifiques posés par l'utilisation à grande échelle des données (sémantique, stockage, recherche, visualisation, ...) que l'impact sociétal qu'induisent les technologies proposées (protection de la vie privée, préservation de la connaissance, ...). L'exposé fait le point sur cette approche interdisciplinaire des masses de données et sur les enjeux scientifiques et économique de cette problématique, en particulier dans le contexte d'un organisme scientifique comme le CNRS.

• Slides: PDF

• Affiliation: Université de Versailles Saint-Quentin-en-Yvelines – CNRS INS2I Institut des Sciences de l'Information et de leurs Interactions

• Email: Mokrane.Bouzeghoub@cnrs-dir.fr

• Web Site: www.prism.uvsq.fr/~mok/Bienv.html

Reset Value (hex) Reg. Descr. 7 6 5 4 3 2 10 with Link 80 RESERVED 81 SP SP[7:0] 07 Stack Pointer (SP), page 21 82 DPL DPL[7:0] 00 Data Pointer (DPTR), p age 21 83 DPH DPH[7:0] 00 84 RESERVED 85 DPTC – AT – – – DPSEL[2:0] 00 Table 13., page 37 86 DPTM – – – – MD1[1:0] MD0[1:0] 00 Table 14., page 38 87 PCON SMOD0 SMOD1 – POR RCLK1 TCLK1 PD IDLE 00 Table 24., page 50 88(1) TCON TF1 <8Fh> TR1 <8Eh> TF0 <8Dh> TR0 <8Ch> IE1 <8Bh> IT1 <8Ah> IE0 <89h> IT0 <88h> 00 Table 39., page 70 89 TMOD GATE C/T M1 M0 GATE C/T M1 M0 00 Table 40., page 72 8A TL0 TL0[7:0] 00 Standard Timer SFRs, pag e 69 8B TL1 TL1[7:0] 00 8C TH0 TH0[7:0] 00 8D TH1 TH1[7:0] 00 8E P1SFS0 P1SFS0[7:0] 00 Table 29., page 60 8F P1SFS1 P1SFS1[7:0] 00 Table 30., page 60 90(1) P1 P1.7 <97h> P1.6 <96h> P1.5 <95h> P1.4 <94h> P1.3 <93h> P1.2 <92h> P1.1 <91h> P1.0 <90h> FF Table 25., page 57 91 P3SFS P3SFS[7:0] 00 Table 28., page 60 92 P4SFS0 P4SFS0[7:0] 00 Table 32., page 61 93 P4SFS1 P4SFS1[7:0] 00 Table 33., page 6125/231 uPSD33xx 94 ADCPS – – – – ADCCE ADCPS[2:0] 00 Table 64., page 122 95 ADAT0 ADATA[7:0] 00 Table 65., page 122 96 ADAT1 – – – – – – ADATA[9:8] 00 Table 66., page 122 97 ACON AINTF AINTEN ADEN ADS[2:0] ADST ADSF 00 Table 63., page 121 98(1) SCON0 SM0 <9Fh> SM1 <9Eh> SM2 <9Dh> REN <9Ch> TB8 <9Bh> RB8 <9Ah> TI <99h> RI <9h8> 00 Table 45., page 82 99 SBUF0 SBUF0[7:0] 00 Figure 25., page 79 9A RESERVED 9B RESERVED 9C RESERVED 9D BUSCON EPFQ EBC WRW1 WRW0 RDW1 RDW0 CW1 CW0 EB Table 35., page 63 9E RESERVED 9F RESERVED A0 RESERVED A1 RESERVED A2 PCACL0 PCACL0[7:0] 00 Table 67., page 124 A3 PCACH0 PCACH0[7:0] 00 Table 67., page 124 A4 PCACON0 EN_ALL EN_PCA EOVF1 PCA_IDL – – CLK_SEL[1:0] 00 Table 70., page 129 A5 PCASTA OVF1 INTF5 INTF4 INTF3 OVF0 INTF2 INTF1 INTF0 00 Table 72., page 131 A6 WDTRST WDTRST[7:0] 00 Table 38., page 68 A7 IEA EADC ESPI EPCA ES1 – – EI2C – 00 Table 18., page 44 SFR Addr (hex) SFR Name Bit Name and Reset Value (hex) Reg. Descr. 7 6 5 4 3 2 10 with LinkuPSD33xx 26/231 A8(1) IE EA – ET2 ES0 ET1 EX1 ET0 EX0 00 Table 17., page 43 A9 TCMMODE 0 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00 Table 73., page 132 AA TCMMODE 1 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00 AB TCMMODE 2 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00 AC CAPCOML 0 CAPCOML0[7:0] 00 Table 67., page 124 AD CAPCOMH 0 CAPCOMH0[7:0] 00 AE WDTKEY WDTKEY[7:0] 55 Table 37., page 68 AF CAPCOML 1 CAPCOML1[7:0] 00 Table 67., page 124 B0(1) P3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 FF Table 26., page 58 B1 CAPCOMH 1 CAPCOMH1[7:0] 00 Table 67., page 124 B2 CAPCOML 2 CAPCOML2[7:0] 00 B3 CAPCOMH 2 CAPCOMH2[7:0] 00 B4 PWMF0 PWMF0[7:0] 00 B5 RESERVED B6 RESERVED B7 IPA PADC PSPI PPCA PS1 – – PI2C – 00 Table 20., page 45 B8(1) IP – – PT2 PS0 PT1 PX1 PT0 PX0 00 Table 19., page 44 B9 RESERVED BA PCACL1 PCACL1[7:0] 00 Table 67., page BB PCACH1 PCACH1[7:0] 00 124 BC Table 2671 page 12027/231 uPSD33xx BD TCMMODE 3 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00 Table 73., page 132 BE TCMMODE 4 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00 BF TCMMODE 5 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00 C0(1) P4 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 FF Table 27., page 58 C1 CAPCOML 3 CAPCOML3[7:0] 00 Table 67., page 124 C2 CAPCOMH 3 CAPCOMH3[7:0] 00 C3 CAPCOML 4 CAPCOML4[7:0] 00 C4 CAPCOMH 4 CAPCOMH4[7:0] 00 C5 CAPCOML 5 CAPCOML5[7:0] 00 C6 CAPCOMH 5 CAPCOMH5[7:0] 00 C7 PWMF1 PWMF1[7:0] 00 C8(1) T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/ RL2 00 Table 41., page 75 C9 RESERVED CA RCAP2L RCAP2L[7:0] 00 Standard Timer SFRs, pag e 69 CB RCAP2H RCAP2H[7:0] 00 CC TL2 TL2[7:0] 00 CD TH2 TH2[7:0] 00 CE IRDACON – IRDA_EN BIT_PULS CDIV4 CDIV3 CDIV2 CDIV1 CDIV0 0F Table 48., page 93 D0(1) PSW CY AC F0 RS[1:0] OV – P 00 Program Status Word (PSW), pa ge 22 D1 RESERVED D2 SPICLKD SPICLKD[5:0] – – 04 Table 61., page 118 D3 SPISTAT – – – BUSY TEISF RORISF TISF RISF 02 Table 62., page 119 SFR Addr (hex) SFR Name Bit Name and Reset Value (hex) Reg. Descr. 7 6 5 4 3 2 10 with LinkuPSD33xx 28/231 D4 SPITDR SPITDR[7:0] 00 Table 62., page D5 SPIRDR SPIRDR[7:0] 00 119 D6 SPICON0 – TE RE SPIEN SSEL FLSB SPO – 00 Table 59., page 117 D7 SPICON1 – – – – TEIE RORIE TIE RIE 00 Table 60., page 118 D8(1) SCON1 SM0 SM2

REN TB8 RB8 TI RI 00 Table 46., page 83 D9 SBUF1 SBUF1[7:0] 00 Figure 25., page 79 DA RESERVED DB S1SETUP SS_EN SMPL_SET[6:0] 00 Table 55., page 105 DC S1CON CR2 EN1 STA STO ADDR AA CR1 CR0 00 Table 50., page 100 DD S1STA GC STOP INTR TX_MD B_BUSY B_LOST ACK_R SLV 00 Table 52., page 103 DE S1DAT S1DAT[7:0] 00 Table 53., page 104 DF S1ADR S1ADR[7:0] 00 Table 54., page 104 E0(1) A A[7:0] 00 Accumulat or (ACC), pa ge 21 E1 to EF RESERVED F0(1) B B[7:0] 00 B Register (B), page 21 F1 RESERVED F2 RESERVED F3 RESERVED F4 RESERVED F5 RESERVED F6 RESERVED SFR Addr (hex) SFR Name Bit Name and Reset Value (hex) Reg. Descr. 7 6 5 4 3 2 10 with Link29/231 uPSD33xx Note: 1. This SFR can be addressed by individual bits (Bit Address mode) or addressed by the entire byte (Direct Address mode). F7 RESERVED F8 RESERVED F9 CCON0 – – – DBGCE CPU_AR CPUPS[2:0] 10 Table 21., page 47 FA RESERVED FB CCON2 – – – PCA0CE PCA0PS[3:0] 10 Table 68., page 125 FC CCON3 – – – PCA1CE PCA1PS[3:0] 10 Table 69., page 125 FD RESERVED FE RESERVED FF RESERVED SFR Addr (hex) SFR Name Bit Name and Reset Value (hex) Reg. Descr. 7 6 5 4 3 2 10 with LinkuPSD33xx 30/231 8032 ADDRESSING MODES The 8032 MCU uses 11 different addressing modes listed below: ■ Register ■ Direct ■ Register Indirect ■ Immediate ■ External Direct ■ External Indirect ■ Indexed ■ Relative ■ Absolute ■ Long ■ Bit Register Addressing This mode uses the contents of one of the registers R0 - R7 (selected by the last three bits in the instruction opcode) as the operand source or destination. This mode is very efficient since an additional instruction byte is not needed to identify the operand. For example: Direct Addressing This mode uses an 8-bit address, which is contained in the second byte of the instruction, to directly address an operand which resides in either 8032 DATA SRAM (internal address range 00h- 07Fh) or resides in 8032 SFR (internal address range 80h-FFh). This mode is quite fast since the range limit is 256 bytes of internal 8032 SRAM. For example: Register Indirect Addressing This mode uses an 8-bit address contained in either Register R0 or R1 to indirectly address an operand which resides in 8032 IDATA SRAM (internal address range 80h-FFh). Although 8032 SFR registers also occupy the same physical address range as IDATA, SFRs will not be accessed by Register Indirect mode. SFRs may only be accesses using Direct address mode. For example: Immediate Addressing This mode uses 8-bits of data (a constant) contained in the second byte of the instruction, and stores it into the memory location or register indicated by the first byte of the instruction. Thus, the data is immediately available within the instruction. This mode is commonly used to initialize registers and SFRs or to perform mask operations. There is also a 16-bit version of this mode for loading the DPTR Register. In this case, the two bytes following the instruction byte contain the 16-bit value. For example: External Direct Addressing This mode will access external memory (XDATA) by using the 16-bit address stored in the DPTR Register. There are only two instructions using this mode and both use the accumulator to either receive a byte from external memory addressed by DPTR or to send a byte from the accumulator to the address in DPTR. The uPSD33xx has a special feature to alternate the contents (source and destination) of DPTR rapidly to implement very efficient memory-to-memory transfers. For example: Note: See details in DUAL DATA POINTERS, page 37. External Indirect Addressing This mode will access external memory (XDATA) by using the 8-bit address stored in either Register R0 or R1. This is the fastest way to access XDATA (least bus cycles), but because only 8-bits are available for address, this mode limits XDATA to a size of only 256 bytes (the traditional Port 2 of the 8032 MCU is not available in the uPSD33xx, so it is not possible to write the upper address byte). This mode is not supported by uPSD33xx. For example: MOV A, R7 ; Move contents of R7 to accumulator MOV A, 40h ; Move contents of DATA SRAM ; at location 40h into the accumulator MOV A, @R0 ; Move into the accumulator the ; contents of IDATA SRAM that is ; pointed to by the address ; contained in R0. MOV A, 40# ; Move the constant, 40h, into ; the accumulator MOV DPTR, 1234# ; Move the constant, 1234h, into ; DPTR MOVX A, @DPTR ; Move contents of accumulator to ; XDATA at address contained in ; DPTR MOVX @DPTR, A ; Move XDATA to accumulator MOVX @R0,A ; Move into the accumulator the ; XDATA that is pointed to by ; the address contained in R0.31/231 uPSD33xx Indexed Addressing This mode is used for the MOVC instruction which allows the 8032 to read a constant from program memory (not data memory). MOVC is often used to read look-up tables that are embedded in program memory. The final address produced by this mode is the result of adding either the 16-bit PC or DPTR value to the contents of the accumulator. The value in the accumulator is referred to as an index. The data fetched from the final location in program memory is stored into the accumulator, overwriting the index value that was previously stored there. For example: Relative Addressing This mode will add the two’s-compliment number stored in the second byte of the instruction to the program counter for short jumps within +128 or – 127 addresses relative to the program counter. This is commonly used for looping and is very efficient since no additional bus cycle is needed to fetch the jump destination address. For example: Absolute Addressing This mode will append the 5 high-order bits of the address of the next instruction to the 11 low-order bits of an ACALL or AJUMP instruction to produce a 16-bit jump address. The jump will be within the same 2K byte page of program memory as the first byte of the following instruction. For example: Long Addressing This mode will use the 16-bits contained in the two bytes following the instruction byte as a jump destination address for LCALL and LJMP instructions. For example: Bit Addressing This mode allows setting or clearing an individual bit without disturbing the other bits within an 8-bit value of internal SRAM. Bit Addressing is only available for certain locations in 8032 DATA and SFR memory. Valid locations are DATA addresses 20h - 2Fh and for SFR addresses whose base address ends with 0h or 8h. (Example: The SFR, IE, has a base address of A8h, so each of the eight bits in IE can be addressed individually at address A8h, A9h, ...up to AFh.) For example: MOVC A, @A+DPTR; Move code byte relative to ; DPTR into accumulator MOVC A, @A+PC ; Move code byte relative to PC ; into accumulator SJMP 34h ; Jump 34h bytes ahead (in program ; memory) of the address at which ; the SJMP instruction is stored. If ; SJMP is at 1000h, program ; execution jumps to 1034h. AJMP 0500h ; If next instruction is located at ; address 4000h, the resulting jump ; will be made to 4500h. LJMP 0500h ; Unconditionally jump to address ; 0500h in program memory SETB AFh ; Set the individual EA bit (Enable All ; Interrupts) inside the SFR Register, ; IE. uPSD33xx 32/231 uPSD33xx INSTRUCTION SET SUMMARY Tables 6 through 11 list all of the instructions supported by the uPSD33xx, including the number of bytes and number of machine cycles required to implement each instruction. This is the standard 8051 instruction set. The meaning of “machine cycles” is how many 8032 MCU core machine cycles are required to execute the instruction. The “native” duration of all machine cycles is set by the memory wait state settings in the SFR, BUSCON, and the MCU clock divider selections in the SFR, CCON0 (i.e. a machine cycle is typically set to 4 MCU clocks for a 5V uPSD33xx). However, an individual machine cycle may grow in duration when either of two things happen: 1. a stall is imposed while loading the 8032 PreFetch Queue (PFQ); or 2. the occurrence of a cache miss in the Branch Cache (BC) during a branch in program execution flow. See 8032 MCU CORE PERFORMANCE ENHANCEMENTS, page 17 or more details. But generally speaking, during typical program execution, the PFQ is not empty and the BC has no misses, producing very good performance without extending the duration of any machine cycles. The uPSD33xx Programmers Guide describes each instruction operation in detail. Table 6. Arithmetic Instruction Set Note: 1. All mnemonics copyrighted ©Intel Corporation 1980. Mnemonic(1) and Use Description Length/Cycles ADD A, Rn Add register to ACC 1 byte/1 cycle ADD A, Direct Add direct byte to ACC 2 byte/1 cycle ADD A, @Ri Add indirect SRAM to ACC 1 byte/1 cycle ADD A, #data Add immediate data to ACC 2 byte/1 cycle ADDC A, Rn Add register to ACC with carry 1 byte/1 cycle ADDC A, direct Add direct byte to ACC with carry 2 byte/1 cycle ADDC A, @Ri Add indirect SRAM to ACC with carry 1 byte/1 cycle ADDC A, #data Add immediate data to ACC with carry 2 byte/1 cycle SUBB A, Rn Subtract register from ACC with borrow 1 byte/1 cycle SUBB A, direct Subtract direct byte from ACC with borrow 2 byte/1 cycle SUBB A, @Ri Subtract indirect SRAM from ACC with borrow 1 byte/1 cycle SUBB A, #data Subtract immediate data from ACC with borrow 2 byte/1 cycle INC A Increment A 1 byte/1 cycle INC Rn Increment register 1 byte/1 cycle INC direct Increment direct byte 2 byte/1 cycle INC @Ri Increment indirect SRAM 1 byte/1 cycle DEC A Decrement ACC 1 byte/1 cycle DEC Rn Decrement register 1 byte/1 cycle DEC direct Decrement direct byte 2 byte/1 cycle DEC @Ri Decrement indirect SRAM 1 byte/1 cycle INC DPTR Increment Data Pointer 1 byte/2 cycle MUL AB Multiply ACC and B 1 byte/4 cycle DIV AB Divide ACC by B 1 byte/4 cycle DA A Decimal adjust ACC 1 byte/1 cycle33/231 uPSD33xx Table 7. Logical Instruction Set Note: 1. All mnemonics copyrighted ©Intel Corporation 1980. Mnemonic(1) and Use Description Length/Cycles ANL A, Rn AND register to ACC 1 byte/1 cycle ANL A, direct AND direct byte to ACC 2 byte/1 cycle ANL A, @Ri AND indirect SRAM to ACC 1 byte/1 cycle ANL A, #data AND immediate data to ACC 2 byte/1 cycle ANL direct, A AND ACC to direct byte 2 byte/1 cycle ANL direct, #data AND immediate data to direct byte 3 byte/2 cycle ORL A, Rn OR register to ACC 1 byte/1 cycle ORL A, direct OR direct byte to ACC 2 byte/1 cycle ORL A, @Ri OR indirect SRAM to ACC 1 byte/1 cycle ORL A, #data OR immediate data to ACC 2 byte/1 cycle ORL direct, A OR ACC to direct byte 2 byte/1 cycle ORL direct, #data OR immediate data to direct byte 3 byte/2 cycle SWAP A Swap nibbles within the ACC 1 byte/1 cycle XRL A, Rn Exclusive-OR register to ACC 1 byte/1 cycle XRL A, direct Exclusive-OR direct byte to ACC 2 byte/1 cycle XRL A, @Ri Exclusive-OR indirect SRAM to ACC 1 byte/1 cycle XRL A, #data Exclusive-OR immediate data to ACC 2 byte/1 cycle XRL direct, A Exclusive-OR ACC to direct byte 2 byte/1 cycle XRL direct, #data Exclusive-OR immediate data to direct byte 3 byte/2 cycle CLR A Clear ACC 1 byte/1 cycle CPL A Compliment ACC 1 byte/1 cycle RL A Rotate ACC left 1 byte/1 cycle RLC A Rotate ACC left through the carry 1 byte/1 cycle RR A Rotate ACC right 1 byte/1 cycle RRC A Rotate ACC right through the carry 1 byte/1 cycleuPSD33xx 34/231 Table 8. Data Transfer Instruction Set Note: 1. All mnemonics copyrighted ©Intel Corporation 1980. Mnemonic(1) and Use Description Length/Cycles MOV A, Rn Move register to ACC 1 byte/1 cycle MOV A, direct Move direct byte to ACC 2 byte/1 cycle MOV A, @Ri Move indirect SRAM to ACC 1 byte/1 cycle MOV A, #data Move immediate data to ACC 2 byte/1 cycle MOV Rn, A Move ACC to register 1 byte/1 cycle MOV Rn, direct Move direct byte to register 2 byte/2 cycle MOV Rn, #data Move immediate data to register 2 byte/1 cycle MOV direct, A Move ACC to direct byte 2 byte/1 cycle MOV direct, Rn Move register to direct byte 2 byte/2 cycle MOV direct, direct Move direct byte to direct 3 byte/2 cycle MOV direct, @Ri Move indirect SRAM to direct byte 2 byte/2 cycle MOV direct, #data Move immediate data to direct byte 3 byte/2 cycle MOV @Ri, A Move ACC to indirect SRAM 1 byte/1 cycle MOV @Ri, direct Move direct byte to indirect SRAM 2 byte/2 cycle MOV @Ri, #data Move immediate data to indirect SRAM 2 byte/1 cycle MOV DPTR, #data16 Load Data Pointer with 16-bit constant 3 byte/2 cycle MOVC A, @A+DPTR Move code byte relative to DPTR to ACC 1 byte/2 cycle MOVC A, @A+PC Move code byte relative to PC to ACC 1 byte/2 cycle MOVX A, @Ri Move XDATA (8-bit addr) to ACC 1 byte/2 cycle MOVX A, @DPTR Move XDATA (16-bit addr) to ACC 1 byte/2 cycle MOVX @Ri, A Move ACC to XDATA (8-bit addr) 1 byte/2 cycle MOVX @DPTR, A Move ACC to XDATA (16-bit addr) 1 byte/2 cycle PUSH direct Push direct byte onto stack 2 byte/2 cycle POP direct Pop direct byte from stack 2 byte/2 cycle XCH A, Rn Exchange register with ACC 1 byte/1 cycle XCH A, direct Exchange direct byte with ACC 2 byte/1 cycle XCH A, @Ri Exchange indirect SRAM with ACC 1 byte/1 cycle XCHD A, @Ri Exchange low-order digit indirect SRAM with ACC 1 byte/1 cycle35/231 uPSD33xx Table 9. Boolean Variable Manipulation Instruction Set Note: 1. All mnemonics copyrighted ©Intel Corporation 1980. Mnemonic(1) and Use Description Length/Cycles CLR C Clear carry 1 byte/1 cycle CLR bit Clear direct bit 2 byte/1 cycle SETB C Set carry 1 byte/1 cycle SETB bit Set direct bit 2 byte/1 cycle CPL C Compliment carry 1 byte/1 cycle CPL bit Compliment direct bit 2 byte/1 cycle ANL C, bit AND direct bit to carry 2 byte/2 cycle ANL C, /bit AND compliment of direct bit to carry 2 byte/2 cycle ORL C, bit OR direct bit to carry 2 byte/2 cycle ORL C, /bit OR compliment of direct bit to carry 2 byte/2 cycle MOV C, bit Move direct bit to carry 2 byte/1 cycle MOV bit, C Move carry to direct bit 2 byte/2 cycle JC rel Jump if carry is set 2 byte/2 cycle JNC rel Jump if carry is not set 2 byte/2 cycle JB rel Jump if direct bit is set 3 byte/2 cycle JNB rel Jump if direct bit is not set 3 byte/2 cycle JBC bit, rel Jump if direct bit is set and clear bit 3 byte/2 cycleuPSD33xx 36/231 Table 10. Program Branching Instruction Set Note: 1. All mnemonics copyrighted ©Intel Corporation 1980. Table 11. Miscellaneous Instruction Set Note: 1. All mnemonics copyrighted ©Intel Corporation 1980. Table 12. Notes on Instruction Set and Addressing Modes Mnemonic(1) and Use Description Length/Cycles ACALL addr11 Absolute subroutine call 2 byte/2 cycle LCALL addr16 Long subroutine call 3 byte/2 cycle RET Return from subroutine 1 byte/2 cycle RETI Return from interrupt 1 byte/2 cycle AJMP addr11 Absolute jump 2 byte/2 cycle LJMP addr16 Long jump 3 byte/2 cycle SJMP rel Short jump (relative addr) 2 byte/2 cycle JMP @A+DPTR Jump indirect relative to the DPTR 1 byte/2 cycle JZ rel Jump if ACC is zero 2 byte/2 cycle JNZ rel Jump if ACC is not zero 2 byte/2 cycle CJNE A, direct, rel Compare direct byte to ACC, jump if not equal 3 byte/2 cycle CJNE A, #data, rel Compare immediate to ACC, jump if not equal 3 byte/2 cycle CJNE Rn, #data, rel Compare immediate to register, jump if not equal 3 byte/2 cycle CJNE @Ri, #data, rel Compare immediate to indirect, jump if not equal 3 byte/2 cycle DJNZ Rn, rel Decrement register and jump if not zero 2 byte/2 cycle DJNZ direct, rel Decrement direct byte and jump if not zero 3 byte/2 cycle Mnemonic(1) and Use Description Length/Cycles NOP No Operation 1 byte/1 cycle Rn Register R0 - R7 of the currently selected register bank. direct 8-bit address for internal 8032 DATA SRAM (locations 00h - 7Fh) or SFR registers (locations 80h - FFh). @Ri 8-bit internal 8032 SRAM (locations 00h - FFh) addressed indirectly through contents of R0 or R1. #data 8-bit constant included within the instruction. #data16 16-bit constant included within the instruction. addr16 16-bit destination address used by LCALL and LJMP. addr11 11-bit destination address used by ACALL and AJMP. rel Signed (two-s compliment) 8-bit offset byte. bit Direct addressed bit in internal 8032 DATA SRAM (locations 20h to 2Fh) or in SFR registers (88h, 90h, 98h, A8h, B0, B8h, C0h, C8h, D0h, D8h, E0h, F0h).37/231 uPSD33xx DUAL DATA POINTERS XDATA is accessed by the External Direct addressing mode, which uses a 16-bit address stored in the DPTR Register. Traditional 8032 architecture has only one DPTR Register. This is a burden when transferring data between two XDATA locations because it requires heavy use of the working registers to manipulate the source and destination pointers. However, the uPSD33xx has two data pointers, one for storing a source address and the other for storing a destination address. These pointers can be configured to automatically increment or decrement after each data transfer, further reducing the burden on the 8032 and making this kind of data movement very efficient. Data Pointer Control Register, DPTC (85h) By default, the DPTR Register of the uPSD33xx will behave no different than in a standard 8032 MCU. The DPSEL0 Bit of SFR register DPTC shown in Table 13, selects which one of the two “background” data pointer registers (DPTR0 or DPTR1) will function as the traditional DPTR Register at any given time. After reset, the DPSEL0 Bit is cleared, enabling DPTR0 to function as the DPTR, and firmware may access DPTR0 by reading or writing the traditional DPTR Register at SFR addresses 82h and 83h. When the DPSEL0 bit is set, then the DPTR1 Register functions as DPTR, and firmware may now access DPTR1 through SFR registers at 82h and 83h. The pointer which is not selected by the DPSEL0 bit remains in the background and is not accessible by the 8032. If the DPSEL0 bit is never set, then the uPSD33xx will behave like a traditional 8032 having only one DPTR Register. To further speed XDATA to XDATA transfers, the SFR bit, AT, may be set to automatically toggle the two data pointers, DPTR0 and DPTR1, each time the standard DPTR Register is accessed by a MOVX instruction. This eliminates the need for firmware to manually manipulate the DPSEL0 bit between each data transfer. Detailed description for the SFR register DPTC is shown in Table 13. Table 13. DPTC: Data Pointer Control Register (SFR 85h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – AT – – – – – DPSEL0 Details Bit Symbol R/W Definition 7 – – Reserved 6 AT R,W 0 = Manually Select Data Pointer 1 = Auto Toggle between DPTR0 and DPTR1 5-1 – – Reserved 0 DPSE0 R,W 0 = DPTR0 Selected for use as DPTR 1 = DPTR1 Selected for use as DPTRuPSD33xx 38/231 Data Pointer Mode Register, DPTM (86h) The two “background” data pointers, DPTR0 and DPTR1, can be configured to automatically increment, decrement, or stay the same after a MOVX instruction accesses the DPTR Register. Only the currently selected pointer will be affected by the increment or decrement. This feature is controlled by the DPTM Register defined in Table 14. The automatic increment or decrement function is effective only for the MOVX instruction, and not MOVC or any other instruction that uses the DTPR Register. Firmware Example. The 8051 assembly code illustrated in Table 15 shows how to transfer a block of data bytes from one XDATA address region to another XDATA address region. Auto-address incrementing and auto-pointer toggling will be used. Table 14. DPTM: Data Pointer Mode Register (SFR 86h, reset value 00h) Table 15. 8051 Assembly Code Example Note: 1. The code loop where the data transfer takes place is only 3 lines of code. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – – MD11 MD10 MD01 MD00 Details Bit Symbol R/W Definition 7-4 – – Reserved 3-2 MD[11:10] R,W DPTR1 Mode Bits 00: DPTR1 No Change 01: Reserved 10: Auto Increment 11: Auto Decrement 1-0 MD[01:00] R,W DPTR0 Mode Bits 00: DPTR0 No Change 01: Reserved 10: Auto Increment 11: Auto Decrement MOV R7, #COUNT ; initialize size of data block to transfer MOV DPTR, #SOURCE_ADDR ; load XDATA source address base into DPTR0 MOV 85h, #01h ; load DPTC to access DPTR1 pointer MOV DPTR, #DEST_ADDR ; load XDATA destination address base into DPTR1 MOV 85h, #40h ; load DPTC to access DPTR0 pointer and auto toggle MOV 86h, #0Ah ; load DPTM to auto-increment both pointers LOOP: MOVX(1) A, @DPTR ; load XDATA byte from source into ACC. ; after load completes, DPTR0 increments and DPTR ; switches DPTR1 MOVX(1) @DPTR, A ; store XDATA byte from ACC to destination. ; after store completes, DPTR1 increments and DPTR ; switches to DPTR0 DJNZ(1) R7, LOOP ; continue until done MOV 86h, #00 ; disable auto-increment MOV 85h, #00 ; disable auto-toggle, now back to single DPTR mode39/231 uPSD33xx DEBUG UNIT The 8032 MCU Module supports run-time debugging through the JTAG interface. This same JTAG interface is also used for In-System Programming (ISP) and the physical connections are described in the PSD Module section, JTAG ISP and JTAG Debug, page 195. Debugging with a serial interface such as JTAG is a non-intrusive way to gain access to the internal state of the 8032 MCU core and various memories. A traditional external hardware emulator cannot be completely effective on the uPSD33xx because of the Pre-Fetch Queue and Branch Cache. The nature of the PFQ and BC hide the visibility of actual program flow through traditional external bus connections, thus requiring on-chip serial debugging instead. Debugging is supported by Windows PC based software tools used for 8051 code development from 3rd party vendors listed at www.st.com/psm. Debug capabilities include: ■ Halt or Start MCU execution ■ Reset the MCU ■ Single Step ■ 3 Match Breakpoints ■ 1 Range Breakpoint (inside or outside range) ■ Program Tracing ■ Read or Modify MCU core registers, DATA, IDATA, SFR, XDATA, and Code ■ External Debug Event Pin, Input or Output Some key points regarding use of the JTAG Debugger. – The JTAG Debugger can access MCU registers, data memory, and code memory while the MCU is executing at full speed by cycle-stealing. This means “watch windows” may be displayed and periodically updated on the PC during full speed operation. Registers and data content may also be modified during full speed operation. – There is no on-chip storage for Program Trace data, but instead this data is scanned from the uPSD33xx through the JTAG channel at runtime to the PC host for proccessing. As such, full speed program tracing is possible only when the 8032 MCU is operating below approximately one MIPS of performance. Above one MIPS, the program will not run real-time while tracing. One MIPS performance is determined by the combination of choice for MCU clock frequency, and the bit settings in SFR registers BUSCON and CCON0. – Breakpoints can optionally halt the MCU, and/ or assert the external Debug Event pin. – Breakpoint definitions may be qualified with read or write operations, and may also be qualified with an address of code, SFR, DATA, IDATA, or XDATA memories. – Three breakpoints will compare an address, but the fourth breakpoint can compare an address and also data content. Additionally, the fouth breakpoint can be logically combined (AND/OR) with any of the other three breakpoints. – The Debug Event pin can be configured by the PC host to generate an output pulse for external triggering when a break condition is met. The pin can also be configured as an event input to the breakpoint logic, causing a break on the falling-edge of an external event signal. If not used, the Debug Event pin should be pulled up to VCC as described in the section, Debugging the 8032 MCU Module., page 201. – The duration of a pulse, generated when the Event pin configured as an output, is one MCU clock cycle. This is an active-low signal, so the first edge when an event occurs is high-to-low. – The clock to the Watchdog Timer, ADC, and I 2C interface are not stopped by a breakpoint halt. – The Watchdog Timer should be disabled while debugging with JTAG, else a reset will be generated upon a watchdog time-out.uPSD33xx 40/231 INTERRUPT SYSTEM The uPSD33xx has an 11-source, two priority level interrupt structure summarized in Table 16. Firmware may assign each interrupt source either high or low priority by writing to bits in the SFRs named, IP and IPA, shown in Table 16. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority interrupt is being serviced, it will be stopped and the new interrupt is serviced. When the new interrupt is finished, the lower priority interrupt that was stopped will be completed. If new interrupt requests are of the same priority level and are received simultaneously, an internal polling sequence determines which request is selected for service. Thus, within each of the two priority levels, there is a second priority structure determined by the polling sequence. Firmware may individually enable or disable interrupt sources by writing to bits in the SFRs named, IE and IEA, shown in Table 16., page 41. The SFR named IE contains a global disable bit (EA), which can be cleared to disable all 11 interrupts at once, as shown in Table 17., page 43. Figure 13., page 42 illustrates the interrupt priority, polling, and enabling process. Each interrupt source has at least one interrupt flag that indicates whether or not an interrupt is pending. These flags reside in bits of various SFRs shown in Table 16., page 41. All of the interrupt flags are latched into the interrupt control system at the beginning of each MCU machine cycle, and they are polled at the beginning of the following machine cycle. If polling determines one of the flags was set, the interrupt control system automatically generates an LCALL to the user’s Interrupt Service Routine (ISR) firmware stored in program memory at the appropriate vector address. The specific vector address for each of the interrupt sources are listed in Table 16., page 41. However, this LCALL jump may be blocked by any of the following conditions: – An interrupt of equal or higher priority is already in progress – The current machine cycle is not the final cycle in the execution of the instruction in progress – The current instruction involves a write to any of the SFRs: IE, IEA, IP, or IPA – The current instruction is an RETI Note: Interrupt flags are polled based on a sample taken in the previous MCU machine cycle. If an interrupt flag is active in one cycle but is denied serviced due to the conditions above, and then later it is not active when the conditions above are finally satisfied, the previously denied interrupt will not be serviced. This means that active interrupts are not remembered. Every poling cycle is new. Assuming all of the listed conditions are satisfied, the MCU executes the hardware generated LCALL to the appropriate ISR. This LCALL pushes the contents of the PC onto the stack (but it does not save the PSW) and loads the PC with the appropriate interrupt vector address. Program execution then jumps to the ISR at the vector address. Execution precedes in the ISR. It may be necessary for the ISR firmware to clear the pending interrupt flag for some interrupt sources, because not all interrupt flags are automatically cleared by hardware when the ISR is called, as shown in Table 16., page 41. If an interrupt flag is not cleared after servicing the interrupt, an unwanted interrupt will occur upon exiting the ISR. After the interrupt is serviced, the last instruction executed by the ISR is RETI. The RETI informs the MCU that the ISR is no longer in progress and the MCU pops the top two bytes from the stack and loads them into the PC. Execution of the interrupted program continues where it left off. Note: An ISR must end with a RETI instruction, not a RET. An RET will not inform the interrupt control system that the ISR is complete, leaving the MCU to think the ISR is still in progress, making future interrupts impossible.41/231 uPSD33xx Table 16. Interrupt Summary Interrupt Source Polling Priority Vector Addr Flag Bit Name (SFR.bit position) 1 = Intr Pending 0 = No Interrupt Flag Bit AutoCleared by Hardware? Enable Bit Name (SFR.bit position) 1 = Intr Enabled 0 = Intr Disabled Priority Bit Name (SFR.bit position) 1= High Priority 0 = Low Priority Reserved 0 (high) 0063h – – – – External Interrupt INT0 1 0003h IE0 (TCON.1) Edge - Yes Level - No EX0 (IE.0) PX0 (IP.0) Timer 0 Overflow 2 000Bh TF0 (TCON.5) Yes ET0 (IE.1) PT0 (IP.1) External Interrupt INT1 3 0013h IE1 (TCON.3 Edge - Yes Level - No EX1 (IE.2) PX1 (IP.2) Timer 1 Overflow 4 001Bh TF1 (TCON.7) Yes ET1 (IE.3) PT1 (IP.3) UART0 5 0023h RI (SCON0.0) TI (SCON0.1) No ES0 (IE.4) PS0 (IP.4) Timer 2 Overflow or TX2 Pin 6 002Bh TF2 (T2CON.7) EXF2 (T2CON.6) No ET2 (IE.5) PT2 (IP.5) SPI 7 0053h TEISF, RORISF, TISF, RISF (SPISTAT[3:0]) Yes ESPI (IEA.6) PSPI (IPA.6) Reserved 8 0033h – – – – I 2C 9 0043h INTR (S1STA.5) Yes EI2C (IEA.1) PI2C (IPA.1) ADC 10 003Bh AINTF (ACON.7) No EADC (IEA.7) PADC (IPA.7) PCA 11 005Bh OFVx, INTFx (PCASTA[0:7]) No EPCA (IEA.5) PPCA (IPA.5) UART1 12 (low) 004Bh RI (SCON1.0) TI (SCON1.1) No ES1 (IEA.4) PS1 (IPA.4)uPSD33xx 42/231 Figure 13. Enabling and Polling Interrupts Reserved Ext INT0 Ext INT1 Timer 0 UART0 Timer 1 SPI USB Timer 2 High LowInterrupt Polling Sequence Interrupt Sources IE/IEA IP/IPA Priority Global Enable ADC PCA I 2 C UART1 AI0784443/231 uPSD33xx Individual Interrupt Sources External Interrupts Int0 and Int1. External interrupt inputs on pins EXTINT0 and EXTINT1 (pins 3.2 and 3.3) are either edge-triggered or level-triggered, depending on bits IT0 and IT1 in the SFR named TCON. When an external interrupt is generated from an edge-triggered (falling-edge) source, the appropriate flag bit (IE0 or IE1) is automatically cleared by hardware upon entering the ISR. When an external interrupt is generated from a level-triggered (low-level) source, the appropriate flag bit (IE0 or IE1) is NOT automatically cleared by hardware. Timer 0 and 1 Overflow Interrupt. Timer 0 and Timer 1 interrupts are generated by the flag bits TF0 and TF1 when there is an overflow condition in the respective Timer/Counter register (except for Timer 0 in Mode 3). Timer 2 Overflow Interrupt. This interrupt is generated to the MCU by a logical OR of flag bits, TF2 and EXE2. The ISR must read the flag bits to determine the cause of the interrupt. – TF2 is set by an overflow of Timer 2. – EXE2 is generated by the falling edge of a signal on the external pin, T2X (pin P1.1). UART0 and UART1 Interrupt. Each of the UARTs have identical interrupt structure. For each UART, a single interrupt is generated to the MCU by the logical OR of the flag bits, RI (byte received) and TI (byte transmitted). The ISR must read flag bits in the SFR named SCON0 for UART0, or SCON1 for UART1 to determine the cause of the interrupt. SPI Interrupt. The SPI interrupt has four interrupt sources, which are logically ORed together when interrupting the MCU. The ISR must read the flag bits to determine the cause of the interrupt. A flag bit is set for: end of data transmit (TEISF); data receive overrun (RORISF); transmit buffer empty (TISF); or receive buffer full (RISF). I 2C Interrupt. The flag bit INTR is set by a variety of conditions occurring on the I2C interface: received own slave address (ADDR flag); received general call address (GC flag); received STOP condition (STOP flag); or successful transmission or reception of a data byte.The ISR must read the flag bits to determine the cause of the interrupt. ADC Interrupt. The flag bit AINTF is set when an A-to-D conversion has completed. PCA Interrupt. The PCA has eight interrupt sources, which are logically ORed together when interrupting the MCU.The ISR must read the flag bits to determine the cause of the interrupt. – Each of the six TCMs can generate a "match or capture" interrupt on flag bits OFV5..0 respectively. – Each of the two 16-bit counters can generate an overflow interrupt on flag bits INTF1 and INTF0 respectively. Tables 17 through Table 20., page 45 have detailed bit definitions of the interrupt system SFRs. Table 17. IE: Interrupt Enable Register (SFR A8h, reset value 00h) Note: 1. 1 = Enable Interrupt, 0 = Disable Interrupt Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EA – ET2 ES0 ET1 EX1 ET0 EX0 Details Bit Symbol R/W Function 7 EA R,W Global disable bit. 0 = All interrupts are disabled. 1 = Each interrupt source can be individually enabled or disabled by setting or clearing its enable bit. 6 – R,W Do not modify this bit. It is used by the JTAG debugger for instruction tracing. Always read the bit and write back the same bit value when writing this SFR. 5(1) ET2 R,W Enable Timer 2 Interrupt 4(1) ES0 R,W Enable UART0 Interrupt 3(1) ET1 R,W Enable Timer 1 Interrupt 2(1) EX1 R,W Enable External Interrupt INT1 1(1) ET0 R,W Enable Timer 0 Interrupt 0(1) EX0 R,W Enable External Interrupt INT0uPSD33xx 44/231 Table 18. IEA: Interrupt Enable Addition Register (SFR A7h, reset value 00h) Note: 1. 1 = Enable Interrupt, 0 = Disable Interrupt Table 19. IP: Interrupt Priority Register (SFR B8h, reset value 00h) Note: 1. 1 = Assigns high priority level, 0 = Assigns low priority level Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EADC ESPI EPCA ES1 – – EI2C – Details Bit Symbol R/W Function 7(1) EADC R,W Enable ADC Interrupt 6(1) ESPI R,W Enable SPI Interrupt 5(1) EPCA R,W Enable Programmable Counter Array Interrupt 4(1) ES1 R,W Enable UART1 Interrupt 3 – – Reserved, do not set to logic '1.' 2 – – Reserved, do not set to logic '1.' 1(1) EI2C R,W Enable I2C Interrupt 0 – – Reserved, do not set to logic '1.' Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – PT2 PS0 PT1 PX1 PT0 PX0 Details Bit Symbol R/W Function 7 – – Reserved 6 – – Reserved 5(1) PT2 R,W Timer 2 Interrupt priority level 4(1) PS0 R,W UART0 Interrupt priority level 3(1) PT1 R,W Timer 1 Interrupt priority level 2(1) PX1 R,W External Interrupt INT1 priority level 1(1) PT0 R,W Timer 0 Interrupt priority level 0(1) PX0 R,W External Interrupt INT0 priority level45/231 uPSD33xx Table 20. IPA: Interrupt Priority Addition register (SFR B7h, reset value 00h) Note: 1. 1 = Assigns high priority level, 0 = Assigns low priority level Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PADC PSPI PPCA PS1 – – PI2C – Details Bit Symbol R/W Function 7(1) PADC R,W ADC Interrupt priority level 6(1) PSPI R,W SPI Interrupt priority level 5(1) PPCA R,W PCA Interrupt level 4(1) PS1 R,W UART1 Interrupt priority level 3 – – Reserved 2 – – Reserved 1(1) PI2C R,W I 2C Interrupt priority level 0 – – ReserveduPSD33xx 46/231 MCU CLOCK GENERATION Internal system clocks generated by the clock generation unit are derived from the signal, XTAL1, shown in Figure 14. XTAL1 has a frequency fOSC, which comes directly from the external crystal or oscillator device. The SFR named CCON0 (Table 21., page 47) controls the clock generation unit. There are two clock signals produced by the clock generation unit: ■ MCU_CLK ■ PERIPH_CLK MCU_CLK This clock drives the 8032 MCU core and the Watchdog Timer (WDT). The frequency of MCU_CLK is equal to fOSC by default, but it can be divided by as much as 2048, shown in Figure 14. The bits CPUPS[2:0] select one of eight different divisors, ranging from 2 to 2048. The new frequency is available immediately after the CPUPS[2:0] bits are written. The final frequency of MCU_CLK is fMCU. MCU_CLK is blocked by either bit, PD or IDL, in the SFR named PCON during MCU Power-down Mode or Idle Mode respectively. MCU_CLK clock can be further divided as required for use in the WDT. See details of the WDT in SUPERVISORY FUNCTIONS, page 65. PERIPH_CLK This clock drives all the uPSD33xx peripherals except the WDT. The Frequency of PERIPH_CLK is always fOSC. Each of the peripherals can independently divide PERIPH_CLK to scale it appropriately for use. PERIPH_CLK runs at all times except when blocked by the PD bit in the SFR named PCON during MCU Power-down Mode. JTAG Interface Clock. The JTAG interface for ISP and for Debugging uses the externally supplied JTAG clock, coming in on pin TCK. This means the JTAG ISP interface is always available, and the JTAG Debug interface is available when enabled, even during MCU Idle mode and Powerdown Mode. However, since the MCU participates in the JTAG debug process, and MCU_CLK is halted during Idle and Power-down Modes, the majority of debug functions are not available during these low power modes. But the JTAG debug interface is capable of executing a reset command while in these low power modes, which will exit back to normal operating mode where all debug commands are available again. The CCON0 SFR contains a bit, DBGCE, which enables the breakpoint comparators inside the JTAG Debug Unit when set. DBGCE is set by default after reset, and firmware may clear this bit at run-time. Disabling these comparators will reduce current consumption on the MCU Module, and it’s recommended to do so if the Debug Unit will not be used (such as in the production version of an end-product). Figure 14. Clock Generation Logic XTAL1 /2 XTAL1 /4 XTAL1 /2048 Q Q Q M U X XTAL1 (default) XTAL1 /8 XTAL1 /16 Q Q XTAL1 /32 XTAL1 /1024 Q Q 0 1 2 3 4 5 6 7 XTAL1 (fOSC) PCON[1]: PD, Power-Down Mode PCON[2:0]: CPUPS[2:0], Clock Pre-Scaler Select PCON[0]: IDL, Idle Mode Clock Divider MCU_CLK (fMCU) (to: 8032, WDT) PERIPH_CLK (fOSC) (to: TIMER0/1/2, UART0/1, PCA0/1, SPI, I2C, ADC) 3 AI0919747/231 uPSD33xx Table 21. CCON0: Clock Control Register (SFR F9h, reset value 10h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – DBGCE CPUAR CPUPS[2:0] Details Bit Symbol R/W Definition 7 – – Reserved 6 – – Reserved 5 – – Reserved 4 DBGCE R,W Debug Unit Breakpoint Comparator Enable 0 = JTAG Debug Unit comparators are disabled 1 = JTAG Debug Unit comparators are enabled (Default condition after reset) 3 CPUAR R,W Automatic MCU Clock Recovery 0 = There is no change of CPUPS[2:0] when an interrupt occurs. 1 = Contents of CPUPS[2:0] automatically become 000b whenever any interrupt occurs. 2:0 CPUPS R,W MCUCLK Pre-Scaler 000b: fMCU = fOSC (Default after reset) 001b: fMCU = fOSC/2 010b: fMCU = fOSC/4 011b: fMCU = fOSC/8 100b: fMCU = fOSC/16 101b: fMCU = fOSC/32 110b: fMCU = fOSC/1024 111b: fMCU = fOSC/2048uPSD33xx 48/231 POWER SAVING MODES The uPSD33xx is a combination of two die, or modules, each module having it’s own current consumption characteristics. This section describes reduced power modes for the MCU Module. See the section, Power Management, page 137 for reduced power modes of the PSD Module. Total current consumption for the combined modules is determined in the DC specifications at the end of this document. The MCU Module has three software-selectable modes of reduced power operation. ■ Idle Mode ■ Power-down Mode ■ Reduced Frequency Mode Idle Mode Idle Mode will halt the 8032 MCU core while leaving the MCU peripherals active (Idle Mode blocks MCU_CLK only). For lowest current consumption in this mode, it is recommended to disable all unused peripherals, before entering Idle mode (such as the ADC and the Debug Unit breakpoint comparators). The following functions remain fully active during Idle Mode (except if disabled by SFR settings). ■ External Interrupts INT0 and INT1 ■ Timer 0, Timer 1 and Timer 2 ■ Supervisor reset from: LVD, JTAG Debug, External RESET_IN_, but not the WTD ■ ADC ■ I 2C Interface ■ UART0 and UART1 Interfaces ■ SPI Interface ■ Programmable Counter Array An interrupt generated by any of these peripherals, or a reset generated from the supervisor, will cause Idle Mode to exit and the 8032 MCU will resume normal operation. The output state on I/O pins of MCU ports 1, 3, and 4 remain unchanged during Idle Mode. To enter Idle Mode, the 8032 MCU executes an instruction to set the IDL bit in the SFR named PCON, shown in Table 24., page 50. This is the last instruction executed in normal operating mode before Idle Mode is activated. Once in Idle Mode, the MCU status is entirely preserved, and there are no changes to: SP, PSW, PC, ACC, SFRs, DATA, IDATA, or XDATA. The following are factors related to Idle Mode exit: – Activation of any enabled interrupt will cause the IDL bit to be cleared by hardware, terminating Idle Mode. The interrupt is serviced, and following the Return from Interrupt instruction (RETI), the next instruction to be executed will be the one which follows the instruction that set the IDL bit in the PCON SFR. – After a reset from the supervisor, the IDL bit is cleared, Idle Mode is terminated, and the MCU restarts after three MCU machine cycles. Power-down Mode Power-down Mode will halt the 8032 core and all MCU peripherals (Power-down Mode blocks MCU_CLK and PERIPH_CLK). This is the lowest power state for the MCU Module. When the PSD Module is also placed in Power-down mode, the lowest total current consumption for the combined die is achieved for the uPSD33xx. See Power Management, page 137 in the PSD Module section for details on how to also place the PSD Module in Power-down mode. The sequence of 8032 instructions is important when placing both modules into Power-down Mode. The instruction that sets the PD Bit in the SFR named PCON (Table 24., page 50) is the last instruction executed prior to the MCU Module going into Power-down Mode. Once in Power-down Mode, the on-chip oscillator circuitry and all clocks are stopped. The SFRs, DATA, IDATA, and XDATA are preserved. Power-down Mode is terminated only by a reset from the supervisor, originating from the RESET_IN_ pin, the Low-Voltage Detect circuit (LVD), or a JTAG Debug reset command. Since the clock to the WTD is not active during Powerdown mode, it is not possible for the supervisor to generate a WDT reset. Table 22., page 49 summarizes the status of I/O pins and peripherals during Idle and Power-down Modes on the MCU Module. Table 23., page 49 shows the state of 8032 MCU address, data, and control signals during these modes. Reduced Frequency Mode The 8032 MCU consumes less current when operating at a lower clock frequency. The MCU can reduce it’s own clock frequency at run-time by writing to three bits, CPUPS[2:0], in the SFR named CCON0 described in Table 21., page 47. These bits effectively divide the clock frequency (fOSC) coming in from the external crystal or oscillator device. The clock division range is from 1/2 to 1/2048, and the resulting frequency is fMCU. This MCU clock division does not affect any of the peripherals, except for the WTD. The clock driving the WTD is the same clock driving the 8032 MCU core as shown in Figure 14., page 46.49/231 uPSD33xx MCU firmware may reduce the MCU clock frequency at run-time to consume less current when performing tasks that are not time critical, and then restore full clock frequency as required to perform urgent tasks. Returning to full clock frequency is done automatically upon an MCU interrupt, if the CPUAR Bit in the SFR named CCON0 is set (the interrupt will force CPUPS[2:0] = 000). This is an excellent way to conserve power using a low frequency clock until an event occurs that requires full performance. See Table 21., page 47 for details on CPUAR. See the DC Specifications at the end of this document to estimate current consumption based on the MCU clock frequency. Note: Some of the bits in the PCON SFR shown in Table 24., page 50 are not related to power control. Table 22. MCU Module Port and Peripheral Status during Reduced Power Modes Note: 1. The Watchdog Timer is not active during Idle Mode. Other supervisor functions are active: LVD, external reset, JTAG Debug reset Table 23. State of 8032 MCU Bus Signals during Power-down and Idle Modes Mode Ports 1, 3, 4 PCA SPI I 2C ADC SUPERVISOR UART0, UART1 TIMER 0,1,2 EXT INT0, 1 Idle Maintain Data Active Active Active Active Active(1) Active Active Active Power-down Maintain Data Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Mode ALE PSEN_ RD_ WR_ AD0-7 A8-15 Idle 0 1 1 1 FFh FFh Power-down 0 1 1 1 FFh FFhuPSD33xx 50/231 Table 24. PCON: Power Control Register (SFR 87h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMOD0 SMOD1 – POR RCLK1 TCLK1 PD IDL Details Bit Symbol R/W Function 7 SMOD0 R,W Baud Rate Double Bit (UART0) 0 = No Doubling 1 = Doubling (See UART Baud Rates, page 84 for details.) 6 SMOD1 R,W Baud Rate Double Bit for 2nd UART (UART1) 0 = No Doubling 1 = Doubling (See UART Baud Rates, page 84 for details.) 5 – – Reserved 4 POR R,W Only a power-on reset sets this bit (cold reset). Warm reset will not set this bit. '0,' Cleared to zero with firmware '1,' Is set only by a power-on reset generated by Supervisory circuit (see Power-up Reset, page 66 for details). 3 RCLK1 R,W Received Clock Flag (UART1) (See Table 41., page 75 for flag description.) 2 TCLK1 R,W Transmit Clock Flag (UART1) (See Table 41., page 75 for flag description) 1 PD R,W Activate Power-down Mode 0 = Not in Power-down Mode 1 = Enter Power-down Mode 0 IDL R,W Activate Idle Mode 0 = Not in Idle Mode 1 = Enter Idle Mode51/231 uPSD33xx OSCILLATOR AND EXTERNAL COMPONENTS The oscillator circuit of uPSD33xx devices is a single stage, inverting amplifier in a Pierce oscillator configuration. The internal circuitry between pins XTAL1 and XTAL2 is basically an inverter biased to the transfer point. Either an external quartz crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuit. Both are operated in parallel resonance. Ceramic resonators are lower cost, but typically have a wider frequency tolerance than quartz crystals. Alternatively, an external clock source from an oscillator or other active device may drive the uPSD33xx oscillator circuit input directly, instead of using a crystal or resonator. The minimum frequency of the quartz crystal, ceramic resonator, or external clock source is 1MHz if the I2C interface is not used. The minimum is 8MHz if I2C is used. The maximum is 40MHz in all cases. This frequency is fOSC, which can be divided internally as described in MCU CLOCK GENERATION, page 46. The pin XTAL1 is the high gain amplifier input, and XTAL2 is the output. To drive the uPSD33xx device externally from an oscillator or other active device, XTAL1 is driven and XTAL2 is left opencircuit. This external source should drive a logic low at the voltage level of 0.3 VCC or below, and logic high at 0.7V VCC or above, up to 5.5V VCC. The XTAL1 input is 5V tolerant. Most of the quartz crystals in the range of 25MHz to 40MHz operate in the third overtone frequency mode. An external LC tank circuit at the XTAL2 output of the oscillator circuit is needed to achieve the third overtone frequency, as shown in Figure 15., page 52. Without this LC circuit, the crystal will oscillate at a fundamental frequency mode that is about 1/3 of the desired overtone frequency. Note: In Figure 15., page 52 crystals which are specified to operate in fundamental mode (not overtone mode) do not need the LC circuit components. Since quartz crystals and ceramic resonators have their own characteristics based on their manufacturer, it is wise to also consult the manufacturer’s recommended values for external components.uPSD33xx 52/231 Figure 15. Oscillator and Clock Connections Crystal or Resonator Usage Direct Drive XTAL1 (in) XTAL1 (in) XTAL2 (out) XTAL2 (out) C1 C2 XTAL (fOSC) L1 C3 External Ocsillator or No Connect Active Clock Source XTAL (fOSC) C1 = C2 C3 L1 Ceramic Resonator 40 - 50pF None Crystal, fundamental mode (3-40MHz) 15-33pF None None None Crystal, overtone mode (25-40MHz) 20pF 10nF 2.2µH AI0919853/231 uPSD33xx I/O PORTS OF MCU MODULE The MCU Module has three 8-bit I/O ports: Port 1, Port 3, and Port 4. The PSD Module has four other I/O ports: Port A, B, C, and D. This section describes only the I/O ports on the MCU Module. I/O ports will function as bi-directional General Purpose I/O (GPIO), but the port pins can have alternate functions assigned at run-time by writing to specific SFRs. The default operating mode (during and after reset) for all three ports is GPIO input mode. Port pins that have no external connection will not float because each pin has an internal weak pull-up (~150K ohms) to VCC. I/O ports 3 and 4 are 5V tolerant, meaning they can be driven/pulled externally up to 5.5V without damage. The pins on Port 4 have a higher current capability than the pins on Ports 1 and 3. Three additional MCU ports (only on 80-pin uPSD33xx devices) are dedicated to bring out the 8032 MCU address, data, and control signals to external pins. One port, named MCUA[11:8], contains four MCU address signal outputs. Another port, named MCUAD[7:0], has eight multiplexed address/data bidirectional signals. The third port has MCU bus control outputs: read, write, program fetch, and address latch. These ports are typically used to connect external parallel peripherals and memory devices, but they may NOT be used as GPIO. Notice that only four of the eight upper address signals come out to pins on the port MCUA[11:8]. If additional high-order address signals are required on external pins (MCU addresses A[15:12]), then these address signals can be brought out as needed to PLD output pins or to the Address Out mode pins on PSD Module ports. See PSD Module section, “Latched Address Output Mode, page 177 for details. Figure 16., page 55 represents the flexibility of pin function routing controlled by the SFRs. Each of the 24 pins on three ports, P1, P3, and P4, may be individually routed on a pin-by-pin basis to a desired function. MCU Port Operating Modes MCU port pins can operate as GPIO or as alternate functions (see Figure 17., page 56 through Figure 19., page 57). Depending on the selected pin function, a particular pin operating mode will automatically be used: ■ GPIO - Quasi-bidirectional mode ■ UART0, UART1 - Quasi-bidirectional mode ■ SPI - Quasi-bidirectional mode ■ I2C - Open drain mode ■ ADC - Analog input mode ■ PCA output - Push-Pull mode ■ PCA input - Input only (Quasi-bidirectional) ■ Timer 0,1,2 - Input only (Quasi-bidirectional) GPIO Function. Ports in GPIO mode operate as quasi-bidirectional pins, consistent with standard 8051 architecture. GPIO pins are individually controlled by three SFRs: ■ SFR, P1 (Table 25., page 57) ■ SFR, P3 (Table 26., page 58) ■ SFR, P4 (Table 27., page 58) These SFRs can be accessed using the Bit Addressing mode, an efficient way to control individual port pins. GPIO Output. Simply stated, when a logic '0' is written to a bit in any of these port SFRs while in GPIO mode, the corresponding port pin will enable a low-side driver, which pulls the pin to ground, and at the same time releases the high-side driver and pull-ups, resulting in a logic'0' output. When a logic '1' is written to the SFR, the low-side driver is released, the high-side driver is enabled for just one MCU_CLK period to rapidly make the 0-to1 transition on the pin, while weak active pull-ups (total ~150K ohms) to VCC are enabled. This structure is consistent with standard 8051 architecture. The high side driver is momentarily enabled only for 0-to-1 transitions, which is implemented with the delay function at the latch output as pictured in Figure 17., page 56 through Figure 19., page 57. After the high-side driver is disabled, the two weak pull-ups remain enabled resulting in a logic '1' output at the pin, sourcing IOH uA to an external device. Optionally, an external pull-up resistor can be added if additional source current is needed while outputting a logic '1.'uPSD33xx 54/231 GPIO Input. To use a GPIO port pin as an input, the low-side driver to ground must be disabled, or else the true logic level being driven on the pin by an external device will be masked (always reads logic '0'). So to make a port pin “input ready”, the corresponding bit in the SFR must have been set to a logic '1' prior to reading that SFR bit as an input. A reset condition forces SFRs P1, P3, and P4 to FFh, thus all three ports are input ready after reset. When a pin is used as an input, the stronger pullup “A” maintains a solid logic '1' until an external device drives the input pin low. At this time, pull-up “A” is automatically disabled, and only pull-up “B” will source the external device IIH uA, consistent with standard 8051 architecture. GPIO Bi-Directional. It is possible to operate individual port pins in bi-directional mode. For an output, firmware would simply write the corresponding SFR bit to logic '1' or '0' as needed. But before using the pin as an input, firmware must first ensure that a logic '1' was the last value written to the corresponding SFR bit prior to reading that SFR bit as an input. GPIO Current Capability. A GPIO pin on Port 4 can sink twice as much current than a pin on either Port 1 or Port 3 when the low-side driver is outputting a logic '0' (IOL). See the DC specifications at the end of this document for full details. Reading Port Pin vs. Reading Port Latch. When firmware reads the GPIO ports, sometimes the actual port pin is sampled in hardware, and sometimes the port SFR latch is read and not the actual pin, depending on the type of MCU instruction used. These two data paths are shown in Figure 17., page 56 through Figure 19., page 57. SFR latches are read (and not the pins) only when the read is part of a read-modify-write instruction and the write destination is a bit or bits in a port SFR. These instructions are: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ, MOV, CLR, and SETB. All other types of reads to port SFRs will read the actual pin logic level and not the port latch. This is consistent with 8051 architecture.55/231 uPSD33xx Figure 16. MCU Module Port Pin Function Routing 8 P3 P1 P4 M C U A D M C U A GPIO (8) UART0 (2) TIMER0/1 (4) I 2C (2) GPIO (8) GPIO (8) TIMER2 (2) UART1 (2) SPI (4) ADC (8) PCA (8) 8032 MCU CORE Low Addr & Data[7:0] 8 Available on PSD Hi Address [15:12] Hi Address [11:8] 4 Module Pins MCU Module 4 On 80-pin Devices Only Ports C N T L RD, WR, PSEN, ALE 4 SFR 8 8 SFR SFR SFR SFR SFR AI09199uPSD33xx 56/231 Figure 17. MCU I/O Cell Block Diagram for Port 1 Figure 18. MCU I/O Cell Block Diagram for Port 3 P1.X Pin Analog_Alt_Func_En Analog_Pin_In D Q PRE SFR P1.X Latch 8032 Data Bus Bit GPIO P1.X SFR Write Latch MCU_Reset P1.X SFR Read Latch (for R-M-W instructions) P1.X SFR Read Pin Select_Alternate_Func Digital_Pin_Data_In IN 1 IN 0 MUX Y VCC VCC VCC SEL WEAK PULL-UP, B STONGER PULL-UP, A LOW SIDE HIGH SIDE DELAY, 1 MCU_CLK DELAY, 1 MCU_CLK Q Digital_Alt_Func_Data_Out AI09600 P3.X Pin Digital_Pin_Data_In D Q PRE SFR P3.X Latch 8032 Data Bus Bit GPIO P3.X SFR Write Latch MCU_Reset P3.X SFR Read Latch (for R-M-W instructions) P3.X SFR Read Pin Select_Alternate_Func Disables High-Side Driver IN 1 IN 0 MUX Y VCC VCC VCC SEL Enable_I2C WEAK PULL-UP, B STONGER PULL-UP, A LOW SIDE HIGH SIDE DELAY, 1 MCU_CLK DELAY, 1 MCU_CLK Q Digital_Alt_Func_Data_Out AI0960157/231 uPSD33xx Figure 19. MCU I/O Cell Block Diagram for Port 4 Table 25. P1: I/O Port 1 Register (SFR 90h, reset value FFh) Note: 1. Write '1' or '0' for pin output. Read for pin input, but prior to READ, this bit must have been set to '1' by firmware or by a reset event. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Details Bit Symbol R/W Function(1) 7 P1.7 R,W Port pin 1.7 6 P1.6 R,W Port pin 1.6 5 P1.5 R,W Port pin 1.5 4 P1.4 R,W Port pin 1.4 3 P1.3 R,W Port pin 1.3 2 P1.2 R,W Port pin 1.2 1 P1.1 R,W Port pin 1.1 0 P1.0 R,W Port pin 1.0 P4.X Pin Digital_Pin_Data_In D Q PRE SFR P4.X Latch 8032 Data Bus Bit GPIO P4.X SFR Write Latch MCU_Reset P4.X SFR Read Latch (for R-M-W instructions) P4.X SFR Read Pin Select_Alternate_Func For PCA Alternate Function IN 1 IN 0 MUX Y VCC VCC VCC SEL Enable_Push_Pull WEAK PULL-UP, B STONGER PULL-UP, A LOW SIDE HIGH SIDE DELAY, 1 MCU_CLK DELAY, 1 MCU_CLK Q Digital_Alt_Func_Data_Out AI09602uPSD33xx 58/231 Table 26. P3: I/O Port 3 Register (SFR B0h, reset value FFh) Note: 1. Write '1' or '0' for pin output. Read for pin input, but prior to READ, this bit must have been set to '1' by firmware or by a reset event. Table 27. P4: I/O Port 4 Register (SFR C0h, reset value FFh) Note: 1. Write '1' or '0' for pin output. Read for pin input, but prior to READ, this bit must have been set to '1' by firmware or by a reset event. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 Details Bit Symbol R/W Function(1) 7 P3.7 R,W Port pin 3.7 6 P3.6 R,W Port pin 3.6 5 P3.5 R,W Port pin 3.5 4 P3.4 R,W Port pin 3.4 3 P3.3 R,W Port pin 3.3 2 P3.2 R,W Port pin 3.2 1 P3.1 R,W Port pin 3.1 0 P3.0 R,W Port pin 3.0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 Details Bit Symbol R/W Function(1) 7 P4.7 R,W Port pin 4.7 6 P4.6 R,W Port pin 4.6 5 P4.5 R,W Port pin 4.5 4 P4.4 R,W Port pin 4.4 3 P4.3 R,W Port pin 4.3 2 P4.2 R,W Port pin 4.2 1 P4.1 R,W Port pin 4.1 0 P4.0 R,W Port pin 4.059/231 uPSD33xx Alternate Functions. There are five SFRs used to control the mapping of alternate functions onto MCU port pins, and these SFRs are depicted as switches in Figure 16., page 55. ■ Port 3 uses the SFR, P3SFS (Table 28., page 60). ■ Port 1 uses SFRs, P1SFS0 (Table 29., page 60) and P1SFS1 (Table 30., page 60). ■ Port 4 uses SFRs, P4SFS0 (Table 32., page 61) and P4SFS1 (Table 33., page 61). Since these SFRs are cleared by a reset, then by default all port pins function as GPIO (not the alternate function) until firmware initializes these SFRs. Each pin on each of the three ports can be independently assigned a different function on a pinby-pin basis. The peripheral functions Timer 2, UART1, and I2C may be split independently between Port 1 and Port 4 for additional flexibility by giving a wider choice of peripheral usage on a limited number of device pins. When the selected alternate function is UART0, UART1, or SPI, then the related pins are in quasibidirectional mode, including the use of the highside driver for rapid 0-to-1 output transitions. The high-side driver is enabled for just one MCU_CLK period on 0-to-1 transitions by the delay function at the “digital_alt_func_data_out” signal pictured in Figure 17., page 56 through Figure 19., page 57. If the alternate function is Timer 0, Timer 1, Timer 2, or PCA input, then the related pins are in quasibidirectional mode, but input only. If the alternate function is ADC, then for each pin the pull-ups, the high-side driver, and the low-side driver are disabled. The analog input is routed directly to the ADC unit. Only Port 1 supports analog functions (Figure 17., page 56). Port 1 is not 5V tolerant. If the alternate function is I2C, the related pins will be in open drain mode, which is just like quasi-bidirectional mode but the high-side driver is not enabled for one cycle when outputting a 0-to-1 transition. Only the low-side driver and the internal weak pull-ups are used. Only Port 3 supports open-drain mode (Figure 18., page 56). I2C requires the use of an external pull-up resistor on each bus signal, typically 4.7KΩ to VCC. If the alternate function is PCA output, then the related pins are in push-pull mode, meaning the pins are actively driven and held to logic '1' by the highside driver, or actively driven and held to logic '0' by the low-side driver. Only Port 4 supports pushpull mode (Figure 19., page 57). Port 4 push-pull pins can source IOH current when driving logic '1,' and sink IOL current when driving logic '0.' This current is significantly more than the capability of pins on Port 1 or Port 3 (see Table 129., page 207). For example, to assign these port functions: ■ Port 1: UART1, ADC[1:0], P1[7:4] are GPIO ■ Port 3: UART0, I2C, P3[5:2] are GPIO ■ Port 4: TCM0, SPI, P4[3:1] are GPIO The following values need to be written to the SFRs: P1SFS0 = 00001111b, or 0Fh P1SFS1 = 00000011b , or 03h P3SFS = 11000011b, or C3h P4SFS0 = 11110001b, or F1h P4SFS1 = 11110000b, or F0huPSD33xx 60/231 Table 28. P3SFS: Port 3 Special Function Select Register (SFR 91h, reset value 00h) Table 29. P1SFS0: Port 1 Special Function Select 0 Register (SFR 8Eh, reset value 00h) Table 30. P1SFS1: Port 1 Special Function Select 1 Register (SFR 8Fh, reset value 00h) Table 31. P1SFS0 and P1SFS1 Details Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3SFS7 P3SFS6 P3SFS5 P3SFS4 P3SFS3 P3SFS2 P3SFS1 P3SFS0 Details Port 3 Pin R/W Default Port Function Alternate Port Function P3SFS[i] - 0; Port 3 Pin, i = 0..7 P3SFS[i] - 1; Port 3 Pin, i = 0..7 0 R,W GPIO UART0 Receive, RXD0 1 R,W GPIO UART0 Transmit, TXD0 2 R,W GPIO Ext Intr 0/Timer 0 Gate, EXT0INT/TG0 3 R,W GPIO Ext Intr 1/Timer 1 Gate, EXT1INT/TG1 4 R,W GPIO Counter 0 Input, C0 5 R,W GPIO Counter 0 Input, C1 6 R,W GPIO I 2C Data, I2CSDA 7 R,W GPIO I 2C Clock, I2CCL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1SF07 P1SF06 P1SF05 P1SF04 P1SF03 P1SF02 P1SF01 P1SF00 Details Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1SF17 P1SF16 P1SF15 P1SF14 P1SF13 P1SF12 P1SF11 P1SF10 Port 1 Pin R/W Default Port Function Alternate 1 Port Function Alternate 2 Port Function P1SFS0[i] = 0 P1SFS1[i] = x P1SFS0[i] = 1 P1SFS1[i] = 0 P1SFS0[i] = 1 P1SFS1[i] = 1 Port 1 Pin, i = 0.. 7 Port 1 Pin, i = 0.. 7 Port 1 Pin, i = 0.. 7 0 R,W GPIO Timer 2 Count Input, T2 ADC Chn 0 Input, ADC0 1 R,W GPIO Timer 2 Trigger Input, TX2 ADC Chn 1 Input, ADC1 2 R,W GPIO UART1 Receive, RXD1 ADC Chn 2 Input, ADC2 3 R,W GPIO UART1 Transmit, TXD1 ADC Chn 3 Input, ADC3 4 R,W GPIO SPI Clock, SPICLK ADC Chn 4 Input, ADC4 5 R,W GPIO SPI Receive, SPIRXD ADC Chn 5 Input, ADC5 6 R,W GPIO SPI Transmit, SPITXD ADC Chn 6 Input, ADC6 7 R,W GPIO SPI Select, SPISEL_ ADC Chn 7 Input, ADC761/231 uPSD33xx Table 32. P4SFS0: Port 4 Special Function Select 0 Register (SFR 92h, reset value 00h) Table 33. P4SFS1: Port 4 Special Function Select 1 Register (SFR 93h, reset value 00h) Table 34. P4SFS0 and P4SFS1 Details Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4SF07 P4SF06 P4SF05 P4SF04 P4SF03 P4SF02 P4SF01 P4SF00 Details Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4SF17 P4SF16 P4SF15 P4SF14 P4SF13 P4SF12 P4SF11 P4SF10 Port 4 Pin R/W Default Port Function Alternate 1 Port Function Alternate 2 Port Function P4SFS0[i] = 0 P4SFS1[i] = x P4SFS0[i] = 1 P4SFS1[i] = 0 P4SFS0[i] = 1 P4SFS1[i] = 1 Port 4 Pin, i = 0.. 7 Port 4 Pin, i = 0.. 7 Port 4 Pin, i = 0.. 7 0 R,W GPIO PCA0 Module 0, TCM0 Timer 2 Count Input, T2 1 R,W GPIO PCA0 Module 1, TCM1 Timer 2 Trigger Input, TX2 2 R,W GPIO PCA0 Module 2, TCM2 UART1 Receive, RXD1 3 R,W GPIO PCA0 Ext Clock, PCACLK0 UART1 Transmit, TXD1 4 R,W GPIO PCA1 Module 3, TCM3 SPI Clock, SPICLK 5 R,W GPIO PCA1 Module 4, TCM4 SPI Receive, SPIRXD 6 R,W GPIO PCA1 Module 5, TCM5 SPI Transmit, SPITXD 7 R,W GPIO PCA1 Ext Clock, PCACLK1 SPI Select, SPISEL_uPSD33xx 62/231 MCU BUS INTERFACE The MCU Module has a programmable bus interface. It is based on a standard 8032 bus, with eight data signals multiplexed with eight low-order address signals (AD[7:0]). It also has eight high-order non-multiplexed address signals (A[15:8]). Time multiplexing is controlled by the address latch signal, ALE. This bus connects the MCU Module to the PSD Module, and also connects to external pins only on 80-pin devices. See the AC specifications section at the end of this document for external bus timing on 80-pin devices. Four types of data transfers are supported, each transfer is to/from a memory location external to the MCU Module: – Code Fetch cycle using the PSEN signal: fetch a code byte for execution – Code Read cycle using PSEN: read a code byte using the MOVC (Move Constant) instruction – XDATA Read cycle using the RD signal: read a data byte using the MOVX (Move eXternal) instruction – XDATA Write cycle using the WR signal: write a data byte using the MOVX instruction The number of MCU_CLK periods for these transfer types can be specified at runtime by firmware writing to the SFR register named BUSCON (Table 35., page 63). Here, the number of MCU_CLK clock pulses per bus cycle are specified to maximize performance. Important: By default, the BUSCON Register is loaded with long bus cycle times (6 MCU_CLK periods) after a reset condition. It is important that the post-reset initialization firmware sets the bus cycle times appropriately to get the most performance, according to Table 36., page 64. Keep in mind that the PSD Module has a faster Turbo Mode (default) and a slower but less power consuming Non-Turbo Mode. The bus cycle times must be programmed in BUSCON to optimize for each mode as shown in Table 36., page 64. See PLD NonTurbo Mode, page 192 for more details. Bus Read Cycles (PSEN or RD) When the PSEN signal is used to fetch a byte of code, the byte is read from the PSD Module or external device and it enters the MCU Pre-Fetch Queue (PFQ). When PSEN is used during a MOVC instruction, or when the RD signal is used to read a byte of data, the byte is routed directly to the MCU, bypassing the PFQ. Bits in the BUSCON Register determine the number of MCU_CLK periods per bus cycle for each of these kinds of transfers to all address ranges. It is not possible to specify in the BUSCON Register a different number of MCU_CLK periods for various address ranges. For example, the user cannot specify 4 MCU_CLK periods for RD read cycles to one address range on the PSD Module, and 5 MCU_CLK periods for RD read cycles to a different address range on an external device. However, the user can specify one number of clock periods for PSEN read cycles and a different number of clock periods for RD read cycles. Note 1: A PSEN bus cycle in progress may be aborted before completion if the PFQ and Branch Cache (BC) determines the current code fetch cycle is not needed. Note 2: Whenever the same number of MCU_CLK periods is specified in BUSCON for both PSEN and RD cycles, the bus cycle timing is typically identical for each of these types of bus cycles. In this case, the only time PSEN read cycles are longer than RD read cycles is when the PFQ issues a stall while reloading. PFQ stalls do not affect RD read cycles. By comparison, in many traditional 8051 architectures, RD bus cycles are always longer than PSEN bus cycles. Bus Write Cycles (WR) When the WR signal is used, a byte of data is written directly to the PSD Module or external device, no PFQ or caching is involved. Bits in the BUSCON Register determine the number of MCU_CLK periods for bus write cycles to all addresses. It is not possible to specify in BUSCON a different number of MCU_CLK periods for writes to various address ranges. Controlling the PFQ and BC The BUSCON Register allows firmware to enable and disable the PFQ and BC at run-time. Sometimes it may be desired to disable the PFQ and BC to ensure deterministic execution. The dynamic action of the PFQ and BC may cause varying program execution times depending on the events that happen prior to a particular section of code of interest. For this reason, it is not recommended to implement timing loops in firmware, but instead use one of the many hardware timers in the uPSD33xx. By default, the PFQ and BC are enabled after a reset condition. Important: Disabling the PFQ or BC will seriously reduce MCU performance.63/231 uPSD33xx Table 35. BUSCON: Bus Control Register (SFR 9Dh, reset value EBh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EPFQ EBC WRW[1:0] RDW[1:0] CW[1:0] Details Bit Symbol R/W Definition 7 EPFQ R,W Enable Pre-Fetch Queue 0 = PFQ is disabled 1 = PFQ is enabled (default) 6 EBC R,W Enable Branch Cache 0 = BC is disabled 1 = BC is enabled (default) 5:4 WRW[1:0] R,W WR Wait, number of MCU_CLK periods for WR write bus cycle during any MOVX instruction 00b: 4 clock periods 01b: 5 clock periods 10b: 6 clock periods (default) 11b: 7 clock periods 3:2 RDW[1:0] R,W RD Wait, number of MCU_CLK periods for RD read bus cycle during any MOVX instruction 00b: 4 clock periods 01b: 5 clock periods 10b: 6 clock periods (default) 11b: 7 clock periods 1:0 CW[1:0] R,W Code Wait, number of MCU_CLK periods for PSEN read bus cycle during any code byte fetch or during any MOVC code byte read instruction. Periods will increase with PFQ stall 00b: 3 clock periods - exception, for MOVC instructions this setting results 4 clock periods 01b: 4 clock periods 10b: 5 clock periods 11b: 6 clock periods (default)uPSD33xx 64/231 Table 36. Number of MCU_CLK Periods Required to Optimize Bus Transfer Rate Note: 1. VDD of the PSD Module 2. “Turbo mode PSD” means that the PSD Module is in the faster, Turbo mode (default condition). A PSD Module in Non-Turbo mode is slower, but consumes less current. See PSD Module section, titled “PLD Non-Turbo Mode” for details. MCU Clock Frequency, MCU_CLK (fMCU) CW[1:0] Clk Periods RDW[1:0] Clk Periods WRW[1:0] Clk Periods 3.3V(1) 5V(1) 3.3V(1) 5V(1) 3.3V(1) 5V(1) 40MHz, Turbo mode PSD(2) 545454 40MHz, Non-Turbo mode PSD 6 5 6 5 6 5 36MHz, Turbo mode PSD 545454 36MHz, Non-Turbo mode PSD 6 4 6 4 6 4 32MHz, Turbo mode PSD 545454 32MHz, Non-Turbo mode PSD 5 4 5 4 5 4 28MHz, Turbo mode PSD 434444 28MHz, Non-Turbo mode PSD 5 4 5 4 5 4 24MHz, Turbo mode PSD 434444 24MHz, Non-Turbo mode PSD 4 3 4 4 4 4 20MHz and below, Turbo mode PSD 334444 20MHz and below, Non-Turbo mode PSD 3 3 4 4 4 465/231 uPSD33xx SUPERVISORY FUNCTIONS Supervisory circuitry on the MCU Module will issue an internal reset signal to the MCU Module and simultaneously to the PSD Module as a result of any of the following four events: – The external RESET_IN pin is asserted – The Low Voltage Detect (LVD) circuitry has detected a voltage on VCC below a specific threshold (power-on or voltage sags) – The JTAG Debug interface has issued a reset command – The Watch Dog Timer (WDT) has timed out The resulting internal reset signal, MCU_RESET, will force the 8032 into a known reset state while asserted, and then 8032 program execution will jump to the reset vector at program address 0000h just after MCU_RESET is deasserted. The MCU Module will also assert an active low internal reset signal, RESET, to the PSD Module. If needed, the signal RESET can be driven out to external system components through any PLD output pin on the PSD Module. When driving this “RESET_OUT” signal from a PLD output, the user can choose to make it either active-high or activelow logic, depending on the PLD equation. External Reset Input Pin, RESET_IN The RESET_IN pin can be connected directly to a mechanical reset switch or other device which pulls the signal to ground to invoke a reset. RESET_IN is pulled up internally and enters a Schmitt trigger input buffer with a voltage hysteresis of VRST_HYS for immunity to the effects of slow signal rise and fall times, as shown in Figure 20. RESET_IN is also filtered to reject a voltage spike less than a duration of tRST_FIL. The RESET_IN signal must be maintained at a logic '0' for at least a duration of tRST_LO_IN while the oscillator is running. The resulting MCU_RESET signal will last only as long as the RESET_IN signal is active (it is not stretched). Refer to the Supervisor AC specifications in Table 150., page 221 at the end of this document for these parameter values. Figure 20. Supervisor Reset Generation S Q MCU Clock Sync Noise Filter VCC PIN PULL-UP DELAY, tRST_ACTV R AI09603 RESET_IN RESET to PSD Module MCU_RESET to MCU and Peripherals LVD JTAG Debug WDTuPSD33xx 66/231 Low VCC Voltage Detect, LVD An internal reset is generated by the LVD circuit when VCC drops below the reset threshold, VLV_THRESH. After VCC returns to the reset threshold, the MCU_RESET signal will remain asserted for tRST_ACTV before it is released. The LVD circuit is always enabled (cannot be disabled by SFR), even in Idle Mode and Power-down Mode. The LVD input has a voltage hysteresis of VRST_HYS and will reject voltage spikes less than a duration of tRST_FIL. Important: The LVD voltage threshold is VLV_THRESH, suitable for monitoring both the 3.3V VCC supply on the MCU Module and the 3.3V VDD supply on the PSD Module for 3.3V uPSD33xxV devices, since these supplies are one in the same on the circuit board. However, for 5V uPSD33xx devices, VLV_THRESH is not suitable for monitoring the 5V VDD voltage supply (VLV_THRESH is too low), but good for monitoring the 3.3V VCC supply. In the case of 5V uPSD33xx devices, an external means is required to monitor the separate 5V VDD supply, if desired. Power-up Reset At power up, the internal reset generated by the LVD circuit is latched as a logic '1' in the POR bit of the SFR named PCON (Table 24., page 50). Software can read this bit to determine whether the last MCU reset was the result of a power up (cold reset) or a reset from some other condition (warm reset). This bit must be cleared with software. JTAG Debug Reset The JTAG Debug Unit can generate a reset for debugging purposes. This reset source is also available when the MCU is in Idle Mode and PowerDown Mode (the JTAG debugger can be used to exit these modes). Watchdog Timer, WDT When enabled, the WDT will generate a reset whenever it overflows. Firmware that is behaving correctly will periodically clear the WDT before it overflows. Run-away firmware will not be able to clear the WDT, and a reset will be generated. By default, the WDT is disabled after each reset. Note: The WDT is not active during Idle mode or Power-down Mode. There are two SFRs that control the WDT, they are WDKEY (Table 37., page 68) and WDRST (Table 38., page 68). If WDKEY contains 55h, the WDT is disabled. Any value other than 55h in WDKEY will enable the WDT. By default, after any reset condition, WDKEY is automatically loaded with 55h, disabling the WDT. It is the responsibility of initialization firmware to write some value other than 55h to WDKEY after each reset if the WDT is to be used. The WDT consists of a 24-bit up-counter (Figure 21), whose initial count is 000000h by default after every reset. The most significant byte of this counter is controlled by the SFR, WDRST. After being enabled by WDKEY, the 24-bit count is increased by 1 for each MCU machine cycle. When the count overflows beyond FFFFFh (224 MCU machine cycles), a reset is issued and the WDT is automatically disabled (WDKEY = 55h again). To prevent the WDT from timing out and generating a reset, firmware must repeatedly write some value to WDRST before the count reaches FFFFFh. Whenever WDRST is written, the upper 8 bits of the 24-bit counter are loaded with the written value, and the lower 16 bits of the counter are cleared to 0000h. The WDT time-out period can be adjusted by writing a value other that 00h to WDRST. For example, if WDRST is written with 04h, then the WDT will start counting 040000h, 040001h, 040002h, and so on for each MCU machine cycle. In this example, the WDT time-out period is shorter than if WDRST was written with 00h, because the WDT is an up-counter. A value for WDRST should never be written that results in a WDT time-out period shorter than the time required to complete the longest code task in the application, else unwanted WDT overflows will occur. Figure 21. Watchdog Counter 23 15 7 0 8-bits 8-bits 8-bits SFR, WDRST AI0960467/231 uPSD33xx The formula to determine WDT time-out period is: WDTPERIOD = tMACH_CYC x NOVERFLOW NOVERFLOW is the number of WDT up-counts required to reach FFFFFFh. This is determined by the value written to the SFR, WDRST. tMACH_CYC is the average duration of one MCU machine cycle. By default, an MCU machine cycle is always 4 MCU_CLK periods for uPSD33xx, but the following factors can sometimes add more MCU_CLK periods per machine cycle: – The number of MCU_CLK periods assigned to MCU memory bus cycles as determined in the SFR, BUSCON. If this setting is greater than 4, then machine cycles have additional MCU_CLK periods during memory transfers. – Whether or not the PFQ/BC circuitry issues a stall during a particular MCU machine cycle. A stall adds more MCU_CLK periods to a machine cycle until the stall is removed. tMACH_CYC is also affected by the absolute time of a single MCU_CLK period. This number is fixed by the following factors: – Frequency of the external crystal, resonator, or oscillator: (fOSC) – Bit settings in the SFR CCON0, which can divide fOSC and change MCU_CLK As an example, assume the following: 1. fOSC is 40MHz, thus its period is 25ns. 2. CCON0 is 10h, meaning no clock division, so the period of MCU_CLK is also 25ns. 3. BUSCON is C1h, meaning the PFQ and BC are enabled, and each MCU memory bus cycle is 4 MCU_CLK periods, adding no additional MCU_CLK periods to MCU machine cycles during memory transfers. 4. Assume there are no stalls from the PFQ/BC. In reality, there are occational stalls but their occurance has minimal impact on WDT timeout period. 5. WDRST contains 00h, meaning a full 224 upcounts are required to reach FFFFFh and generate a reset. In this example, tMACH_CYC = 100ns (4 MCU_CLK periods x 25ns) NOVERFLOW = 224 = 16777216 up-counts WDTPERIOD = 100ns X 16777216 = 1.67 seconds The actual value will be slightly longer due to PFQ/ BC. Firmware Example: The following 8051 assembly code illustrates how to operate the WDT. A simple statement in the reset initialization firmware enables the WDT, and then a periodic write to clear the WDT in the main firmware is required to keep the WDT from overflowing. This firmware is based on the example above (40MHz fOSC, CCON0 = 10h, BUSCON = C1h). For example, in the reset initialization firmware (the function that executes after a jump to the reset vector): Somewhere in the flow of the main program, this statement will execute periodically to reset the WDT before it’s time-out period of 1.67 seconds. For example: MOV AE, #AA ; enable WDT by writing value to ; WDKEY other than 55h MOV A6, #00 ; reset WDT, loading 000000h. ; Counting will automatically ; resume as long as 55h in not in ; WDKEYuPSD33xx 68/231 Table 37. WDKEY: Watchdog Timer Key Register (SFR AEh, reset value 55h) Table 38. WDRST: Watchdog Timer Reset Counter Register (SFR A6h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDKEY[7:0] Details Bit Symbol R/W Definition [7:0] WDKEY W 55h disables the WDT from counting. 55h is automatically loaded in this SFR after any reset condition, leaving the WDT disabled by default. Any value other than 55h written to this SFR will enable the WDT, and counting begins. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDRST[7:0] Details Bit Symbol R/W Definition [7:0] WDRST W This SFR is the upper byte of the 24-bit WDT up-counter. Writing this SFR sets the upper byte of the counter to the written value, and clears the lower two bytes of the counter to 0000h. Counting begins when WDKEY does not contain 55h.69/231 uPSD33xx STANDARD 8032 TIMER/COUNTERS There are three 8032-style 16-bit Timer/Counter registers (Timer 0, Timer 1, Timer 2) that can be configured to operate as timers or event counters. There are two additional 16-bit Timer/Counters in the Programmable Counter Array (PCA), seePCA Block, page 123 for details. Standard Timer SFRs Timer 0 and Timer 1 have very similar functions, and they share two SFRs for control: ■ TCON (Table 39., page 70) ■ TMOD (Table 40., page 72). Timer 0 has two SFRs that form the 16-bit counter, or that can hold reload values, or that can scale the clock depending on the timer/counter mode: ■ TH0 is the high byte, address 8Ch ■ TL0 is the low byte, address 8Ah Timer 1 has two similar SFRs: ■ TH1 is the high byte, address 8Dh ■ TL1 is the low byte, address 8Bh Timer 2 has one control SFR: ■ T2CON (Table 41., page 75) Timer 2 has two SFRs that form the 16-bit counter, and perform other functions: ■ TH2 is the high byte, address CDh ■ TL2 is the low byte, address CCh Timer 2 has two SFRs for capture and reload: ■ RCAP2H is the high byte, address CBh ■ RCAP2L is the low byte, address CAh Clock Sources When enabled in the “Timer” function, the Registers THx and TLx are incremented every 1/12 of the oscillator frequency (fOSC). This timer clock source is not effected by MCU clock dividers in the CCON0, stalls from PFQ/BC, or bus transfer cycles. Timers are always clocked at 1/12 of fOSC. When enabled in the “Counter” function, the Registers THx and TLx are incremented in response to a 1-to-0 transition sampled at their corresponding external input pin: pin C0 for Timer 0; pin C1 for Timer 1; or pin T2 for Timer 2. In this function, the external clock input pin is sampled by the counter at a rate of 1/12 of fOSC. When a logic '1' is determined in one sample, and a logic '0' in the next sample period, the count is incremented at the very next sample period (period1: sample=1, period2: sample=0, period3: increment count while continuing to sample). This means the maximum count rate is 1/24 of the fOSC. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be active for at least one full sample period (12 / fOSC, seconds). However, if MCU_CLK is divided by the SFR CCON0, then the sample period must be calculated based on the resultant, longer, MCU_CLK frequency. In this case, an external clock signal on pins C0, C1, or T2 should have a duration longer than one MCU machine cycle, tMACH_CYC. The section, Watchdog Timer, WDT, page 66 explains how to estimate tMACH_CYC.uPSD33xx 70/231 Table 39. TCON: Timer Control Register (SFR 88h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Details Bit Symbol R/W Definition 7 TF1 R Timer 1 overflow interrupt flag. Set by hardware upon overflow. Automatically cleared by hardware after firmware services the interrupt for Timer 1. 6 TR1 R,W Timer 1 run control. 1 = Timer/Counter 1 is on, 0 = Timer/Counter 1 is off. 5 TF0 R Timer 0 overflow interrupt flag. Set by hardware upon overflow. Automatically cleared by hardware after firmware services the interrupt for Timer 0. 4 TR0 R,W Timer 0 run control. 1 = Timer/Counter 0 is on, 0 = Timer/Counter 0 is off. 3 IE1 R Interrupt flag for external interrupt pin, EXTINT1. Set by hardware when edge is detected on pin. Automatically cleared by hardware after firmware services EXTINT1 interrupt. 2 IT1 R,W Trigger type for external interrupt pin EXTINT1. 1 = falling edge, 0 = lowlevel 1 IE0 R Interrupt flag for external interrupt pin, EXTINT0. Set by hardware when edge is detected on pin. Automatically cleared by hardware after firmware services EXTINT0 interrupt. 0 IT0 R,W Trigger type for external interrupt pin EXTINT0. 1 = falling edge, 0 = lowlevel71/231 uPSD33xx SFR, TCON Timer 0 and Timer 1 share the SFR, TCON, that controls these timers and provides information about them. See Table 39., page 70. Bits IE0 and IE1 are not related to Timer/Counter functions, but they are set by hardware when a signal is active on one of the two external interrupt pins, EXTINT0 and EXTINT1. For system information on all of these interrupts, see Table 16., page 41, Interrupt Summary. Bits IT0 and IT1 are not related to Timer/Counter functions, but they control whether or not the two external interrupt input pins, EXTINT0 and EXTINT1 are edge or level triggered. SFR, TMOD Timer 0 and Timer 1 have four modes of operation controlled by the SFR named TMOD (Table 40). Timer 0 and Timer 1 Operating Modes The “Timer” or “Counter” function is selected by the C/T control bits in TMOD. The four operating modes are selected by bit-pairs M[1:0] in TMOD. Modes 0, 1, and 2 are the same for both Timer/ Counters. Mode 3 is different. Mode 0. Putting either Timer/Counter into Mode 0 makes it an 8-bit Counter with a divide-by-32 prescaler. Figure 22 shows Mode 0 operation as it applies to Timer 1 (same applies to Timer 0). In this mode, the Timer Register is configured as a 13-bit register. As the count rolls over from all '1s' to all '0s,' it sets the Timer Interrupt flag TF1. The counted input is enabled to the Timer when TR1 = 1 and either GATE = 0 or EXTINT1 = 1. (Setting GATE = 1 allows the Timer to be controlled by external input pin, EXTINT1, to facilitate pulse width measurements). TR1 is a control bit in the SFR, TCON. GATE is a bit in the SFR, TMOD. The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Setting the run flag, TR1, does not clear the registers. Mode 0 operation is the same for the Timer 0 as for Timer 1. Substitute TR0, TF0, C0, TL0, TH0, and EXTINT0 for the corresponding Timer 1 signals in Figure 22. There are two different GATE Bits, one for Timer 1 and one for Timer 0. Mode 1. Mode 1 is the same as Mode 0, except that the Timer Register is being run with all 16 bits. Mode 2. Mode 2 configures the Timer Register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 23., page 73. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset with firmware. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0. Mode 3. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 24., page 73. TL0 uses the Timer 0 control Bits: C/T, GATE, TR0, and TF0, as well as the pin EXTINT0. TH0 is locked into a timer function (counting at a rate of 1/12 fOSC) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the “Timer 1“ interrupt flag. Mode 3 is provided for applications requiring an extra 8-bit timer on the counter (see Figure 24., page 73). With Timer 0 in Mode 3, a uPSD33xx device can look like it has three Timer/ Counters (not including the PCA). When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt.uPSD33xx 72/231 Table 40. TMOD: Timer Mode Register (SFR 89h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GATE C/T M[1:0] GATE C/T M[1:0] Details Bit Symbol R/W Timer Definition (T/C is abbreviation for Timer/Counter) 7 GATE R,W Timer 1 Gate control. When GATE = 1, T/C is enabled only while pin EXTINT1 is '1' and the flag TR1 is '1.' When GATE = 0, T/C is enabled whenever the flag TR1 is '1.' 6 C/T R,W Counter or Timer function select. When C/T = 0, function is timer, clocked by internal clock. C/T = 1, function is counter, clocked by signal sampled on external pin, C1. [5:4] M[1:0] R,W Mode Select. 00b = 13-bit T/C. 8 bits in TH1 with TL1 as 5-bit prescaler. 01b = 16-bit T/C. TH1 and TL1 are cascaded. No prescaler. 10b = 8-bit auto-reload T/C. TH1 holds a constant and loads into TL1 upon overflow. 11b = Timer Counter 1 is stopped. 3 GATE R,W Timer 0 Gate control. When GATE = 1, T/C is enabled only while pin EXTINT0 is '1' and the flag TR0 is '1.' When GATE = 0, T/C is enabled whenever the flag TR0 is '1.' 2 C/T R,W Counter or Timer function select. When C/T = 0, function is timer, clocked by internal clock. C/T = 1, function is counter, clocked by signal sampled on external pin, C0. [1:0] M[1:0] R,W Mode Select. 00b = 13-bit T/C. 8 bits in TH0 with TL0 as 5-bit prescaler. 01b = 16-bit T/C. TH0 and TL0 are cascaded. No prescaler. 10b = 8-bit auto-reload T/C. TH0 holds a constant and loads into TL0 upon overflow. 11b = TL0 is 8-bit T/C controlled by standard Timer 0 control bits. TH0 is a separate 8-bit timer that uses Timer 1 control bits.73/231 uPSD33xx Figure 22. Timer/Counter Mode 0: 13-bit Counter Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload Figure 24. Timer/Counter Mode 3: Two 8-bit Counters AI06622 f OSC TF1 Interrupt Gate TR1 EXTINT1 pin C1 pin Control TL1 (5 bits) TH1 (8 bits) C/T = 0 C/T = 1 ÷ 12 AI06623 f OSC TF1 Interrupt Gate TR1 EXTINT1 pin C1 pin Control TL1 (8 bits) TH1 (8 bits) C/T = 0 C/T = 1 ÷ 12 AI06624 f OSC TF0 Interrupt Gate TR0 EXTINT0 pin C0 pin Control TL0 (8 bits) C/T = 0 C/T = 1 ÷ 12 f OSC TF1 Interrupt Control TH0 (8 bits) ÷ 12 TR1uPSD33xx 74/231 Timer 2 Timer 2 can operate as either an event timer or as an event counter. This is selected by the bit C/T2 in the SFR named, T2CON (Table 41., page 75). Timer 2 has three operating modes selected by bits in T2CON, according to Table 42., page 76. The three modes are: ■ Capture mode ■ Auto re-load mode ■ Baud rate generator mode Capture Mode. In Capture Mode there are two options which are selected by the bit EXEN2 in T2CON. Figure 25., page 79 illustrates Capture mode. If EXEN2 = 0, then Timer 2 is a 16-bit timer if C/T2 = 0, or it’s a 16-bit counter if C/T2 = 1, either of which sets the interrupt flag bit TF2 upon overflow. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input pin T2X causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into Registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2X causes interrupt flag bit EXF2 in T2CON to be set. Either flag TF2 or EXF2 will generate an interrupt and the MCU must read both flags to determine the cause. Flags TF2 and EXF2 are not automatically cleared by hardware, so the firmware servicing the interrupt must clear the flag(s) upon exit of the interrupt service routine. Auto-reload Mode. In the Auto-reload Mode, there are again two options, which are selected by the bit EXEN2 in T2CON. Figure 26., page 79 shows Auto-reload mode. If EXEN2 = 0, then when Timer 2 counts up and rolls over from FFFFh it not only sets the interrupt flag TF2, but also causes the Timer 2 registers to be reloaded with the 16-bit value contained in Registers RCAP2L and RCAP2H, which are preset with firmware. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2X will also trigger the 16-bit reload and set the interrupt flag EXF2. Again, firmware servicing the interrupt must read both TF2 and EXF2 to determine the cause, and clear the flag(s) upon exit. Note: The uPSD33xx does not support selectable up/down counting in Auto-reload mode (this feature was an extension to the original 8032 architecture).75/231 uPSD33xx Table 41. T2CON: Timer 2 Control Register (SFR C8h, reset value 00h) Note: 1. The RCLK1 and TCLK1 Bits in the SFR named PCON control UART1, and have the exact same function as RCLK and TCLK. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 Details Bit Symbol R/W Definition 7 TF2 R,W Timer 2 flag, causes interrupt if enabled. TF2 is set by hardware upon overflow. Must be cleared by firmware. TF2 will not be set when either RCLK or TCLK =1. 6 EXF2 R,W Timer 2 flag, causes interrupt if enabled. EXF2 is set when a capture or reload is caused by a negative transition on T2X pin and EXEN2 = 1. EXF2 must be cleared by firmware. 5 RCLK(1) R,W UART0 Receive Clock control. When RCLK = 1, UART0 uses Timer 2 overflow pulses for its receive clock in Modes 1 and 3. RCLK=0, Timer 1 overflow is used for its receive clock 4 TCLK(1) R,W UART0 Transmit Clock control. When TCLK = 1, UART0 uses Timer 2 overflow pulses for its transmit clock in Modes 1 and 3. TCLK=0, Timer 1 overflow is used for transmit clock 3 EXEN2 R,W Timer 2 External Enable. When EXEN2 = 1, capture or reload results when negative edge on pin T2X occurs. EXEN2 = 0 causes Timer 2 to ignore events at pin T2X. 2 TR2 R,W Timer 2 run control. 1 = Timer/Counter 2 is on, 0 = Timer Counter 2 is off. 1 C/T2 R,W Counter or Timer function select. When C/T2 = 0, function is timer, clocked by internal clock. When C/T2 = 1, function is counter, clocked by signal sampled on external pin, T2. 0 CP/RL2 R,W Capture/Reload. When CP/RL2 = 1, capture occurs on negative transition at pin T2X if EXEN2 = 1. When CP/RL2 = 0, auto-reload occurs when Timer 2 overflows, or on negative transition at pin T2X when EXEN2=1. When RCLK = 1 or TCLK = 1, CP/RL2 is ignored, and Timer 2 is forced to autoreload upon Timer 2 overflowuPSD33xx 76/231 Table 42. Timer/Counter 2 Operating Modes Note: ↓ = falling edge Mode Bits in T2CON SFR Pin T2X Remarks Input Clock RCLK or TCLK CP/ RL2 TR2 EXEN2 Timer, Internal Counter, External (Pin T2, P1.0) 16-bit Autoreload 001 0 x reload [RCAP2H, RCAP2L] to [TH2, TL2] upon overflow (up counting) fOSC/12 MAX fOSC/24 001 1 ↓ reload [RCAP2H, RCAP2L] to [TH2, TL2] at falling edge on pin T2X 16-bit Capture 0 1 1 0 x 16-bit Timer/Counter (up counting) fOSC/12 MAX fOSC/24 011 1 ↓ Capture [TH2, TL2] and store to [RCAP2H, RCAP2L] at falling edge on pin T2X Baud Rate Generator 1 x 1 0 x No overflow interrupt request (TF2) fOSC/2 – 1x1 1 ↓ Extra Interrupt on pin T2X, sets TF2 Off x x 0 x x Timer 2 stops – –77/231 uPSD33xx Baud Rate Generator Mode. The RCLK and/or TCLK Bits in the SFR T2CON allow the transmit and receive baud rates on serial port UART0 to be derived from either Timer 1 or Timer 2. Figure 27., page 80 illustrates Baud Rate Generator Mode. When TCLK = 0, Timer 1 is used as UART0’s transmit baud generator. When TCLK = 1, Timer 2 will be the transmit baud generator. RCLK has the same effect for UART0’s receive baud rate. With these two bits, UART0 can have different receive and transmit baud rates - one generated by Timer 1, the other by Timer 2. Note: Bits RCLK1 and TCLK1 in the SFR named PCON (see PCON: Power Control Register (SFR 87h, reset value 00h), page 50) have identical functions as RCLK and TCLK but they apply to UART1 instead. For simplicity in the following discussions about baud rate generation, no suffix will be used when referring to SFR registers and bits related to UART0 or UART1, since each UART interface has identical operation. Example, TCLK or TCLK1 will be referred to as just TCLK. The Baud Rate Generator Mode is similar to the Auto-reload Mode, in that a roll over in TH2 causes the Timer 2 registers, TH2 and TL2, to be reloaded with the 16-bit value in Registers RCAP2H and RCAP2L, which are preset with firmware. The baud rates in UART Modes 1 and 3 are determined by Timer 2’s overflow rate as follows: UART Mode 1,3 Baud Rate = Timer 2 Overflow Rate / 16 The timer can be configured for either “timer” or “counter” operation. In the most typical applications, it is configured for “timer” operation (C/T2 = 0). “Timer” operation is a little different for Timer 2 when it's being used as a baud rate generator. In this case, the baud rate is given by the formula: UART Mode 1,3 Baud Rate = fOSC/(32 x [65536 – [RCAP2H, RCAP2L])) where [RCAP2H, RCAP2L] is the content of the SFRs RCAP2H and RCAP2L taken as a 16-bit unsigned integer. A roll-over in TH2 does not set TF2, and will not generate an interrupt. Therefore, the Timer Interrupt does not have to be disabled when Timer 2 is in the Baud Rate Generator Mode. If EXEN2 is set, a 1-to-0 transition on pin T2X will set the Timer 2 interrupt flag EXF2, but will not cause a reload from RCAP2H and RCAP2L to TH2 and TL2. Thus when Timer 2 is in use as a baud rate generator, the pin T2X can be used as an extra external interrupt, if desired. When Timer 2 is running (TR2 = 1) in a “timer” function in the Baud Rate Generator Mode, firmware should not read or write TH2 or TL2. Under these conditions the results of a read or write may not be accurate. However, SFRs RCAP2H and RCAP2L may be read, but should not be written, because a write might overlap a reload and cause write and/or reload errors. Timer 2 should be turned off (clear TR2) before accessing Timer 2 or Registers RCAP2H and RCAP2L, in this case. Table 43., page 78 shows commonly used baud rates and how they can be obtained from Timer 2, with T2CON = 34h.uPSD33xx 78/231 Table 43. Commonly Used Baud Rates Generated from Timer2 (T2CON = 34h) fOSC MHz Desired Baud Rate Timer 2 SFRs Resulting Baud Rate Baud Rate Deviation RCAP2H (hex) RCAP2L(hex) 40.0 115200 FF F5 113636 -1.36% 40.0 57600 FF EA 56818 -1.36% 40.0 28800 FF D5 29070 0.94% 40.0 19200 FF BF 19231 0.16% 40.0 9600 FF 7E 9615 0.16% 36.864 115200 FF F6 115200 0 36.864 57600 FF EC 57600 0 36.864 28800 FF D8 28800 0 36.864 19200 FF C4 19200 0 36.864 9600 FF 88 9600 0 36.0 28800 FF D9 28846 0.16% 36.0 19200 FF C5 19067 -0.69% 36.0 9600 FF 8B 9615 0.16% 24.0 57600 FF F3 57692 0.16% 24.0 28800 FF E6 28846 0.16% 24.0 19200 FF D9 19231 0.16% 24.0 9600 FF B2 9615 0.16% 12.0 28800 FF F3 28846 0.16% 12.0 9600 FF D9 9615 0.16% 11.0592 115200 FF FD 115200 0 11.0592 57600 FF FA 57600 0 11.0592 28800 FF F4 28800 0 11.0592 19200 FF EE 19200 0 11.0592 9600 FF DC 9600 0 3.6864 115200 FF FF 115200 0 3.6864 57600 FF FE 57600 0 3.6864 28800 FF FC 28800 0 3.6864 19200 FF FA 19200 0 3.6864 9600 FF F4 9600 0 1.8432 19200 FF FD 19200 0 1.8432 9600 FF FA 9600 079/231 uPSD33xx Figure 25. Timer 2 in Capture Mode Figure 26. Timer 2 in Auto-Reload Mode AI06625 f OSC TF2 Capture TR2 T2 pin Control TL2 (8 bits) TH2 (8 bits) C/T2 = 0 C/T2 = 1 ÷ 12 EXP2 Control EXEN2 RCAP2L RCAP2H T2X pin Timer 2 Interrupt Transition Detector AI06626 f OSC TF2 Reload TR2 T2 pin Control TL2 (8 bits) TH2 (8 bits) C/T2 = 0 C/T2 = 1 ÷ 12 EXP2 Control EXEN2 RCAP2L RCAP2H T2X pin Timer 2 Interrupt Transition DetectoruPSD33xx 80/231 Figure 27. Timer 2 in Baud Rate Generator Mode AI09605 f OSC Reload TR2 T2 pin Control Note: Oscillator frequency is divided by 2, not 12 like in other timer modes. Note: Availability of additional external interrupt. TL2 (8 bits) TH2 (8 bits) C/T2 = 0 C/T2 = 1 ÷ 12 ÷ 2 ÷ 16 ÷ 16 EXF2 Control EXEN2 RCAP2L RCAP2H T2X pin Timer 2 Interrupt TX CLK RX CLK Timer 1 Overflow SMOD RCLK '1' '0' '0' '1' '1' '0' TCLK Transition Detector81/231 uPSD33xx SERIAL UART INTERFACES uPSD33xx devices provide two standard 8032 UART serial ports. – The first port, UART0, is connected to pins RxD0 (P3.0) and TxD0 (P3.1) – The second port, UART1 is connected to pins RxD1 (P1.2) and TxD1 (P1.3). UART1 can optionally be routed to pins P4.2 and P4.3 as described in Alternate Functions, page 59. The operation of the two serial ports are the same and are controlled by two SFRs: ■ SCON0 (Table 45., page 82) for UART0 ■ SCON1 (Table 46., page 83) for UART1 Each UART has its own data buffer accessed through an SFR listed below: ■ SBUF0 for UART0, address 99h ■ SBUF1 for UART1, address D9h When writing SBU0 or SBUF1, the data automatically loads into the associated UART transmit data register. When reading this SFR, data comes from a different physical register, which is the receive register of the associated UART. Note: For simplicity in the remaining UART discussions, the suffix “0” or “1” will be dropped when referring to SFR registers and bits related to UART0 or UART1, since each UART interface has identical operation. Example, SBUF0 and SBUF1 will be referred to as just SBUF. Each UART serial port can be full-duplex, meaning it can transmit and receive simultaneously. Each UART is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the SBUF Register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost. UART Operation Modes Each UART can operate in one of four modes, one mode is synchronous, and the others are asynchronous as shown in Table 44. Mode 0. Mode 0 provides asynchronous, half-duplex operation. Serial data is both transmitted, and received on the RxD pin. The TxD pin outputs a shift clock for both transmit and receive directions, thus the MCU must be the master. Eight bits are transmitted/received LSB first. The baud rate is fixed at 1/12 of fOSC. Mode 1. Mode 1 provides standard asynchronous, full-duplex communication using a total of 10 bits per data byte. Data is transmitted through TxD and received through RxD with: a Start Bit (logic '0'), eight data bits (LSB first), and a Stop Bit (logic '1'). Upon receive, the eight data bits go into the SFR SBUF, and the Stop Bit goes into bit RB8 of the SFR SCON. The baud rate is variable and derived from overflows of Timer 1 or Timer 2. Mode 2. Mode 2 provides asynchronous, full-duplex communication using a total of 11 bits per data byte. Data is transmitted through TxD and received through RxD with: a Start Bit (logic '0'); eight data bits (LSB first); a programmable 9th data bit; and a Stop Bit (logic '1'). Upon Transmit, the 9th data bit (from bit TB8 in SCON) can be assigned the value of '0' or '1.' Or, for example, the Parity Bit (P, in the PSW) could be moved into TB8. Upon receive, the 9th data bit goes into RB8 in SCON, while the Stop Bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of fOSC. Mode 3. Mode 3 is the same as Mode 2 in all respects except the baud rate is variable like it is in Mode 1. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming Start Bit if REN = 1. Table 44. UART Operating Modes Mode Synchronization Bits of SFR, SCON Baud Clock Data Bits Start/Stop Bits See Figure SM0 SM1 0 Synchronous 0 0 fOSC/12 8 None Figure 28., page 86 1 Asynchronous 0 1 Timer 1 or Timer 2 Overflow 8 1 Start, 1 Stop Figure 30., page 88 2 Asynchronous 1 0 fOSC/32 or fOSC/64 9 1 Start, 1 Stop Figure 32., page 90 3 Asynchronous 1 1 Timer 1 or Timer 2 Overflow 9 1 Start, 1 Stop Figure 34., page 91uPSD33xx 82/231 Multiprocessor Communications. Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into bit RB8, then comes a stop bit. The port can be programmed such that when the stop bit is received, the UART interrupt will be activated only if bit RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multi-processor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that were not being addressed leave their SM2 bits set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1, SM2 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. Serial Port Control Registers The SFR SCON0 controls UART0, and SCON1 controls UART1, shown in Table 45 and Table 46. These registers contain not only the mode selection bits, but also the 9th data bit for transmit and receive (bits TB8 and RB8), and the UART Interrupt flags, TI and RI. Table 45. SCON0: Serial Port UART0 Control Register (SFR 98h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SM0 SM1 SM2 REN TB8 RB8 TI RI Details Bit Symbol R/W Definition 7 SM0 R,W Serial Mode Select, See Table 44., page 81. Important, notice bit order of SM0 and SM1. [SM0:SM1] = 00b, Mode 0 [SM0:SM1] = 01b, Mode 1 [SM0:SM1] = 10b, Mode 2 [SM0:SM1] = 11b, Mode 3 6 SM1 R,W 5 SM2 R,W Serial Multiprocessor Communication Enable. Mode 0: SM2 has no effect but should remain 0. Mode 1: If SM2 = 0 then stop bit ignored. SM2 =1 then RI active if stop bit = 1. Mode 2 and 3: Multiprocessor Comm Enable. If SM2=0, 9th bit is ignored. If SM2=1, RI active when 9th bit = 1. 4 REN R,W Receive Enable. If REN=0, UART reception disabled. If REN=1, reception is enabled 3 TB8 R,W TB8 is assigned to the 9th transmission bit in Mode 2 and 3. Not used in Mode 0 and 1. 2 RB8 R,W Mode 0: RB8 is not used. Mode 1: If SM2 = 0, the RB8 is the level of the received stop bit. Mode 2 and 3: RB8 is the 9th data bit that was received in Mode 2 and 3. 1 TI R,W Transmit Interrupt flag. Causes interrupt at end of 8th bit time when transmitting in Mode 0, or at beginning of stop bit transmission in other modes. Must clear flag with firmware. 0 RI R,W Receive Interrupt flag. Causes interrupt at end of 8th bit time when receiving in Mode 0, or halfway through stop bit reception in other modes (see SM2 for exception). Must clear this flag with firmware.83/231 uPSD33xx Table 46. SCON1: Serial Port UART1 Control Register (SFR D8h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SM0 SM1 SM2 REN TB8 RB8 TI RI Details Bit Symbol R/W Definition 7 SM0 R,W Serial Mode Select, See Table 44., page 81. Important, notice bit order of SM0 and SM1. [SM0:SM1] = 00b, Mode 0 [SM0:SM1] = 01b, Mode 1 [SM0:SM1] = 10b, Mode 2 [SM0:SM1] = 11b, Mode 3 6 SM1 R,W 5 SM2 R,W Serial Multiprocessor Communication Enable. Mode 0: SM2 has no effect but should remain 0. Mode 1: If SM2 = 0 then stop bit ignored. SM2 =1 then RI active if stop bit = 1. Mode 2 and 3: Multiprocessor Comm Enable. If SM2=0, 9th bit is ignored. If SM2=1, RI active when 9th bit = 1. 4 REN R,W Receive Enable. If REN=0, UART reception disabled. If REN=1, reception is enabled 3 TB8 R,W TB8 is assigned to the 9th transmission bit in Mode 2 and 3. Not used in Mode 0 and 1. 2 RB8 R,W Mode 0: RB8 is not used. Mode 1: If SM2 = 0, the RB8 is the level of the received stop bit. Mode 2 and 3: RB8 is the 9th data bit that was received in Mode 2 and 3. 1 TI R,W Transmit Interrupt flag. Causes interrupt at end of 8th bit time when transmitting in Mode 0, or at beginning of stop bit transmission in other modes. Must clear flag with firmware. 0 RI R,W Receive Interrupt flag. Causes interrupt at end of 8th bit time when receiving in Mode 0, or halfway through stop bit reception in other modes (see SM2 for exception). Must clear this flag with firmware.uPSD33xx 84/231 UART Baud Rates The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = fOSC / 12 The baud rate in Mode 2 depends on the value of the bit SMOD in the SFR named PCON. If SMOD = 0 (default value), the baud rate is 1/64 the oscillator frequency, fOSC. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. Mode 2 Baud Rate = (2SMOD / 64) x fOSC Baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate. Using Timer 1 to Generate Baud Rates. When Timer 1 is used as the baud rate generator (bits RCLK = 0, TCLK = 0), the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Mode 1,3 Baud Rate = (2SMOD / 32) x (Timer 1 overflow rate) The Timer 1 Interrupt should be disabled in this application. The Timer itself can be configured for either “timer” or “counter” operation, and in any of its 3 running modes. In the most typical applications, it is configured for “timer” operation, in the Auto-reload Mode (high nibble of the SFR TMOD = 0010B). In that case the baud rate is given by the formula: Mode 1,3 Baud Rate = (2SMOD / 32) x (fOSC / (12 x [256 – (TH1)])) Table 47 lists various commonly used baud rates and how they can be obtained from Timer 1. Using Timer/Counter 2 to Generate Baud Rates. See Baud Rate Generator Mode, page 77. Table 47. Commonly Used Baud Rates Generated from Timer 1 UART Mode fOSC MHz Desired Baud Rate Resultant Baud Rate Baud Rate Deviation SMOD bit in PCON Timer 1 C/T Bit in TMOD Timer Mode in TMOD TH1 Reload value (hex) Mode 0 Max 40.0 3.33MHz 3.33MHz 0 X X X X Mode 2 Max 40.0 1250 k 1250 k 0 1 X X X Mode 2 Max 40.0 625 k 625 k 0 0 X X X Modes 1 or 3 40.0 19200 18939 -1.36% 1 0 2 F5 Modes 1 or 3 40.0 9600 9470 -1.36% 1 0 2 EA Modes 1 or 3 36.0 19200 18570 -2.34% 1 0 2 F6 Modes 1 or 3 33.333 57600 57870 0.47% 1 0 2 FD Modes 1 or 3 33.333 28800 28934 0.47% 1 0 2 FA Modes 1 or 3 33.333 19200 19290 0.47% 1 0 2 F7 Modes 1 or 3 33.333 9600 9645 0.47% 1 0 2 EE Modes 1 or 3 24.0 9600 9615 0.16% 1 0 2 F3 Modes 1 or 3 12.0 4800 4808 0.16% 1 0 2 F3 Modes 1 or 3 11.0592 57600 57600 0 1 0 2 FF Modes 1 or 3 11.0592 28800 28800 0 1 0 2 FE Modes 1 or 3 11.0592 19200 19200 0 1 0 2 FD Modes 1 or 3 11.0592 9600 9600 0 1 0 2 FA Modes 1 or 3 3.6864 19200 19200 0 1 0 2 FF Modes 1 or 3 3.6864 9600 9600 0 1 0 2 FE Modes 1 or 3 1.8432 9600 9600 0 1 0 2 FF Modes 1 or 3 1.8432 4800 4800 0 1 0 2 FE85/231 uPSD33xx More About UART Mode 0 Refer to the block diagram in Figure 28., page 86, and timing diagram in Figure 29., page 86. Transmission is initiated by any instruction which writes to the SFR named SBUF. At the end of a write operation to SBUF, a 1 is loaded into the 9th position of the transmit shift register and tells the TX Control unit to begin a transmission. Transmission begins on the following MCU machine cycle, when the “SEND” signal is active in Figure 29. SEND enables the output of the shift register to the alternate function on the port containing pin RxD, and also enables the SHIFT CLOCK signal to the alternate function on the port containing the pin, TxD. At the end of each SHIFT CLOCK in which SEND is active, the contents of the transmit shift register are shifted to the right one position. As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the '1' that was initially loaded into the 9th position, is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift, then deactivate SEND, and then set the interrupt flag TI. Both of these actions occur at S1P1. Reception is initiated by the condition REN = 1 and RI = 0. At the end of the next MCU machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enables the SHIFT CLOCK signal to the alternate function on the port containing the pin, TxD. Each pulse of SHIFT CLOCK moves the contents of the receive shift register one position to the left while RECEIVE is active. The value that comes in from the right is the value that was sampled at the RxD pin. As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the left-most position in the shift register, it flags the RX Control unit to do one last shift, and then it loads SBUF. After this, RECEIVE is cleared, and the receive interrupt flag RI is set.uPSD33xx 86/231 Figure 28. UART Mode 0, Block Diagram Figure 29. UART Mode 0, Timing Diagram AI06824 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Shift Clock Serial Port Interrupt f OSC/12 REN R1 Rx Clock Start Tx Clock Start Shift Shift Send Receive T R CL D S Q 7 6 5 4 3 2 1 0 RxD P3.0 Alt Input Function RxD Pin TxD Pin AI06825 Write to SBUF Send Shift RxD (Data Out) TxD (Shift Clock) TI Write to SCON RI Receive Shift RxD (Data In) TxD (Shift Clock) Clear RI Receive Transmit D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D787/231 uPSD33xx More About UART Mode 1 Refer to the block diagram in Figure 30., page 88, and timing diagram in Figure 31., page 88. Transmission is initiated by any instruction which writes to SBUF. At the end of a write operation to SBUF, a '1' is loaded into the 9th position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually starts at the end of the MCU the machine cycle following the next rollover in the divide-by-16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the writing of SBUF. Transmission begins with activation of SEND which puts the start bit at pin TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to pin TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivates SEND, and sets the interrupt flag, TI. This occurs at the 10th divide-by-16 rollover after a write to SBUF. Reception is initiated by a detected 1-to-0 transition at the pin RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not '0,' the receive circuits are reset and the unit goes back to looking for another '1'-to- '0' transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the reset of the rest of the frame will proceed. As data bits come in from the right, '1s' shift out to the left. When the start bit arrives at the left-most position in the shift register (which in mode 1 is a 9-bit register), it flags the RX Control unit to do one last shift, load SBUF and RB8, and set the receive interrupt flag RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. RI = 0, and 2. Either SM2 = 0, or the received stop bit = 1. If either of these two conditions are not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a '1'-to-'0' transition on pin RxD.uPSD33xx 88/231 Figure 30. UART Mode 1, Block Diagram Figure 31. UART Mode 1, Timing Diagram AI06826 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Serial Port Interrupt Rx Clock Start Tx Clock Start Shift Shift Send Load SBUF TI RI CL D S Q 1FFh TxD Pin Data Rx Detector RxD Pin 1-to-0 Transition Detector ÷16 Sample ÷16 ÷2 TB8 Timer1 Overflow Timer2 Overflow 0 0 1 1 0 1 TCLK RCLK SMOD AI06843 Write to SBUF Data Shift TxD TI Rx Clock RxD Bit Detector Sample Times Shift RI Receive Transmit D0 D1 D2 D3 D4 D5 D6 D7 Send Tx Clock Start Bit Stop Bit D0 D1 D2 D3 D4 D5 D6 D7 Start Bit Stop Bit89/231 uPSD33xx More About UART Modes 2 and 3 For Mode 2, refer to the block diagram in Figure 32., page 90, and timing diagram in Figure 33., page 90. For Mode 3, refer to the block diagram in Figure 34., page 91, and timing diagram in Figure 35., page 91. Keep in mind that the baud rate is programmable to either 1/32 or 1/64 of fOSC in Mode 2, but Mode 3 uses a variable baud rate generated from Timer 1 or Timer 2 rollovers. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction which writes to SBUF. At the end of a write operation to SBUF, the TB8 Bit is loaded into the 9th position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually starts at the end of the MCU the machine cycle following the next rollover in the divideby-16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the writing of SBUF. Transmission begins with activation of SEND which puts the start bit at pin TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to pin TxD. The first shift pulse occurs one bit time after that. The first shift clocks a '1' (the stop bit) into the 9th bit position of the shift register. There-after, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When bit TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND, and set the interrupt flag, TI. This occurs at the 11th divide-by 16 rollover after writing to SBUF. Reception is initiated by a detected 1-to-0 transition at pin RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not '0,' the receive circuits are reset and the unit goes back to looking for another '1'-to- '0' transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, '1s' shift out to the left. When the start bit arrives at the left-most position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control unit to do one last shift, load SBUF and RB8, and set the interrupt flag RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. RI = 0, and 2. Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a '1'-to-'0' transition on pin RxD.uPSD33xx 90/231 Figure 32. UART Mode 2, Block Diagram Figure 33. UART Mode 2, Timing Diagram AI06844 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Serial Port Interrupt Rx Clock Start Tx Clock Start Shift Shift Send Load SBUF TI RI CL D S Q 1FFh TxD Pin Data Rx Detector RxD Pin 1-to-0 Transition Detector ÷16 Sample ÷16 ÷2 TB8 f OSC/32 0 1 SMOD AI06845 Write to SBUF Data Shift TxD TI Rx Clock RxD Bit Detector Sample Times Shift RI Receive Transmit D0 D1 D2 D3 D4 D5 D6 D7 Send Tx Clock Start Bit TB8 Stop Bit D0 D1 D2 D3 D4 D5 D6 D7 Start Bit RB8 Stop Bit Stop Bit Generator91/231 uPSD33xx Figure 34. UART Mode 3, Block Diagram Figure 35. UART Mode 3, Timing Diagram AI06846 Zero Detector Internal Bus Tx Control Rx Control Internal Bus SBUF Write to SBUF Read SBUF Load SBUF SBUF Input Shift Register Shift Serial Port Interrupt Rx Clock Start Tx Clock Start Shift Shift Send Load SBUF TI RI CL D S Q 1FFh TxD Pin Data Rx Detector RxD Pin 1-to-0 Transition Detector ÷16 Sample ÷16 ÷2 TB8 Timer1 Overflow Timer2 Overflow 0 0 1 1 0 1 TCLK RCLK SMOD AI06847 Write to SBUF Data Shift TxD TI Rx Clock RxD Bit Detector Sample Times Shift RI Receive Transmit D0 D1 D2 D3 D4 D5 D6 D7 Send Tx Clock Start Bit TB8 Stop Bit D0 D1 D2 D3 D4 D5 D6 D7 Start Bit RB8 Stop Bit Stop Bit GeneratoruPSD33xx 92/231 IrDA INTERFACE uPSD33xx devices provide an internal IrDA interface that will allow the connection of the UART1 serial interface directly to an external infrared transceiver device. The IrDA interface does this by automatically shortening the pulses transmitted on UART1’s TxD1 pin, and stretching the incoming pulses received on the RxD1 pin. Reference Figures 36 and 37. When the IrDA interface is enabled, the output signal from UART1’s transmitter logic on pin TxD1 is compliant with the IrDA Physical Layer Link Specification v1.4 (www.irda.org) operating from 1.2k bps up to 115.2k bps. The pulses received on the RxD1 pin are stretched by the IrDA interface to be recognized by UART1’s receiver logic, also adhering to the IrDA specification up to 115.2k bps. Note: In Figure 37 a logic '0' in the serial data stream of a UART Frame corresponds to a logic high pulse in an IR Frame. A logic '1' in a UART Frame corresponds to no pulse in an IR Frame. Figure 36. IrDA Interface Figure 37. Pulse Shaping by the IrDA Interface UART1 IrDA Interface TxD RxD uPSD33XX IrDA Transceiver TxD1-IrDA RxD1-IrDA SIRClk AI07851 Start Bit 0101 11 1 00 0 Stop Bit UART Frame Data Bits Bit Time Pulse Width = 3/16 Bit Time Start Bit 0101 11 1 00 0 Stop Bit UART Frame IR Frame IR Frame Data Bits AI0962493/231 uPSD33xx The UART1 serial channel can operate in one of four different modes as shown in Table 44., page 81 in the section, SERIAL UART INTERFACES, page 81. However, when UART1 is used for IrDA communication, UART1 must operate in Mode 1 only, to be compatible with IrDA protocol up to 115.2k bps. The IrDA interface will support baud rates generated from Timer 1 or Timer 2, just like standard UART serial communication, but with one restriction. The transmit baud rate and receive baud rate must be the same (cannot be different rates as is allowed by standard UART communications). The IrDA Interface is disabled after a reset and is enabled by setting the IRDAEN Bit in the SFR named IRDACON (Table 48., page 93). When IrDA is disabled, the UART1's RxD and TxD signals will bypass the internal IrDA logic and instead they are routed directly to the pins RxD1 and TxD1 respectively. When IrDA is enabled, the IrDA pulse shaping logic is active and resides between UART1 and the pins RxD1 and TxD1 as shown in Figure 36., page 92. Table 48. IRDACON Register Bit Definition (SFR CEh, Reset Value 0Fh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – IRDAEN PULSE CDIV4 CDIV3 CDIV2 CDIV1 CDIV0 Details Bit Symbol R/W Definition 7 – – Reserved 6 IRDAEN RW IrDA Enable 0 = IrDA Interface is disabled 1 = IrDA is enabled, UART1 outputs are disconnected from Port 1 (or Port 4) 5 PULSE RW IrDA Pulse Modulation Select 0 = 1.627µs 1 = 3/16 bit time pulses 4-0 CDIV[4:0] RW Specify Clock Divider (see Table 49., page 94)uPSD33xx 94/231 Pulse Width Selection The IrDA interface has two ways to modulate the standard UART1 serial stream: 1. An IrDA data pulse will have a constant pulse width for any bit time, regardless of the selected baud rate. 2. An IrDA data pulse will have a pulse width that is proportional to the the bit time of the selected baud rate. In this case, an IrDA data pulse width is 3/16 of its bit time, as shown in Figure 37., page 92. The PULSE bit in the SFR named IRDACON determines which method above will be used. According to the IrDA physical layer specification, for all baud rates at 115.2k bps and below, the minimum data pulse width is 1.41µs. For a baud rate of 115.2k bps, the maximum pulse width 2.23µs. If a constant pulse width is to be used for all baud rates (PULSE bit = 0), the ideal general pulse width is 1.63µs, derived from the bit time of the fastest baud rate (8.68µs bit time for 115.2k bps rate), multiplied by the proportion, 3/16. To produce this fixed data pulse width when the PULSE bit = 0, a prescaler is needed to generate an internal reference clock, SIRClk, shown in Figure 36., page 92. SIRClk is derived by dividing the oscillator clock frequency, fOSC, using the five bits CDIV[4:0] in the SFR named IRDACON. A divisor must be chosen to produce a frequency for SIRClk that lies between 1.34 MHz and 2.13 MHz, but it is best to choose a divisor value that produces SIRClk frequency as close to 1.83MHz as possible, because SIRClk at 1.83MHz will produce an fixed IrDA data pulse width of 1.63µs. Table 49 provides recommended values for CDIV[4:0] based on several different values of fOSC. For reference, SIRClk of 2.13MHz will generate a fixed IrDA data pulse width of 1.41µs, and SIRClk of 1.34MHz will generate a fixed data pulse width of 2.23µs. Table 49. Recommended CDIV[4:0] Values to Generate SIRClk (default CDIV[4:0] = 0Fh, 15 decimal) Note: 1. When PULSE bit = 0 (fixed data pulse width), this is minimum recommended fOSC because CDIV[4:0] must be 4 or greater. fOSC (MHz) Value in CDIV[4:0] Resulting fSIRCLK (MHz) 40.00 16h, 22 decimal 1.82 36.864, or 36.00 14h, 20 decimal 1.84, or 1.80 24.00 0Dh, 13 decimal 1.84 11.059, or 12.00 06h, 6 decimal 1.84, or 2.00 7.3728(1) 04h, 4 decimal 1.8495/231 uPSD33xx I 2C INTERFACE uPSD33xx devices support one serial I2C interface. This is a two-wire communication channel, having a bi-directional data signal (SDA, pin P3.6) and a clock signal (SCL, pin P3.7) based on opendrain line drivers, requiring external pull-up resistors, RP, each with a typical value of 4.7kΩ (see Figure 38). I 2C Interface Main Features Byte-wide data is transferred, MSB first, between a Master device and a Slave device on two wires. More than one bus Master is allowed, but only one Master may control the bus at any given time. Data is not lost when another Master requests the use of a busy bus because I2C supports collision detection and arbitration. The bus Master initiates all data movement and generates the clock that permits the transfer. Once a transfer is initiated by the Master, any device addressed is considered a Slave. Automatic clock synchronization allows I2C devices with different bit rates to communicate on the same physical bus. A single device can play the role of Master or Slave, or a single device can be a Slave only. Each Slave device on the bus has a unique address, and a general broadcast address is also available. A Master or Slave device has the ability to suspend data transfers if the device needs more time to transmit or receive data. This I2C interface has the following features: – Serial I/O Engine (SIOE): serial/parallel conversion; bus arbitration; clock generation and synchronization; and handshaking are all performed in hardware – Interrupt or Polled operation – Multi-master capability – 7-bit Addressing – Supports standard speed I2C (SCL up to 100kHz), fast mode I2C (101KHz to 400kHz), and high-speed mode I2C (401KHz to 833kHz) Figure 38. Typical I2C Bus Configuration Note: 1. For 3.3V system, connect RP to 3.3V VCC. For 5.0V system, connect RP to 5.0V VDD. I 2C BUS SDA SCL RP RP VCC or VDD(1) Device with I2C Interface Device with I2C Interface SDA/P3.6 SCL/P3.7 uPSD33XX(V) Device with I2C Interface AI09623uPSD33xx 96/231 Communication Flow I 2C data flow control is based on the fact that all I 2C compatible devices will drive the bus lines with open-drain (or open-collector) line drivers pulled up with external resistors, creating a wired-AND situation. This means that either bus line (SDA or SCL) will be at a logic '1' level only when no I2C device is actively driving the line to logic '0.' The logic for handshaking, arbitration, synchronization, and collision detection is implemented by each I2C device having: 1. The ability to hold a line low against the will of the other devices who are trying to assert the line high. 2. The ability of a device to detect that another device is driving the line low against its will. Assert high means the driver releases the line and external pull-ups passively raise the signal to logic '1.' Holding low means the open-drain driver is actively pulling the signal to ground for a logic '0.' For example, if a Slave device cannot transmit or receive a byte because it is distracted by and interrupt or it has to wait for some process to complete, it can hold the SCL clock line low. Even though the Master device is generating the SCL clock, the Master will sense that the Slave is holding the SCL line low against the will of the Master, indicating that the Master must wait until the Slave releases SCL before proceeding with the transfer. Another example is when two Master devices try to put information on the bus simultaneously, the first one to release the SDA data line looses arbitration while the winner continues to hold SDA low. Two types of data transfers are possible with I2C depending on the R/W bit, see Figure 39., page 97. 1. Data transfer from Master Transmitter to Slave Receiver (R/W = 0). In this case, the Master generates a START condition on the bus and it generates a clock signal on the SCL line. Then the Master transmits the first byte on the SDA line containing the 7-bit Slave address plus the R/W bit. The Slave who owns that address will respond with an acknowledge bit on SDA, and all other Slave devices will not respond. Next, the Master will transmit a data byte (or bytes) that the addressed Slave must receive. The Slave will return an acknowledge bit after each data byte it successfully receives. After the final byte is transmitted by the Master, the Master will generate a STOP condition on the bus, or it will generate a RESTART conditon and begin the next transfer. There is no limit to the number of bytes that can be transmitted during a transfer session. 2. Data transfer from Slave Transmitter to Master Receiver (R/W = 1). In this case, the Master generates a START condition on the bus and it generates a clock signal on the SCL line. Then the Master transmits the first byte on the SDA line containing the 7-bit Slave address plus the R/W bit. The Slave who owns that address will respond with an acknowledge bit on SDA, and all other Slave devices will not respond. Next, the addressed Slave will transmit a data byte (or bytes) to the Master. The Master will return an acknowledge bit after each data byte it successfully receives, unless it is the last byte the Master desires. If so, the Master will not acknowledge the last byte and from this, the Slave knows to stop transmitting data bytes to the Master. The Master will then generate a STOP condition on the bus, or it will generate a RE-START conditon and begin the next transfer. There is no limit to the number of bytes that can be transmitted during a transfer session. A few things to know related to these transfers: – Either the Master or Slave device can hold the SCL clock line low to indicate it needs more time to handle a byte transfer. An indefinite holding period is possible. – A START condition is generated by a Master and recognized by a Slave when SDA has a 1- to-0 transition while SCL is high (Figure 39., page 97). – A STOP condition is generated by a Master and recognized by a Slave when SDA has a 0- to1 transition while SCL is high (Figure 39., page 97). – A RE-START (repeated START) condition generated by a Master can have the same function as a STOP condition when starting another data transfer immediately following the previous data transfer (Figure 39., page 97). – When transferring data, the logic level on the SDA line must remain stable while SCL is high, and SDA can change only while SCL is low. However, when not transferring data, SDA may change state while SCL is high, which creates the START and STOP bus conditions.97/231 uPSD33xx – An Acknowlegde bit is generated from a Master or a Slave by driving SDA low during the “ninth” bit time, just following each 8-bit byte that is transfered on the bus (Figure 39., page 97). A Non-Acknowledge occurs when SDA is asserted high during the ninth bit time. All byte transfers on the I2C bus include a 9th bit time reserved for an Acknowlege (ACK) or Non-Acknowledge (NACK). – An additional Master device that desires to control the bus should wait until the bus is not busy before generating a START condition so that a possible Slave operation is not interrupted. – If two Master devices both try to generate a START condition simultaneously, the Master who looses arbitration will switch immediately to Slave mode so it can recoginize it’s own Slave address should it appear on the bus. Figure 39. Data Transfer on an I2C Bus MSB 7-bit Slave Address READ/WRITE Indicator Acknowledge bits from receiver Start Condition Clock can be held low to stall transfer. Repeated if more data bytes are transferred. Repeated Start Condition Stop Condition 12 789 3-6 1 2 9 3-8 ACK MSB ACK NACK R/W AI09625uPSD33xx 98/231 Operating Modes The I2C interface supports four operating modes: ■ Master-Transmitter ■ Master-Receiver ■ Slave-Transmitter ■ Slave-Receiver The interface may operate as either a Master or a Slave within a given application, controlled by firmware writing to SFRs. By default after a reset, the I2C interface is in Master Receiver mode, and the SDA/P3.6 and SCL/ P3.7 pins default to GPIO input mode, high impedance, so there is no I2C bus interference. Before using the I2C interface, it must be initialized by firmware, and the pins must be configured. This is discussed in I 2C Operating Sequences, page 108. Bus Arbitration A Master device always samples the I2C bus to ensure a bus line is high whenever that Master is asserting a logic 1. If the line is low at that time, the Master recognizes another device is overriding it’s own transmission. A Master may start a transfer only if the I2C bus is not busy. However, it’s possible that two or more Masters may generate a START condition simultaneously. In this case, arbitration takes place on the SDA line each time SCL is high. The Master that first senses that its bus sample does not correspond to what it is driving (SDA line is low while it’s asserting a high) will immediately change from Master-Transmitter to Slave-Receiver mode. The arbitration process can carry on for many bit times if both Masters are addressing the same Slave device, and will continue into the data bits if both Masters are trying to be Master-Transmitter. It is also possible for arbitration to carry on into the acknowledge bits if both Masters are trying to be Master-Receiver. Because address and data information on the bus is determined by the winning Master, no information is lost during the arbitration process. Clock Synchronization Clock synchronization is used to synchronize arbitrating Masters, or used as a handshake by a devices to slow down the data transfer. Clock Sync During Arbitration. During bus arbitration between competing Masters, Master_X, with the longest low period on SCL, will force Master_Y to wait until Master_X finishes its low period before Master_Y proceeds to assert its high period on SCL. At this point, both Masters begin asserting their high period on SCL simultaneously, and the Master with the shortest high period will be the first to drive SCL for the next low period. In this scheme, the Master with the longest low SCL period paces low times, and the Master with the shortest high SCL period paces the high times, making synchronized arbitration possible. Clock Sync During Handshaking. This allows receivers in different devices to handle various transfer rates, either at the byte-level, or bit-level. At the byte-level, a device may pause the transfer between bytes by holding SCL low to have time to store the latest received byte or fetch the next byte to transmit. At the bit-level, a Slave device may extend the low period of SCL by holding it low. Thus the speed of any Master device will adapt to the internal operation of the Slave. General Call Address A General Call (GC) occurs when a Master-Transmitter initiates a transfer containing a Slave address of 0000000b, and the R/W bit is logic 0. All Slave devices capable of responding to this broadcast message will acknowledge the GC simultaneously and then behave as a Slave-Receiver. The next byte transmitted by the Master will be accepted and acknowledged by all Slaves capable of handling the special data bytes. A Slave that cannot handle one of these data bytes must ignore it by not acknowledging it. The I2C specification lists the possible meanings of the special bytes that follow the first GC address byte, and the actions to be taken by the Slave device(s) upon receiving them. A common use of the GC by a Master is to dynamically assign device addresses to Slave devices on the bus capable of a programmable device address. The uPSD33xx can generate a GC as a MasterTransmitter, and it can receive a GC as a Slave. When receiving a GC address (00h), an interrupt will be generated so firmware may respond to the special GC data bytes if desired.99/231 uPSD33xx Serial I/O Engine (SIOE) At the heart of the I2C interface is the hardware SIOE, shown in Figure 40. The SIOE automatically handles low-level I2C bus protocol (data shifting, handshaking, arbitration, clock generation and synchronization) and it is controlled and monitored by five SFRs. The five SFRs shown in Figure 40 are: ■ S1CON - Interface Control (Table 50., page 100) ■ S1STA - Interface Status (Table 52., page 103) ■ S1DAT - Data Shift Register (Table 53., page 104) ■ S1ADR - Device Address (Table 54., page 104) ■ S1SETUP - Sampling Rate (Table 55., page 105) Figure 40. I2C Interface SIOE Block Diagram OpenDrain Output Input OpenDrain Output Input Comparator S1SETUP - Sample Rate Control (START Condition) S1STA - Interface Status S1CON - Interface Control ACK Bit SCL / P3.7 Timing and Control Clock Generation Arbitration and Sync Periph Clock (fOSC) SDA / P3.6 8032 MCU Bus INTR to 8032 S1DAT - Shift Register Serial DATA IN Serial DATA OUT Shift Direction 8 8 8 8 8 7 7 b7 b0 S1ADR - Device Address b7 b0 AI09626uPSD33xx 100/231 I 2C Interface Control Register (S1CON) Table 50. Serial Control Register S1CON (SFR DCh, Reset Value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CR2 ENI1 STA STO ADDR AA CR[1:0] Details Bit Symbol R/W Function 7 CR2 R,W This bit, along with bits CR1 and CR0, determine the SCL clock frequency (fSCL) when SIOE is in Master mode. These bits create a clock divisor for fOSC. See Table 51. 6 ENI1 R,W I 2C Interface Enable 0 = SIOE disabled, 1 = SIOE enabled. When disabled, both SDA and SCL signals are in high impedance state. 5 STA R,W START flag. When set, Master mode is entered and SIOE generates a START condition only if the I2C bus is not busy. When a START condition is detected on the bus, the STA flag is cleared by hardware. When the STA bit is set during an interrupt service, the START condition will be generated after the interrupt service. 4 STO R,W STOP flag When STO is set in Master mode, the SIOE generates a STOP condition. When a STOP condition is detected, the STO flag is cleared by hardware. When the STO bit is set during an interrupt service, the STOP condition will be generated after the interrupt service. 3 ADDR R,W This bit is set when an address byte received in Slave mode matches the device address programmed into the S1ADR register. The ADDR bit must be cleared with firmware. 2 AA R,W Assert Acknowledge enable If AA = 1, an acknowledge signal (low on SDA) is automatically returned during the acknowledge bit-time on the SCL line when any of the following three events occur: 1. SIOE in Slave mode receives an address that matches contents of S1ADR register 2. A data byte has been received while SIOE is in Master Receiver mode 3. A data byte has been received while SIOE is a selected Slave Receiver When AA = 0, no acknowledge is returned (high on SDA during acknowledge bit-time). 1, 0 CR1, CR0 R,W These bits, along with bit CR2, determine the SCL clock frequency (fSCL) when SIOE is in Master mode. These bits create a clock divisor for fOSC. See Table 51 for values.101/231 uPSD33xx Table 51. Selection of the SCL Frequency in Master Mode based on fOSC Examples Note: 1. These values are beyond the bit rate supported by uPSD33xx. CR2 CR1 CR0 fOSC Divided by: Bit Rate (kHz) @ fOSC 12MHz fOSC 24MHz fOSC 36MHz fOSC 40MHz fOSC 0 0 0 32 375 750 X(1) X(1) 0 0 1 48 250 500 750 833 0 1 0 60 200 400 600 666 0 1 1 120 100 200 300 333 1 0 0 240 50 100 150 166 1 0 1 480 25 50 75 83 1 1 0 960 12.5 25 37.5 41 1 1 1 1920 6.25 12.5 18.75 20uPSD33xx 102/231 I 2C Interface Status Register (S1STA) The S1STA register provides status regarding immediate activity and the current state of operation on the I2C bus. All bits in this register are read-only except bit 5, INTR, which is the interrupt flag. Interrupt Conditions. If the I2C interrupt is enabled (EI2C = 1 in SFR named IEA, and EA =1 in SFR named IE), and the SIOE is initialized, then an interrupt is automatically generated when any one of the following five events occur: – When the SIOE receives an address that matches the contents of the SFR, S1ADR. Requirements: SIOE is in Slave Mode, and bit AA = 1 in the SFR S1CON. – When the SIOE receives General Call address. Requirments: SIOE is in Slave Mode, bit AA = 1 in the SFR S1CON – When a complete data byte has been received or transmitted by the SIOE while in Master mode. The interrupt will occur even if the Master looses arbitration. – When a complete data byte has been received or transmitted by the SIOE while in selected Slave mode. – A STOP condition on the bus has been recognized by the SIOE while in selected Slave mode. Selected Slave mode means the device address sent by the Master device at the beginning of the current data transfer matched the address stored in the S1ADR register. If the I2C interrupt is not enabled, the MCU may poll the INTR flag in S1STA.103/231 uPSD33xx Table 52. S1STA: I2C Interface Status Register (SFR DDh, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GC STOP INTR TX_MODE BBUSY BLOST ACK_RESP SLV Details Bit Symbol R/W Function 7 GC R General Call flag GC = 1 if the General Call address of 00h was received when SIOE is in Slave mode, and GC is cleared by a START or STOP condition on the bus. If the SIOE is in Master mode when GC = 1, the Bus Lost condition exists, and BLOST = 1. 6 STOP R STOP flag STOP = 1 while SIOE detects a STOP condition on the bus when in Master or Slave mode. 5 INTR R,W Interrupt flag INTR is set to 1 by any of the five I2C interrupt conditions listed above. INTR must be cleared by firmware. 4 TX_MODE R Transmission Mode flag TX_MODE = 1 whenever the SIOE is in Master-Transmitter or SlaveTransmitter mode. TX_MODE = 0 when SIOE is in any receiver mode. 3 BBUSY R Bus Busy flag BBUSY = 1 when the I2C bus is in use. BBUSY is set by the SIOE when a START condition exists on the bus and BBUSY is cleared by a STOP condition. 2 BLOST R Bus Lost flag BLOST is set when the SIOE is in Master mode and it looses the arbitration process to another Master device on the bus. 1 ACK_RESP R Not Acknowledge Response flag While SIOE is in Transmitter mode: – After SIOE sends a byte, ACK_RESP = 1 whenever the external I2C device receives the byte, but that device does NOT assert an ackowledge signal (external device asserted a high on SDA during the acknowledge bit-time). – After SIOE sends a byte, ACK_RESP = 0 whenever the external I2C device receives the byte, and that device DOES assert an ackowledge signal (external device drove a low on SDA during the acknowledge bit-time) Note: If SIOE is in Master-Transmitter mode, and ACK_RESP = 1 due to a Slave-Transmitter not sending an Acknowledge, a STOP condition will not automatically be generated by the SIOE. The STOP condition must be generated with S1CON.STO = 1. 0 SLV R Slave Mode flag SLV = 1 when the SIOE is in Slave mode. SLV = 0 when the SIOE is in Master mode (default).uPSD33xx 104/231 I 2C Data Shift Register (S1DAT) The S1ADR register (Table 53) holds a byte of serial data to be transmitted or it holds a serial byte that has just been received. The MCU may access S1DAT while the SIOE is not in the process of shifting a byte (the INTR flag indicates shifting is complete). While transmitting, bytes are shifted out MSB first, and when receiving, bytes are shifted in MSB first, through the Acknowledge Bit register as shown in Figure 40., page 99. Bus Wait Condition. After the SIOE finishes receiving a byte in Receive mode, or transmitting a byte in Transmit mode, the INTR flag (in S1STA) is set and automatically a wait condition is imposed on the I2C bus (SCL held low by SIOE). In Transmit mode, this wait condition is released as soon as the MCU writes any byte to S1DAT. In Receive mode, the wait condition is released as soon as the MCU reads the S1DAT register. This method allows the user to handle transmit and receive operations within an interrupt service routine. The SIOE will automatically stall the I2C bus at the appropriate time, giving the MCU time to get the next byte ready to transmit or time to read the byte that was just received. Table 53. S1DAT: I2C Data Shift register (SFR DEh, reset value 00h) I 2C Address Register (S1ADR) The S1ADR register (Table 54) holds the 7-bit device address used when the SIOE is operating as a Slave. When the SIOE receives an address from a Master, it will compare this address to the contents of S1ADR, as shown in Figure 40., page 99. If the 7 bits match, the INTR Interrupt flag (in S1STA) is set, and the ADDR Bit (in S1CON) is set. The SIOE cannot modify the contents S1ADR, and S1ADR is not used during Master mode. Table 54. S1ADR: I2C Address register (SFR DFh, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S1DAT[7:0] Details Bit Symbol R/W Function 7:0 S1DAT[7:0] R/W Holds the data byte to be transmitted in Transmit mode, or it holds the data byte received in Receiver mode. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 – Details Bit Symbol R/W Function 7:1 SLA[6:0] R/W Stores desired 7-bit device address, used when SIOE is in Slave mode. 0 – – Not used105/231 uPSD33xx I 2C START Sample Setting (S1SETUP) The S1SETUP register (Table 55) determines how many times an I2C bus START condition will be sampled before the SIOE validates the START condition, giving the SIOE the ability to reject noise or illegal transmissions. Because the minimum duration of an START condition varies with I2C bus speed (fSCL), and also because the uPSD33xx may be operated with a wide variety of frequencies (fOSC), it is necessary to scale the number of samples per START condition based on fOSC and fSCL. In Slave mode, the SIOE recognizes the beginning of a START condition when it detects a '1'-to-'0' transition on the SDA bus line while the SCL line is high (see Figure 39., page 97). The SIOE must then validate the START condition by sampling the bus lines to ensure SDA remains low and SCL remains high for a minimum amount of hold time, tHLDSTA. Once validated, the SIOE begins receiving the address byte that follows the START condition. If the EN_SS Bit (in the S1SETUP Register) is not set, then the SIOE will sample only once after detecting the '1'-to-'0' transition on SDA. This single sample is taken 1/fOSC seconds after the initial 1- to-0 transition was detected. However, more samples should be taken to ensure there is a valid START condition. To take more samples, the SIOE should be initialized such that the EN_SS Bit is set, and a value is written to the SMPL_SET[6:0] field of the S1SETUP Register to specify how many samples to take. The goal is to take a good number of samples during the minimum START condition hold time, tHLDSTA, but no so many samples that the bus will be sampled after tHLDSTA expires. Table 56., page 106 describes the relationship between the contents of S1SETUP and the resulting number of I2C bus samples that SIOE will take after detecting the 1-to-0 transition on SDA of a START condition. Important: Keep in mind that the time between samples is always 1/fOSC. The minimum START condition hold time, tHLDSTA, is different for the three common I2C speed categories per Table 57., page 106. Table 55. S1SETUP: I2C START Condition Sample Setup register (SFR DBh, reset value 00h) Note: 1. Sampling SCL and SDA lines begins after '1'-to-'0' transition on SDA occurred while SCL is high. Time between samples is 1/fOSC. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN_SS SMPL_SET[6:0] Details Bit Symbol R/W Function 7 EN_SS R/W Enable Sample Setup EN_SS = 1 will force the SIOE to sample(1) a START condition on the bus the number of times specified in SMPL_SET[6:0]. EN_SS = 0 means the SIOE will sample(1) a START condition only one time, regardless of the contents of SMPL_SET[6:0]. 6:0 SMPL_SET [6:0] – Sample Setting Specifies the number of bus samples(1) taken during a START condition. See Table 56 for values.uPSD33xx 106/231 Table 56. Number of I2C Bus Samples Taken after 1-to-0 Transition on SDA (START Condition) Table 57. Start Condition Hold Time Note: 1. 833KHz is maximum for uPSD33xx devices. Contents of S1SETUP Resulting value for S1SETUP Resulting Number of Samples Taken After 1-to-0 on SDA Line SS_EN bit SMPL_SET[6:0] 0 XXXXXXXb 00h (default) 1 1 0000000b 80h 1 1 0000001b 81h 2 1 0000010b 82h 3 ... ... ... ... 1 0001011b 8Bh 12 1 0010111b 97h 24 ... ... ... ... 1 1111111b FFh 128 I 2C Bus Speed Range of I2C Clock Speed (fSCL) Minimum START Condition Hold Time (tHLDSTA) Standard Up to 100KHz 4000ns Fast 101KHz to 400KHz 600ns High 401KHz to 833KHz(1) 160ns107/231 uPSD33xx Table 58 provides recommended settings for S1SETUP based on various combinations of fOSC and fSCL. Note that the “Total Sample Period” times in Table 57., page 106 are typically slightly less than the minimum START condition hold time, tHLDSTA for a given I2C bus speed. Important: The SCL bit rate fSCL must first be determined by bits CR[2:0] in the SFR S1CON before a value is chosen for SMPL_SET[6:0] in the SFR S1SETUP. Table 58. S1SETUP Examples for Various I2C Bus Speeds and Oscillator Frequencies Note: 1. Not compatible with High Speed I2C. I 2C Bus Speed, fSCL Parameter Oscillator Frequency, fOSC 6 MHz 12 MHz 24 MHz 33 MHz 40 MHz Standard Recommended S1SETUP Value 93h A7h CFh EEh FFh Number of Samples 20 40 80 111 128 Time Between Samples 166.6ns 83.3ns 41.6ns 30ns 25ns Total Sampled Period 3332ns 3332ns 3332ns 3333ns 3200ns Fast Recommended S1SETUP Value 82h 85h 8Bh 90h 93h Number of Samples 3 6 12 17 20 Time Between Samples 166.6ns 83.3ns 41.6ns 30ns 25ns Total Sampled Period 500ns 500ns 500ns 510ns 500ns High Recommended S1SETUP Value (Note 1) 80 82 83 84 Number of Samples - 1 3 4 5 Time Between Samples - 83.3ns 41.6ns 30ns 25ns Total Sampled Period - 83.3 125ns 120ns 125nsuPSD33xx 108/231 I 2C Operating Sequences The following pseudo-code explains hardware control for these I2C functions on the uPSD33xx: – Initialize the Interface – Function as Master-Transmitter – Function as Master-Receiver – Function as Slave-Transmitter – Function as Slave-Receiver – Interrupt Service Routine Full C code drivers for the uPSD33xx I2C interface, and other interfaces are available from the web at www.st.com\psm. Initialization after a uPSD33xx reset Ensure pins P3.6 and P3.7 are GPIO inputs – SFR P3.7 = 1 and SFR P3.6 = 1 Configure pins P3.6 and P3.7 as I2C – SFR P3SFS.6 = 1 and P3SFS.7 = 1 Set I2C clock prescaler to determine fSCL – SFR S1CON.CR[2:0] = desired SCL freq. Set bus START condition sampling – SFR S1SETUP[7:0] = number of samples Enable individual I2C interrupt and set priority – SFR IEA.I2C = 1 – SFR IPA.I2C = 1 if high priority is desired Set the Device address for Slave mode – SFR S1ADR = XXh, desired address Enable SIOE (as Slave) to return an ACK signal – SFR S1CON.AA = 1 Master-Transmitter Disable all interrupts – SFR IE.EA = 0 Set pointer to global data xmit buffer, set count – *xmit_buf = *pointer to data – buf_length = number of bytes to xmit Set global variables to indicate Master-Xmitter – I2C_master = 1, I2C_xmitter = 1 Disable Master from returning an ACK – SFR S1CON.AA = 0 Enable I2C SIOE – SFR S1CON.INI1 = 1 Transmit Address and R/W bit = 0 to Slave – Is bus not busy? (SFR S1STA.BBUSY = 0?) – SFR S1DAT[7:0] = Load Slave Address & FEh – SFR S1CON.STA = 1, send START on bus Enable All Interrupts and go do something else – SFR IE.EA = 1 Master-Receiver Disable all interrupts – SFR IE.EA = 0 Set pointer to global data recv buffer, set count – *recv_buf = *pointer to data – buf_length = number of bytes to recv Set global variables to indicate Master-Xmitter – I2C_master = 1, I2C_xmitter = 0 Disable Master from returning an ACK – SFR S1CON.AA = 0 Enable I2C SIOE – SFR S1CON.INI1 = 1 Transmit Address and R/W bit = 1 to Slave – Is bus not busy? (SFR S1STA.BBUSY = 0?) – SFR S1DAT[7:0] = Load Slave Address # 01h – SFR S1CON.STA = 1, send START on bus Enable All Interrupts and go do something else – SFR IE.EA = 1109/231 uPSD33xx Slave-Transmitter Disable all interrupts – SFR IE.EA = 0 Set pointer to global data xmit buffer, set count – *xmit_buf = *pointer to data – buf_length = number of bytes to xmit Set global variables to indicate Master-Xmitter – I2C_master = 0, I2C_xmitter = 1 Enable SIOE – SFR S1CON.INI1 = 1 Prepare to Xmit first data byte – SFR S1DAT[7:0] = xmit_buf[0] Enable All Interrupts and go do something else – SFR IE.EA = 1 Slave-Receiver Disable all interrupts – SFR IE.EA = 0 Set pointer to global data recv buffer, set count – *recv_buf = *pointer to data – buf_length = number of bytes to recv Set global variables to indicate Master-Xmitter – I2C_master = 0, I2C_xmitter = 0 Enable SIOE – SFR S1CON.INI1 = 1 Enable All Interrupts and go do something else – SFR IE.EA = 1 Interrupt Service Routine (ISR). A typical I2C interrupt service routine would handle a interrupt for any of the four combinations of Master/Slave and Transmitter/Receiver. In the example routines above, the firmware sets global variables, I2C_master and I2C_xmitter, before enabling interrupts. These flags tell the ISR which one of the four cases to process. Following is pseudo-code for high-level steps in the I2C ISR: Begin I2C ISR : Clear I2C interrupt flag: – S1STA.INTR = 0 Read status of SIOE, put in to variable, status – status = S1STA Read global variables that determine the mode – mode <= (I2C_master, I2C_slave) If mode is Master-Transmitter Bus Arbitration lost? (status.BLOST=1?) If Yes, Arbitration was lost: – S1DAT = dummy, write to release bus – Exit ISR, SIOE will switch to Slave Recv mode If No, Arbitration was not lost, continue: ACK recvd from Slave? (status.ACK_RESP=0?) If No, an ACK was not received: – S1CON.STO = 1, set STOP bus condition – – S1DAT = dummy, write to release bus – Exit ISR If Yes, ACK was received, then continue: – S1DAT = xmit_buf[buffer_index], transmit byte Was that the last byte of data to transmit? If No, it was not the last byte, then: – Exit ISR, transmit next byte on next interrupt If Yes, it was the last byte, then: – S1CON.STO = 1, set STOP bus condition – S1DAT = dummy, write to release bus – Exit ISRuPSD33xx 110/231 Else If mode is Master-Receiver: Bus Arbitration lost? (status.BLOST=1?) If Yes, Arbitration was lost: – S1DAT = dummy, write to release bus – Exit ISR, SIOE will switch to Slave Recv mode If No, Aribitration was not lost, continue: Is this Interrupt from sending an address to Slave, or is it from receiving a data byte from Slave? If its from sending Slave address, goto A: If its from receiving Slave data, goto B: A: (Interrupt is from Master sending addr to Slave) ACK recvd from Slave? (status.ACK_RESP=0?) If No, an ACK was not received: – S1CON.STO = 1, set STOP condition – dummy = S1DAT, read to release bus – Exit ISR If Yes, ACK was received, then continue: – dummy = S1DAT, read to release bus Does Master want to receive just one data byte? If Yes, do not allow Master to ACK on next interrupt: – Exit ISR, now ready to recv one byte from Slv If No, Master can ACK next byte from Slv – S1CON.AA = 1, allow Master to send ACK – Exit ISR, now ready to recv data from Slave B: (Interrupt is from Master recving data from Slv) – recv_buf[buffer_index] = S1DAT, read byte Is this the last data byte to receive from Slave? If Yes, tell Slave to stop transmitting: – S1CON.STO = 1, set STOP bus condition – Exit ISR, finished receiving data from Slave If No, continue: Is this the next to last byte to receive from Slave? If this is the next to last byte, do not allow Master to ACK on next interrupt. – S1CON.AA = 0, don’t let Master return ACK – Exit ISR, now ready to recv last byte from Slv If this is not next to last byte, let Master send ACK to Slave – Exit ISR, ready to recv more bytes from Slave Else If mode is Slave-Transmitter: Is this Intr from SIOE detecting a STOP on bus? If Yes, a STOP was detected: – S1DAT = dummy, write to release bus – Exit ISR, Master needs no more data bytes If No, a STOP was not detected, continue: ACK recvd from Master? (status.ACK_RESP=0?) If No, an ACK was not received: – S1DAT = dummy, write to release bus – Exit ISR, Master needs no more data bytes If Yes, ACK was received, then continue: – S1DAT = xmit_buf[buffer_index], transmit byte – Exit ISR, transmit next byte on next interrupt111/231 uPSD33xx Else If mode is Slave-Receiver: Is this Intr from SIOE detecting a STOP on bus? If Yes, a STOP was detected: – recv_buf[buffer_index] = S1DAT, get last byte – Exit ISR, Master has sent last byte If No, a STOP was not detected, continue: Determine if this Interrupt is from receiving an address or a data byte from a Master. Is (S1CON.ADDR = 1 and S1CON.AA =1)? If No, intr is from receiving data, goto C: If Yes, intr is from an address, continue: – slave_is_adressed = 1, local variable set true – S1CON.ADDR = 0, clear address match flag Determine if R/W bit indicates transmit or receive. Does status.TX_MODE = 1? If Yes, Master wants transmit mode – Exit ISR, indicate Master wants Slv-Xmit mode If No, Master wants Slave-Recv mode – dummy = S1DAT, read taran se bueuPSD33xx 112/231 SPI (SYNCHRONOUS PERIPHERAL INTERFACE) uPSD33xx devices support one serial SPI interface in Master Mode only. This is a three- or fourwire synchronous communication channel, capable of full-duplex operation on 8-bit serial data transfers. The four SPI bus signals are: ■ SPIRxD Pin P1.5 or P4.5 receives data from the Slave SPI device to the uPSD33xx ■ SPITxD Pin P1.6 or P4.6 transmits data from the uPSD33xx to the Slave SPI device ■ SPICLK Pin P1.4 or P4.4 clock is generated from the uPSD33xx to the SPI Slave device ■ SPISEL Pin P1.7 or P4.7 selects the signal from the uPSD33xx to an individual Slave SPI device This SPI interface supports single-Master/multiple-Slave connections. Multiple-Master connections are not directly supported by the uPSD33xx (no internal logic for collision detection). If more than one Slave device is required, the SPISEL signal may be generated from uPSD33xx GPIO outputs (one for each Slave) or from the PLD outputs of the PSD Module. Figure 41. illustrates three examples of SPI device connections using the uPSD33xx: ■ Single-Master/Single-Slave with SPISEL ■ Single-Master/Single-Slave without SPISEL ■ Single-Master/Multiple-Slave without SPISEL Figure 41. SPI Device Connection Examples SPI Bus SPI Bus SPI Bus SPITxD SPIRxD uPSD33xx SPI Master SPI Slave SPICLK Device SPISEL AI07853b MOSI MISO SCLK Single-Master/Single-Slave, with SPISEL Single-Master/Single-Slave, without SPISEL Single-Master/Multiple-Slave, without SPISEL SS SPI Slave Device MOSI MISO SCLK SS SPI Slave Device MOSI MISO SCLK SS SS SPITxD SPIRxD uPSD33xx SPI Master SPI Slave SPICLK Device SPITxD SPIRxD uPSD33xx SPI Master SPICLK GPIO or PLD GPIO or PLD MOSI MISO SCLK113/231 uPSD33xx SPI Bus Features and Communication Flow The SPICLK signal is a gated clock generated from the uPSD33xx (Master) and regulates the flow of data bits. The Master may transmit at a variety of baud rates, and the SPICLK signal will clock one period for each bit of transmitted data. Data is shifted on one edge of SPICLK and sampled on the opposite edge. The SPITxD signal is generated by the Master and received by the Slave device. The SPIRxD signal is generated by the Slave device and received by the Master. There may be no more than one Slave device transmitting data on SPIRxD at any given time in a multi-Slave configuration. Slave selection is accomplished when a Slave’s “Slave Select” (SS) input is permanently grounded or asserted active-low by a Master device. Slave devices that are not selected do not interfere with SPI activities. Slave devices ignore SPICLK and keep their MISO output pins in high-impedance state when not selected. The SPI specification allows a selection of clock polarity and clock phase with respect to data. The uPSD33xx supports the choice of clock polarity, but it does not support the choice of clock phase (phase is fixed at what is typically known as CPHA = 1). See Figure 43. and Figure 44., page 114 for SPI data and clock relationships. Referring to these figures (43 and 44), when the phase mode is defined as such (fixed at CPHA =1), in a new SPI data frame, the Master device begins driving the first data bit on SPITxD at the very first edge of the first clock period of SPICLK. The Slave device will use this first clock edge as a transmission start indicator, and therefore the Slave’s Slave Select input signal may remain grounded in a single-Master/single-Slave configuration (which means the user does not have to use the SPISEL signal from uPSD33xx in this case). The SPI specification does not specify high-level protocol for data exchange, only low-level bit-serial transfers are defined. Full-Duplex Operation When an SPI transfer occurs, 8 bits of data are shifted out on one pin while a different 8 bits of data are simultaneously shifted in on a second pin. Another way to view this transfer is that an 8-bit shift register in the Master and another 8-bit shift register in the Slave are connected as a circular 16-bit shift register. When a transfer occurs, this distributed shift register is shifted 8 bit positions; thus, the data in the Master and Slave devices are effectively exchanged (see Figure 42.). Bus-Level Activity Figure 43. details an SPI receive operation (with respect to bus Master) and Figure 44. details an SPI transmit operation. Also shown are internal flags available to firmware to manage data flow. These flags are accessed through a number of SFRs. Note: The uPSD33xx SPI interface SFRs allow the choice of transmitting the most significant bit (MSB) of a byte first, or the least significant bit (LSB) first. The same bit-order applies to data reception. Figures 43 and 44 illustrate shifting the LSB first. Figure 42. SPI Full-Duplex Data Exchange SPI Bus Master Device Slave Device AI10485 SS SPITxD SPIRxD Baud Rate Generator 8-Bit Shift Register 8-Bit Shift Register SPICLK MOSI MISO SCLKuPSD33xx 114/231 Figure 43. SPI Receive Operation Example Figure 44. SPI Transmit Operation Example Bit7 SPICLK (SPO=0) SPICLK (SPO=1) SPIRXD Bit0 Bit1 Bit7 Bit0 Bit1 Bit7 1 frame RISF RORIS BUSY SPIINTR SPIRDR Full interrupt requested Interrupt handler read data in SPIRDR SPIRDR Full interrupt requested Transmit End interrupt requested AI07855 Bit0 SPICLK (SPO=0) SPICLK (SPO=1) SPITXD Bit1 Bit7 Bit0 Bit1 Bit7 1 frame TISF TEISF BUSY SPIINTR SPITDR Empty interrupt requested Interrupt handler write data in TDR SPITDR Empty interrupt requested Transmit End interrupt requested SPISEL AI07854115/231 uPSD33xx SPI SFR Registers Six SFR registers control the SPI interface: ■ SPICON0 (Table 59., page 117) for interface control ■ SPICON1 (Table 60., page 118) for interrupt control ■ SPITDR (SFR D4h, Write only) holds byte to transmit ■ SPIRDR (SFR D5h, Read only) holds byte received ■ SPICLKD (Table 61., page 118) for clock divider ■ SPISTAT (Table 62., page 119) holds interface status The SPI interface functional block diagram (Figure 45.) shows these six SFRs. Both the transmit and receive data paths are double-buffered, meaning that continuous transmitting or receiving (back-toback transfer) is possible by reading from SPIRDR or writing data to SPITDR while shifting is taking place. There are a number of flags in the SPISTAT register that indicate when it is full or empty to assist the 8032 MCU in data flow management. When enabled, these status flags will cause an interrupt to the MCU. Figure 45. SPI Interface, Master Mode Only SPITDR - TRANSMIT REGISTER SPITxD / P1.6 or P4.6 TIMING AND CONTROL (fOSC) INTR to 8032 SPIRDR - RECEIVE REGISTER 8-bit SHIFT REGISTER 8 8 8 8 SPIRxD / P1.5 or P4.5 SPICON0, SPICON1 - CONTROL REGISTERS 8 SPISTAT - STATUS REGISTER 8 8032 MCU DATA BUS CLOCK GENERATE SPISEL / P1.7 or P4.7 CLOCK SPICLK / P1.4 or P4.4 DIVIDE ÷1 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 SPICLKD - DIVIDE SELECT 8 PERIPH_CLK AI10486uPSD33xx 116/231 SPI Configuration The SPI interface is reset by the MCU reset, and firmware needs to initialize the SFRs SPICON0, SPICON1, and SPICLKD to define several operation parameters. The SPO Bit in SPICON0 determines the clock polarity. When SPO is set to '0,' a data bit is transmitted on SPITxD from one rising edge of SPICLK to the next and is guaranteed to be valid during the falling edge of SPICLK. When SPO is set to '1,' a data bit is transmitted on SPITxD from one falling edge of SPICLK to the next and is guaranteed to be valid during the rising edge of SPICLK. The uPSD33xx will sample received data on the appropriate edge of SPICLK as determined by SPO. The effect of the SPO Bit can be seen in Figure 43. and Figure 44., page 114. The FLSB Bit in SPICON0 determines the bit order while transmitting and receiving the 8-bit data. When FLSB is '0,' the 8-bit data is transferred in order from MSB (first) to LSB (last). When FLSB Bit is set to '1,' the data is transferred in order from LSB (first) to MSB (last). The clock signal generated on SPICLK is derived from the internal PERIPH_CLK signal. PERIPH_CLK always operates at the frequency, fOSC, and runs constantly except when stopped in MCU Power Down mode. SPICLK is a result of dividing PERIPH_CLK by a sum of different divisors selected by the value contained in the SPICLKD register. The default value in SPICLKD after a reset divides PERIPH_CLK by a factor of 4. The bits in SPICLKD can be set to provide resulting divisor values in of sums of multiples of 4, such as 4, 8, 12, 16, 20, all the way up to 252. For example, if SPICLKD contains 0x24, SPICLK has the frequency of PERIH_CLK divided by 36 decimal. The SPICLK frequency must be set low enough to allow the MCU time to read received data bytes without loosing data. This is dependent upon many things, including the crystal frequency of the MCU and the efficiency of the SPI firmware. Dynamic Control At runtime, bits in registers SPICON0, SPICON1, and SPISTAT are managed by firmware for dynamic control over the SPI interface. The bits Transmitter Enable (TE) and Receiver Enable (RE) when set will allow transmitting and receiving respectively. If TE is disabled, both transmitting and receiving are disabled because SPICLK is driven to constant output logic ‘0’ (when SPO = 0) or logic '1' (when SPO = 1). When the SSEL Bit is set, the SPISEL pin will drive to logic '0' (active) to select a connected slave device at the appropriate time before the first data bit of a byte is transmitted, and SPISEL will automatically return to logic '1' (inactive) after transmitting the eight bit of data, as shown in Figure 44., page 114. SPISEL will continue to automatically toggle this way for each byte data transmission while the SSEL bit is set by firmware. When the SSEL Bit is cleared, the SPISEL pin will drive to constant logic '1' and stay that way (after a transmission in progress completes). The Interrupt Enable Bits (TEIE, RORIE,TIE, and RIE) when set, will allow an SPI interrupt to be generated to the MCU upon the occurrence of the condition enabled by these bits. Firmware must read the four corresponding flags in the SPISTAT register to determine the specific cause of interrupt. These flags are automatically cleared when firmware reads the SPISTAT register.117/231 uPSD33xx Table 59. SPICON0: Control Register 0 (SFR D6h, Reset Value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – TE RE SPIEN SSEL FLSB SBO – Details Bit Symbol R/W Definition 7 – – Reserved 6 TE RW Transmitter Enable 0 = Transmitter is disabled 1 = Transmitter is enabled 5 RE RW Receiver Enable 0 = Receiver is disabled 1 = Receiver is enabled 4 SPIEN RW SPI Enable 0 = Entire SPI Interface is disabled 1 = Entire SPI Interface is enabled 3 SSEL RW Slave Selection 0 = SPISEL output pin is constant logic '1' (slave device not selected) 1 = SPISEL output pin is logic '0' (slave device is selected) during data transfers 2 FLSB RW First LSB 0 = Transfer the most significant bit (MSB) first 1 = Transfer the least significant bit (LSB) first 1 SPO – Sampling Polarity 0 = Sample transfer data at the falling edge of clock (SPICLK is '0' when idle) 1 = Sample transfer data at the rising edge of clock (SPICLK is '1' when idle) 0 – – ReserveduPSD33xx 118/231 Table 60. SPICON1: SPI Interface Control Register 1 (SFR D7h, Reset Value 00h) Table 61. SPICLKD: SPI Prescaler (Clock Divider) Register (SFR D2h, Reset Value 04h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – – TEIE RORIE TIE RIE Details Bit Symbol R/W Definition 7-4 – – Reserved 3 TEIE RW Transmission End Interrupt Enable 0 = Disable Interrupt for Transmission End 1 = Enable Interrupt for Transmission End 2 RORIE RW Receive Overrun Interrupt Enable 0 = Disable Interrupt for Receive Overrun 1 = Enable Interrupt for Receive Overrun 1 TIE RW Transmission Interrupt Enable 0 = Disable Interrupt for SPITDR empty 1 = Enable Interrupt for SPITDR empty 0 RIE RW Reception Interrupt Enable 0 = Disable Interrupt for SPIRDR full 1 = Enable Interrupt for SPIRDR full Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DIV128 DIV64 DIV32 DIV16 DIV8 DIV4 – – Details Bit Symbol R/W Definition 7 DIV128 RW 0 = No division 1 = Divide fOSC clock by 128 6 DIV64 RW 0 = No division 1 = Divide fOSC clock by 64 5 DIV32 RW 0 = No division 1 = Divide fOSC clock by 32 4 DIV16 RW 0 = No division 1 = Divide fOSC clock by 16 3 DIV8 RW 0 = No division 1 = Divide fOSC clock by 8 2 DIV4 RW 0 = No division 1 = Divide fOSC clock by 4 1-0 Not Used –119/231 uPSD33xx Table 62. SPISTAT: SPI Interface Status Register (SFR D3h, Reset Value 02h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – BUSY TEISF RORISF TISF RISF Details Bit Symbol R/W Definition 7-5 – – Reserved 4 BUSY R SPI Busy 0 = Transmit or Receive is completed 1 = Transmit or Receive is in process 3 TEISF R Transmission End Interrupt Source flag 0 = Automatically resets to '0' when firmware reads this register 1 = Automatically sets to '1' when transmission end occurs 2 RORISF R Receive Overrun Interrupt Source flag 0 = Automatically resets to '0' when firmware reads this register 1 = Automatically sets to '1' when receive overrun occurs 1 TISF R Transfer Interrupt Source flag 0 = Automatically resets to '0' when SPITDR is full (just after the SPITDR is written) 1 = Automatically sets to '1' when SPITDR is empty (just after byte loads from SPITDR into SPI shift register) 0 RISF R Receive Interrupt Source flag 0 = Automatically resets to '0' when SPIRDR is empty (after the SPIRDR is read) 1 = Automatically sets to '1' when SPIRDR is fulluPSD33xx 120/231 ANALOG-TO-DIGITAL CONVERTOR (ADC) The ADC unit in the uPSD33xx is a SAR type ADC with an SAR register, an auto-zero comparator and three internal DACs. The unit has 8 input channels with 10-bit resolution. The A/D converter has its own VREF input (80-pin package only), which specifies the voltage reference for the A/D operations. The analog to digital converter (A/D) allows conversion of an analog input to a corresponding 10-bit digital value. The A/D module has eight analog inputs (P1.0 through P1.7) to an 8x1 multiplexor. One ADC channel is selected by the bits in the configuration register. The converter generates a 10-bits result via successive approximation. The analog supply voltage is connected to the VREF input, which powers the resistance ladder in the A/D module. The A/D module has 3 registers, the control register ACON, the A/D result register ADAT0, and the second A/D result register ADAT1. The ADAT0 Register stores Bits 0.. 7 of the converter output, Bits 8.. 9 are stored in Bits 0..1 of the ADAT1 Register. The ACON Register controls the operation of the A/D converter module. Three of the bits in the ACON Register select the analog channel inputs, and the remaining bits control the converter operation. ADC channel pin input is enabled by setting the corresponding bit in the P1SFS0 and P1SFS1 Registers to '1' and the channel select bits in the ACON Register. The ADC reference clock (ADCCLK) is generated from fOSC divided by the divider in the ADCPS Register. The ADC operates within a range of 2 to 16MHz, with typical ADCCLK frequency at 8MHz. The conversion time is 4µs typical at 8MHz. The processing of conversion starts when the Start Bit ADST is set to '1.' After one cycle, it is cleared by hardware. The ADC is monotonic with no missing codes. Measurement is by continuous conversion of the analog input. The ADAT Register contains the results of the A/D conversion. When conversion is complete, the result is loaded into the ADAT. The A/D Conversion Status Bit ADSF is set to '1.' The block diagram of the A/D module is shown in Figure 46. The A/D status bit ADSF is set automatically when A/D conversion is completed and cleared when A/D conversion is in process. In addition, the ADC unit sets the interrupt flag in the ACON Register after a conversion is complete (if AINTEN is set to '1'). The ADC interrupts the CPU when the enable bit AINTEN is set. Port 1 ADC Channel Selects The P1SFS0 and P1SFS1 Registers control the selection of the Port 1 pin functions. When the P1SFS0 Bit is '0,' the pin functions as a GPIO. When bits are set to '1,' the pins are configured as alternate functions. A new P1SFS1 Register selects which of the alternate functions is enabled. The ADC channel is enabled when the bit in P1SFS1 is set to '1.' Note: In the 52-pin package, there is no individual VREF pin because VREF is combined with AVCC pin. Figure 46. 10-Bit ADC ANALOG MUX SELECT ADC OUT - 10 BITS ACON REG ADAT 0 REG CONTROL 10-BIT SAR ADC ADAT1 REG ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 AVREF P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 AVREF AI07856121/231 uPSD33xx Table 63. ACON Register (SFR 97h, Reset Value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AINTF AINTEN ADEN ADS2 ADS1 ADS0 ADST ADSF Details Bit Symbol Function 7 AINTF ADC Interrupt flag. This bit must be cleared with software. 0 = No interrupt request 1 = The AINTF flag is set when ADSF goes from '0' to '1.' Interrupts CPU when both AINTF and AINTEN are set to '1.' 6 AINTEN ADC Interrupt Enable 0 = ADC interrupt is disabled 1 = ADC interrupt is enabled 5 ADEN ADC Enable Bit 0 = ADC shut off and consumes no operating current 1 = Enable ADC. After ADC is enabled, 16ms of calibration is needed before ADST Bit is set. 4.. 2 ADS2.. 0 Analog channel Select 000 Select channel 0 (P1.0) 001 Select channel 0 (P1.1) 010 Select channel 0 (P1.2) 011 Select channel 0 (P1.3) 101 Select channel 0 (P1.5) 110 Select channel 0 (P1.6) 111 Select channel 0 (P1.7) 1 ADST ADC Start Bit 0 = Force to zero 1 = Start ADC, then after one cycle, the bit is cleared to '0.' 0 ADSF ADC Status Bit 0 = ADC conversion is not completed 1 = ADC conversion is completed. The bit can also be cleared with software.uPSD33xx 122/231 Table 64. ADCPS Register Details (SFR 94h, Reset Value 00h) Table 65. ADAT0 Register (SFR 95H, Reset Value 00h) Table 66. ADAT1 Register (SFR 96h, Reset Value 00h) Bit Symbol Function 7:4 – Reserved 3 ADCCE ADC Conversion Reference Clock Enable 0 = ADC reference clock is disabled (default) 1 = ADC reference clock is enabled 2:0 ADCPS[2:0] ADC Reference Clock PreScaler Only three Prescaler values are allowed: ADCPS[2:0] = 0, for fOSC frequency 16MHz or less. Resulting ADC clock is fOSC. ADCPS[2:0] = 1, for fOSC frequency 32MHz or less. Resulting ADC clock is fOSC/2. ADCPS[2:0] = 2, for fOSC frequency 32MHz > 40MHz. Resulting ADC clock is fOSC/4. Bit Symbol Function 7:0 – Store ADC output, Bit 7 - 0 Bit Symbol Function 7:2 – Reserved 1.. 0 – Store ADC output, Bit 9, 8123/231 uPSD33xx PROGRAMMABLE COUNTER ARRAY (PCA) WITH PWM There are two Programmable Counter Array blocks (PCA0 and PCA1) in the uPSD33xx. A PCA block consists of a 16-bit up-counter, which is shared by three TCM (Timer Counter Module). A TCM can be programmed to perform one of the following four functions: 1. Capture Mode: capture counter values by external input signals 2. Timer Mode 3. Toggle Output Mode 4. PWM Mode: fixed frequency (8-bit or 16-bit), programmable frequency (8-bit only) PCA Block The 16-bit Up-Counter in the PCA block is a freerunning counter (except in PWM Mode with programmable frequency). The Counter has a choice of clock input: from an external pin, Timer 0 Overflow, or PCA Clock. A PCA block has 3 Timer Counter Modules (TCM) which share the 16-bit Counter output. The TCM can be configured to capture or compare counter value, generate a toggling output, or PWM functions. Except for the PWM function, the other TCM functions can generate an interrupt when an event occurs. Every TCM is connected to a port pin in Port 4; the TCM pin can be configured as an event input, a PWMs, a Toggle Output, or as External Clock Input. The pins are general I/O pins when not assigned to the TCM. The TCM operation is configured by Control registers and Capture/Compare registers. Table 67., page 124 lists the SFR registers in the PCA blocks. Figure 47. PCA0 Block Diagram TIMER0 OVERFLOW P4.3/ECI PCACH0 8-bit PCACL0 8-bit CLKSEL1 IDLE MODE (From CPU) OVF0 INT EOVFI TCM0 TCM1 TCM2 PWM FREQ COMPARE P4.0/CEX0 P4.1/CEX1 P4.2/CEX2 16-bit up Timer/Counter CLKSEL0 PCAIDLE PCA0CLK CLEAR COUNTER EN_PCA EN_ALL AI07857uPSD33xx 124/231 Table 67. PCA0 and PCA1 Registers SFR Address Register Name RW Register Function PCA0 PCA1 PCA0 PCA1 A2 BA PCACL0 PCACL1 RW The low 8 bits of PCA 16-bit counter. A3 BB PCACH0 PCACH1 RW The high 8 bits of PCA 16-bit counter. A4 BC PCACON0 PCACON1 RW Control Register – Enable PCA, Timer Overflow flag , PCA Idle Mode, and Select clock source. A5 A5 PCASTA N/A RW Status Register, Interrupt Status flags – Common for both PCA Block 0 and 1. A9, AA, AB BD, BE, BF TCMMODE0 TCMMODE1 TCMMODE2 TCMMODE3 TCMMODE4 TCMMODE5 RW TCM Mode – Capture, Compare, and Toggle Enable Interrupts – PWM Mode Select. AC AD C1 C2 CAPCOML0 CAPCOMH0 CAPCOML3 CAPCOMH3 RW Capture/Compare registers of TCM0 AF B1 C3 C4 CAPCOML1 CAPCOMH1 CAPCOML4 CAPCOMH4 RW Capture/Compare registers of TCM1 B2 B3 C5 C6 CAPCOML2 CAPCOMH2 CAPCOML5 CAPCOMH5 RW Capture/Compare registers of TCM2 B4 C7 PWMF0 PWMF1 RW The 8-bit register to program the PWM frequency. This register is used for programmable, 8-bit PWM Mode only. FB FC CCON2 CCON3 RW Specify the pre-scaler value of PCA0 or PCA1 clock input125/231 uPSD33xx PCA Clock Selection The clock input to the 16-bit up counter in the PCA block is user-programmable. The three clock sources are: – PCA Prescaler Clock (PCA0CLK, PCA1CLK) – Timer 0 Overflow – External Clock, Pin P4.3 or P4.7 The clock source is selected in the configuration register PCACON. The Prescaler output clock PCACLK is the fOSC divided by the divisor which is specified in the CCON2 or CCON3 Register. When External Clock is selected, the maximum clock frequency should not exceed fOSC/4. Table 68. CCON2 Register Bit Definition (SFR 0FBh, Reset Value 10h) Table 69. CCON3 Register Bit Definition (SFR 0FCh, Reset Value 10h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – PCA0CE PCA0PS3 PCA0PS2 PCA0PS1 PCA0PS0 Details Bit Symbol R/W Definition 4 PCA0CE R/W PCA0 Clock Enable 0 = PCA0CLK is disabled 1 = PCA0CLK is enabled (default) 3:0 PCA0PS [3:0] R/W PCA0 Prescaler fPCA0CLK = fOSC / (2 ^ PCA0PS[3:0]) Divisor range: 1, 2, 4, 8, 16... 16384, 32768 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – – – PCA1CE PCA1PS3 PCA1PS2 PCA1PS1 PCA1PS0 Details Bit Symbol R/W Definition 4 PCA1CE R/W PCA1 Clock Enable 0 = PCA1CLK is disabled 1 = PCA1CLK is enabled (default) 3:0 PCA1PS [3:0] R/W PCA1 Prescaler fPCA1CLK = fOSC / (2 ^ PCA1PS[3:0]) Divisor range: 1, 2, 4, 8, 16... 16384, 32768uPSD33xx 126/231 Operation of TCM Modes Each of the TCM in a PCA block supports four modes of operation. However, an exception is when the TCM is configured in PWM Mode with programmable frequency. In this mode, all TCM in a PCA block must be configured in the same mode or left to be not used. Capture Mode The CAPCOM registers in the TCM are loaded with the counter values when an external pin input changes state. The user can configure the counter value to be loaded by positive edge, negative edge or any transition of the input signal. At loading, the TCM can generate an interrupt if it is enabled. Timer Mode The TCM modules can be configured as software timers by enable the comparator. The user writes a value to the CAPCOM registers, which is then compared with the 16-bit counter. If there is a match, an interrupt can be generated to CPU. Toggle Mode In this mode, the user writes a value to the TCM's CAPCOM registers and enables the comparator. When there is a match with the Counter output, the output of the TCM pin toggles. This mode is a simple extension of the Timer Mode. PWM Mode - (X8), Fixed Frequency In this mode, one or all the TCM's can be configured to have a fixed frequency PWM output on the port pins. The PWM frequency depends on when the low byte of the Counter overflows (modulo 256). The duty cycle of each TCM module can be specified in the CAPCOMHn Register. When the PCA_Counter_L value is equal to or greater than the value in CAPCOMHn, the PWM output is switched to a high state. When the PCA_Counter_L Register overflows, the content in CAPCOMHn is loaded to CAPCOMLn and a new PWM pulse starts. Figure 48. Timer Mode Note: m = 0: n = 0, 1, or 2 m = 1: n = 3, 4, or 5 MATCH_TIMER INTR 0 0 0 TCMMODEn ENABLE 8 8 MATCH PCASTA CAPCOMLn PCACHm PCACLm 16-bit COMPARATOR CAPCOMHn INTFn 0 0 16-bit up Timer/Counter 8 8 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0 RESET WRITE to CAPCOMHn WRITE to CAPCOMLn 1 0 EN_FLAG C D AI07858127/231 uPSD33xx Figure 49. PWM Mode - (X8), Fixed Frequency Note: m = 0: n = 0, 1, or 2 m = 1: n = 3, 4, or 5 CAPCOMHn OVERFLOW ENABLE 8 PCACLm 8 CAPCOMLn 8-bit COMPARATORn CEXn MATCH S R Q Q SET CLR 0 0 TCMMODEn 0 0 0 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0 AI07859uPSD33xx 128/231 PWM Mode - (X8), Programmable Frequency In this mode, the PWM frequency is not determined by the overflow of the low byte of the Counter. Instead, the frequency is determined by the PWMFm Register. The user can load a value in the PWMFm Register, which is then compared to the low byte of the Counter. If there is a match, the Counter is cleared and the Load registers (PWMFm, CAPCOMHn) are re-loaded for the next PWM pulse. There is only one PWMFm Register which serves all 3 TCM in a PCA block. If one of the TCM modules is operating in this mode, the other modules in the PCA must be configured to the same mode or left not to be used. The duty cycle of the PWM can be specified in the CAPCOMHn Register as in the PWM with fixed frequency mode. Different TCM modules can have their own duty cycle. Note: The value in the Frequency Register (PWMFm) must be larger than the duty cycle register (CAPCOM). Figure 50. PWM Mode - (X8) Programmable Frequency Note: m = 0: n = 0, 1, or 2 m = 1: n = 3, 4, or 5 CLR PCACHm PWM FREQ COMPARE PWMFm = PCACLm PCACLm CAPCOMHn ENABLE ENABLE CEXn 8 8 PWMFm 8-bit COMPARATORm 8-bit COMPARATORn CAPCOMLn MATCH S R Q Q SET CLR 8 0 0 TCMMODEn 0 0 0 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0 AI07860129/231 uPSD33xx PWM Mode - Fixed Frequency, 16-bit The operation of the 16-bit PWM is the same as the 8-bit PWM with fixed frequency. In this mode, one or all the TCM can be configured to have a fixed frequency PWM output on the port pins. The PWM frequency is depending on the clock input frequency to the 16-bit Counter. The duty cycle of each TCM module can be specified in the CAPCOMHn and CAPCOMLn Registers. When the 16- bit PCA_Counter is equal or greater than the values in registers CAPCOMHn and CAPCOMLn, the PWM output is switched to a high state. When the PCA_Counter overflows, CEXn is asserted low. PWM Mode - Fixed Frequency, 10-bit The 10-bit PWM logic requires that all 3 TCMs in PCA0 or PCA1 operate in the same 10-bit PWM mode. The 10-bit PWM operates in a similar manner as the 16-bit PWM, except the PCACHm and PCACLm counters are reconfigured as 10-bit counters. The CAPCOMHn and CAPCOMLn Registers become 10-bit registers. PWM duty cycle of each TCM module can be specified in the 10-bit CAPCOMHn and CAPCOMLn Registers. When the 10-bit PCA counter is equal or greater than the values in the 10-bit registers CAPCOMHn and CAPCOMLn, the PWM output switches to a high state. When the 10-bit PCA counter overflows, the PWM pin is switched to a logic low and starts the next PWM pulse. The most-significant 6 bits in the PCACHm counter and CAPCOMH Register are “Don’t cares” and have no effect on the PWM generation. Writing to Capture/Compare Registers When writing a 16-bit value to the PCA Capture/ Compare registers, the low byte should always be written first. Writing to CAPCOMLn clears the E_COMP Bit to '0'; writing to CAPCOMHn sets E_COMP to '1' the largest duty cycle is 100% (CAPCOMHn CAPCOMLn = 0x0000), and the smallest duty cycle is 0.0015% (CAPCOMHn CAPCOMLn = 0xFFFF). A 0% duty cycle may be generated by clearing the E_COMP Bit to ‘0’. Control Register Bit Definition Each PCA has its own PCA_CONFIGn, and each module within the PCA block has its own TCM_Mode Register which defines the operation of that module (see Table 70., page 129 through Table 71., page 130). There is one PCA_STATUS Register that covers both PCA0 and PCA1 (see Table 72., page 131). Table 70. PCA0 Control Register PCACON0 (SFR 0A4h, Reset Value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN-ALL EN_PCA EOVFI PCAIDLE – – CLK_SEL[1:0] Details Bit Symbol Function 7 EN-ALL 0 = No impact on TCM modules 1 = Enable both PCA counters simultaneously (override the EN_PCA Bits) This bit is to start the two 16-bit counters in the PCA. For customers who want 5 PWM, for example, this bit can start all of the PWM outputs. 6 EN_PCA 0 = PCA counter is disabled 1 = PCA counter is enabled EN_PCA Counter Run Control Bit. Set with software to turn the PCA counter on. Must be cleared with software to turn the PCA counter off. 5 EOVFI 1 = Enable Counter Overflow Interrupt if overflow flag (OVF) is set 4 PCAIDLE 0 = PCA operates when CPU is in Idle Mode 1 = PCA stops running when CPU is in Idle Mode 3 – Reserved 2 10B_PWM 0 = Select 16-bit PWM 1 = Select 10-bit PWM 1-0 CLK_SEL [1:0] 00 Select Prescaler clock as Counter clock 01 Select Timer 0 Overflow 10 Select External Clock pin (P4.3 for PCA0) (MAX clock rate = fOSC/4)uPSD33xx 130/231 Table 71. PCA1 Control Register PCACON1 (SFR 0BCh, Reset Value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – EN_PCA EOVFI PCAIDLE – – CLK_SEL[1:0] Details Bit Symbol Function 6 EN_PCA 0 = PCA counter is disabled 1 = PCA counter is enabled EN_PCA Counter Run Control Bit. Set with software to turn the PCA counter on. Must be cleared with software to turn the PCA counter off. 5 EOVFI 1 = Enable Counter Overflow Interrupt if overflow flag (OVF) is set 4 PCAIDLE 0 = PCA operates when CPU is in Idle Mode 1 = PCA stops running when CPU is in Idle Mode 3 – Reserved 2 10B_PWM 0 = Select 16-bit PWM 1 = Select 10-bit PWM 1-0 CLK_SEL [1:0] 00 Select Prescaler clock as Counter clock 01 Select Timer 0 Overflow 10 Select External Clock pin (P4.7 for PCA1) (MAX clock rate = fOSC/4)131/231 uPSD33xx Table 72. PCA Status Register PCASTA (SFR 0A5h, Reset Value 00h)uPSD33xx 132/231 TCM Interrupts There are 8 TCM interrupts: 6 match or capture interrupts and two counter overflow interrupts. The 8 interrupts are “ORed” as one PCA interrupt to the CPU. By the nature of PCA application, it is unlikely that many of the interrupts occur simultaneously. If they do, the CPU has to read the interrupt flags and determine which one to serve. The software has to clear the interrupt flag in the Status Register after serving the interrupt. Table 73. TCMMODE0 - TCMMODE5 (6 Registers, Reset Value 00h) Table 74. TCMMODE Register Configurations Note: 1. 10-bit PWM mode requires the 10B_PWM Bit in the PCACON Register set to '1.' Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] Details Bit Symbol Function 7 EINTF 1 - Enable the interrupt flags (INTF) in the Status Register to generate an interrupt. 6 E_COMP 1 - Enable the comparator when set 5 CAP_PE 1 - Enable Capture Mode, a positive edge on the CEXn pin. 4 CAP_NE 1 - Enable Capture Mode, a negative edge on the CEXn pin. 3 MATCH 1 - A match from the comparator sets the INTF bits in the Status Register. 2 TOGGLE 1 - A match on the comparator results in a toggling output on CEXn pin. 1-0 PWM[1:0] 01 Enable PWM Mode (x8), fixed frequency. Enable the CEXn pin as a PWM output. 10 Enable PWM Mode (x8) with programmable frequency. Enable the CEXn pin as a PWM output. 11 Enable PWM Mode (x10 or x16), fixed frequency. Enable the CEXn pin as a PWM output. EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0 TCM FUNCTION 0 0 0 0 0 0 0 0 No operation (reset value) 0 1 0 0 0 0 0 1 8-bit PWM, fixed frequency 0 1 0 0 0 0 10 8-bit PWM, programmable frequency 0 1 0 0 0 0 11 10-bit or 16-bit PMW, fixed frequency(1) X 1 0 0 1 1 0 0 16-bit toggle X 1 0 0 1 0 0 0 16-bit Software Timer X X 0 1 0 0 0 0 16-bit capture, negative trigger X X 1 0 0 0 0 0 16-bit capture, positive trigger X X 1 1 0 0 0 0 16-bit capture, transition trigger133/231 uPSD33xx PSD MODULE The PSD Module is stacked with the MCU Module to form the uPSD33xx, see uPSD33xx HARDWARE DESCRIPTION, page 13. Details of the PSD Module are shown in Figure 51. The two separate modules interface with each other at the 8032 Address, Data, and Control interface blocks in Figure 51. Figure 51. PSD Module Block Diagram PD1 PD2 PORT D PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PORT B PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 GENERAL PLD 20 INPUT MACROCELLS A B 16 OUTPUT MACROCELLS A B A B A B A B A B A B A B B C B C B C B C B C B C B C B C SECURITY LOCK PLD INPUT BUS PIN FEEDBACK NODE FEEDBACK PSD Module: uPSD33XX DECODE PLD AND-OR ARRAY FS0-7 AAAAAAAA BBBBBBBB C C C C TO PLD INPUT BUS PORT C PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 JTAG-ISP TO ALL AREAS OF PSD MODULE ADDR, DATA, CONTROL BUS LINKED TO 8032 MCU RUNTIME CONTROL, 256 REGs GPIO, VM, PAGE POWER MNGMT CSIOP PLD CSBOOT0-3 EXTERNAL CHIPSELECTS MAIN FLASH MEMORY Up to 8 SEGMENTS FS0 Up to 256 KBytes TOTAL FS7 2nd FLASH MEMORY Up to 4 SEGMENTS Up to 32 KBytes TOTAL CSBOOT0 CSBOOT3 DATA ADDRESS LATCH LOW ADDR HIGH ADDR 8032 MUX ADDR/DATA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 8032 HI ADDR A8 A9 A10 A11 A12 A13 A14 A15 8032 CNTL RD WR PSEN ALE RST 8032 MCU Module PORT A (80-pin only) TO JTAG DEBUG ON MCU GPIO PLD GPIO GPIO GPIO 8 PIN INPUTS MCU READ or WRITE MCU READ PLD OUT PLD OUT PLD OUT PLD OUT PLD OUT JTAG CNTL 8 PIN INPUTS 4 PIN INPUTS MCU READ or WRITE RS0 Up to 32 KBytes SRAM PAGE REG JTAG OMC ALLOCATOR AND-OR ARRAY 69 INPUTS 69 INPUTS AI07872B PLD INPUT BUSuPSD33xx 134/231 PSD Module Functional Description Major functional blocks are shown in Figure 51., page 133. The next sections describe each major block. 8032 Address/Data/Control Interface. These signals attach directly to the MCU Module to implement a typical multiplexed 8051-style bus between the two stacked die. The MCU instruction prefetch and branch cache logic resides on the MCU Module, leaving a standard 8051-style memory interface on the PSD Module. The active-low reset signal originating from the MCU Module goes to the PSD Module reset input (RST). This reset signal can then be routed as an external output from the uPSD33xx to the system PC board, if needed, through any one of the PLD output pins as active-high or active-low logic by specifying logic equations in PSDsoft Express. The 8032 address and data busses are routed throughout the PSD Module as shown in Figure 51 connecting many elements on the PSD Module to the 8032 MCU. The 8032 bus is not only connected to the memories, but also to the General PLD, making it possible for the 8032 to directly read and write individual logic macrocells inside the General PLD. Dual Flash Memories and IAP. uPSD33xx devices contain two independent Flash memory arrays. This means that the 8032 can read instructions from one Flash memory array while erasing or writing the other Flash memory array. Concurrent operation like this enables robust remote updates of firmware, also known as In-Application Programming (IAP). IAP can occur using any uPSD33xx interface (e.g., UART, I2C, SPI). Concurrent memory operation also enables the designer to emulate EEPROM memory within either of the two Flash memory arrays for small data sets that have frequent updates. The 8032 can erase Flash memories by individual sectors or it can erase an entire Flash memory array at one time. Each sector in either Flash memory may be individually write protected, blocking any WRITEs from the 8032 (good for boot and start-up code protection). The Flash memories automatically go to standby between 8032 READ or WRITE accesses to conserve power. Minimum erase cycles is 100K and minimum data retention is 15 years. Flash memory, as well as the entire PSD Module may be programmed with the JTAG In-System Programming (ISP) interface with no 8032 involvement, good for manufacturing and lab development. Main Flash Memory. The Main Flash memory is divided into equal sized sectors that are individually selectable by the Decode PLD output signals, named FSx, one signal for each Main Flash memory sector. Each Flash sector can be located at any address within 8032 program address space (accessed with PSEN) or data address space, also known as 8032 XDATA space (accessed with RD or WR), as defined with the software development tool, PSDsoft Express. The user only has to specify an address range for each segment and specify if Main Flash memory will reside in 8032 data or program address space, and then PSEN, RD, or WR are automatically activated for the specified range. 8032 firmware is easily programmed into Main Flash memory using PSDsoft Express or other software tools. See Table 75., page 135 for Main Flash sector sizes on the various uPSD33xx devices. Secondary Flash Memory. The smaller Secondary Flash memory is also divided into equal sized sectors that are individually selectable by the Decode PLD signals, named CSBOOTx, one signal for each Secondary Flash memory sector. Each sector can be located at any address within 8032 program address space (accessed with PSEN) or XDATA space (accessed with RD or WR) as defined with PSDsoft Express. The user only has to specify an address range for each segment, and specify if Secondary Flash memory will reside in 8032 data or program address space, and then PSEN, RD, or WR are automatically activated for the specified range. 8032 firmware is easily programmed into Secondary Flash memory using PSDsoft Express and others. See Table 75., page 135 for Secondary Flash sector sizes. SRAM. The SRAM is selected by a single signal, named RS0, from the Decode PLD. SRAM may be located at any address within 8032 XDATA space (accessed with RD or WR), or optionally within 8032 program address space (accessed with PSEN) to execute code from SRAM. The default setting places SRAM in XDATA space only. These choices are specified using PSDSoft Express, where the user specifies an SRAM address range. The user would also specify (at run-time) if SRAM will additionally reside in 8032 program address space, and then PSEN, RD, or WR are automatically activated for the specified range. See Table 75., page 135 for SRAM sizes. The SRAM may optionally be backed up by an external battery (or other DC source) to make its contents non-volatile (see SRAM Standby Mode (battery backup), page 193).135/231 uPSD33xx Table 75. uPSD33xx Memory Configuration Runtime Control Registers, CSIOP. A block of 256 bytes is decoded inside the PSD Module for module control and status (see Table 79., page 145). The base address of these 256 locations is referred to in this data sheet as csiop (Chip Select I/O Port), and is selected by the Decode PLD output signal, CSIOP. The csiop registers are always viewed by the 8032 as XDATA, and are accessed with RD and WR signals. The address range of CSIOP is specified using PSDsoft Express where the user only has to specify an address range of 256 bytes, and then the RD or WR signals are automatically activated for the specified range. Individual registers within this block are accessed with an offset from the specified csiop base address. 39 registers are used out of the 256 locations to control the output state of I/ O pins, to read I/O pins, to set the memory page, to control 8032 program and data address space, to control power management, to READ/WRITE macrocells inside the General PLD, and other functions during runtime. Unused locations within csiop are reserved and should not be accessed. Memory Page Register. 8032 MCU architecture has an inherent size limit of 64K bytes in either program address space or XDATA space. Some uPSD33xx devices have much more memory that 64K, so special logic such as this page register is needed to access the extra memory. This 8-bit page register (Figure 52) can be loaded and read by the 8032 at runtime as one of the csiop registers. Page register outputs feed directly into both PLDs creating extended address signals used to “page” memory beyond the 64K byte limit (program space or XDATA). Most 8051 compilers directly support memory paging, also known as memory banking. If memory paging is not needed, or if not all eight page register bits are needed for memory paging, the remaining bits may be used in the General PLD for general logic. Page Register outputs are cleared to logic ’0’ at reset and powerup. Programmable Logic (PLDs) . The uPSD33xx contains two PLDs (Figure 63., page 157) that may optionally run in Turbo or Non-Turbo mode. PLDs operate faster (less propagation delay) while in Turbo mode but consume more power than in Non-Turbo mode. Non-Turbo mode allows the PLDs to go to standby automatically when no PLD inputs are changing to conserve power. The logic configuration (from equations) of both PLDs is stored with non-volatile Flash technology and the logic is active upon power-up. PLDs may NOT be programmed by the 8032, PLD programming only occurs through the JTAG interface. Figure 52. Memory Page Register Device